A Wide Tuning-Range mm-Wave LC-VCO Sized Using

Evolutionary Algorithms

A Thesis

Presented in Partial Fulfillment of the Requirements for the DegreeHonors Research Distinction in the The Ohio State University

By

Matthew R. Belz,

Undergraduate Program in Electrical and Computer Engineering

The Ohio State University

2019

Research Distinction Committee:

Dr. Waleed Khalil, Advisor

Dr. Steven Bibyk

Dr. Tawfiq Musah

c© Copyright by

Matthew R. Belz

2019

Abstract

Designing a LC Voltage Controlled Oscillator (LC-VCO) for mm-Wave frequencies

requires a careful balance of interdependent design parameters. The losses due to

passive elements dictate the required cross coupled pair transconductance (gm), which

in turn affects the tuning range via fixed capacitance. As such, the design process

requires significant engineering time. An optimization methodology using a genetic

algorithm is proposed to optimize component selection for use in the LC-VCO. The

design for the LC-VCO is broken into pseudo-independent sub-modules to allow the

designer greater control and to allow the optimization to benefit from manual circuit

intuition. Performance of the components chosen by the genetic algorithm is verified

using a circuit simulator to achieve a center frequency of 29 GHz with a 15.8 GHz

tuning range. The simulated phase noise performance is -103.2 dBc/Hz using a 10

MHz frequency offset.

ii

Acknowledgments

First I would thank my parents who have always supported my scientific endeavors

and academic pursuits. They always pushed me to do my best work and without them

I wouldn’t have made it this far.

All the members of the Circuit Lab for Advanced Sensors and Systems (CLASS)

have not only been incredible mentors, but also great friends. Our casual conver-

sations have given me many useful insights. I also have learned so much from the

now graduated students Dr. Matt LaRue, Dr. Luke Duncan, and Dr. Jamin McCue

who all were very open to my questions when I was just starting in the group. Dr.

Shahriar Rashid helped me understand some of the basics of RF design during our

chats and whiteboard sessions about VCOs. I really appreciate your willingness to

help me understand the concepts at a fundamental level.

I would especially like to thank Gus Fragasse for his help on my VCO modeling

paper. There were a few times when the simulations weren’t working, and I thought

I would not make the deadline. Gus patiently helped me debug, and encouraged me

to keep plugging away—for this I am very grateful.

When I first started making my own electronic gadgets as an electrical engineering

major Dr. Steve Bibyk helped guide me when I got stuck. Thanks for all the support

over the years.

I also would like to thank Dr. Tawfiq Musah for serving on my defense committee.

iii

Finally, I would like to thank my advisor Dr. Waleed Khalil. As an undergrad at

such a large institution it is easy to get lost and Dr. Khalil was always there to help

me make decisions about class choices, graduate school, and how to develop my skills

to be successful in my later career. Dr. Khalil is passionate about electronics and

also cares deeply about each of his students, there’s not much more one can wish for

in an advisor.

iv

Table of Contents

Page

Abstract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ii

Acknowledgments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii

List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vii

List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . viii

1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.1 Clock Generation in Hardware . . . . . . . . . . . . . . . . . . . . 2

2. LC-VCO With C-DAC Optimization . . . . . . . . . . . . . . . . . . . . 5

2.1 LC-VCO Design Methodology . . . . . . . . . . . . . . . . . . . . . 62.2 Genetic Algorithm Design . . . . . . . . . . . . . . . . . . . . . . . 82.3 VCO GA Optimization Setup . . . . . . . . . . . . . . . . . . . . . 10

2.3.1 Cost Surface Generation . . . . . . . . . . . . . . . . . . . . 112.3.2 Cost Function Derivation . . . . . . . . . . . . . . . . . . . 12

2.4 Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3. Conclusions and Future Work . . . . . . . . . . . . . . . . . . . . . . . . 22

3.1 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223.2 Broader Impacts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223.3 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

v

Appendices 25

A. Collaboration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

B. MATLAB Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Bibliography . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

vi

List of Tables

Table Page

2.1 Optimized VCO Component Sizes . . . . . . . . . . . . . . . . . . . . 20

2.2 Fitness Objectives and Results . . . . . . . . . . . . . . . . . . . . . . 21

2.3 Performance Comparison to Manually Designed LC-VCOs . . . . . . 21

vii

List of Figures

Figure Page

1.1 Simplified PLL Model . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.2 Homodyne Transmitter Model . . . . . . . . . . . . . . . . . . . . . . 3

2.1 LC-VCO Architectusing a 10 MHz frequency offset.ure . . . . . . . . 6

2.2 Genetic Algorithm Encoding Process . . . . . . . . . . . . . . . . . . 10

2.3 Crossover and Mutation Illustration . . . . . . . . . . . . . . . . . . . 10

2.4 VCO Optimization Algorithm . . . . . . . . . . . . . . . . . . . . . . 12

2.5 Varactor Cost Surfaces . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.6 Inductance Cost Surfaces . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.7 Fit Surface for Cross-Coupled Pair Width . . . . . . . . . . . . . . . 16

2.8 Fit Function for Cross Coupled Pair Parasitic Capacitance . . . . . . 16

2.9 Sized VCO Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.10 Simulated Tuning Curves of the GA-optimized VCO . . . . . . . . . 17

2.11 Simulated VCO Phase Noise Performance . . . . . . . . . . . . . . . 17

2.12 Genetic Algorithm Convergence . . . . . . . . . . . . . . . . . . . . . 18

2.13 Oscillation of VCO . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

viii

Chapter 1: Introduction

As demand increases for mm-Wave communication links such as the emerging

5th Generation cellular standard (5G) and automotive RADAR, CMOS-based wide

tuning range (TR) mm-wave Voltage Controlled Oscillators (VCOs) are positioned

to become an integral part of next generation System on Chips (SoCs) [1, 2]. The

increasing use of wireless technologies such as Wi-Fi, Bluetooth, and Cellular along

with the demand for higher data rates has led to spectrum crowding. Moving up

in frequency to the mm-Wave bands is a current trend since it will allow for higher

data rates due to the larger availability of open spectrum. The frequency range for

mm-Wave is roughly defined between 30 and 300 GHz.

Designing an integrated voltage controlled oscillator (VCO), a critical component

to any wireless system, requires many engineering hours to tune so it will meet the

required specifications. Like many analog circuits, the design process for the VCO

necessitates a careful balance of interdependent factors. If one component is changed

such as the varactor to increase the tuning range, several other parameters will need

to be updated such as the transconductance from the cross coupled pair as a larger

varactor will reduce the parallel resistance of the tank. This will in turn increase the

tank capacitance and reduce both the operating frequency and tuning range [1]. This

1

is one example of how the design of a VCO becomes a circular relationship and can

be difficult to break.

While there are many different types of voltage controlled oscillators, the topology

used in this work uses an LC tank and a negative resistance element. The LC-VCO

approach is widely used for high frequency applications and is well suited for mm-

Wave operation [1]. This work is focused on a design automation approach to reduce

the number of design iterations and overall design time for the LC-VCO.

1.1 Clock Generation in Hardware

An accurate frequency reference is required for data transmission and reception

in both wireline and wireless domains. Crystal oscillators are used to generate fre-

quency references with accuracy on the order of 0.1-10’s of parts per million. Nev-

ertheless, crystal oscillators resonate at a particular fixed frequency, well below the

single GHz range. In order to generate an adjustable frequency reference suitable for

high-frequency data transmission, a phase locked loop (PLL) is often used. The PLL

seen in Figure 1.1, takes an ultra-stable reference, often a precision crystal, and then

uses a feedback loop to reduce phase errors from the VCO. The difference between

the RF output phase and the reference is measured using the error detection block in

Figure 1.1. The phase difference is measured by the phase detector (PD) and the PLL

corrects for this difference using the charge pump (CP). The CP generates a control

voltage which will adjust the frequency of the VCO. The output frequency from the

VCO is divided for the error detection stage using the divide by N block where N

can be either integer or fractional. After an initial startup period, the PLL is ide-

ally locked to the accuracy of the reference signal and produces an output waveform

2

Figure 1.1: Simplified PLL Model

suitable for high-speed clocks and data transmissions. The PLL can then be used

as a local oscillator (LO) for wireless transmitters such as the homodyne transmitter

seen in Figure 1.2. The homodyne transmitter takes a baseband signal and directly

upconverts to the RF frequency for use in wireless standards such as Bluetooth.

Figure 1.2: Homodyne Transmitter Model

3

The gain of the VCO is denoted Kvco and represents the slope of the line when

the output frequency is plotted vs. the control voltage. In other words, Kvco shows

how sensitive the output frequency is for a given change in the control voltage. Since

the oscillation frequency is 12π

√LC

either the inductor or capacitor can adjust the op-

eration frequency. In practice, due to the difficulty of adjusting on-chip inductors,

an adjustable capacitor is used for the frequency adjustment. In this work an accu-

mulation mode varactor is used to change the capacitance of the tank and thus the

operation frequency [3].

4

Chapter 2: LC-VCO With C-DAC Optimization

The work in [4] presents a multi-objective algorithm to optimize the trade-off

between power consumption and phase noise reflected in the Figure of Merit (FOM)

for the VCO. After optimization, the FOM was comparable with previous state of the

art designs. However, the VCO tuning range is a critical parameter of performance

and its optimization has not been explored.

In this work, an optimization technique is presented which includes a segmented

capacitive digital to analog converter (C-DAC). In this topology, the C-DAC is used

to achieve low phase noise and wide tuning range simultaneously [5]. The framework

selected for optimization is a multi-objective genetic algorithm (GA), which is used

to optimize the TR and tank quality factor by determining the best component sizes

for the LC-VCO topology as presented in Figure 2.1. Unlike the TR parameter, the

PN of the VCO is not automatically optimized using a cost function, but rather it

is optimized by using a small value of inductance and using a C-DAC to ensure a

low Kvco. The addition of PN into the optimization is discussed in the future work

section.

The optimization methodology proposed in this work has a runtime on the or-

der of one minute compared to several hours reported previously [4, 6]. The runtime

5

Figure 2.1: LC-VCO Architectusing a 10 MHz frequency offset.ure

is reduced since the evolutionary algorithm optimizes based on cost surfaces devel-

oped using prior simulation data rather than using the simulator to evaluate the cost

function for each generation. This allows for an optimization based on simulation

data for each block rather than relying on analytical equations that suffer from gross

simplifications.

2.1 LC-VCO Design Methodology

A bottom-biased LC-VCO topology, presented in Figure 2.1, is the subject of

the optimization in this work. A symmetric, center-tapped inductor is used for the

inductive element in the VCO. At mm-Wave frequencies, only a single turn is required,

thus, eliminating this variable from the search space. Additionally, since the PN is

6

inversely proportional to the inductance of the tank inductor, the value of inductance

is minimized within the geometric allowances of the process design kit in a pre-

processing optimization step [1].

The use of a single varactor element to provide a tuning range sets a limit on the

achievable PN performance due to amplitude modulation to phase modulation (AM

to PM) conversion from the large tuning curve slope Kvco [7]. Reducing Kvco while

maintaining a large tuning range is achieved by digitally switching fixed capacitors

for coarse tuning, and using a varactor for fine tuning. To ensure operation across

process voltage and temperature (PVT) as well as parasitic variations, the varactor

is sized for 30 to 50 percent frequency overlap between the tuning curves.

The number of tuning curves are determined prior to running the evolutionary al-

gorithm and represents a trade-off between tuning resolution and tuning range. While

increasing the number of tuning curves results in a finer coarse tuning resolution, it

also adds parasitic capacitance and inductance due to the feed line network [5]. This

parasitic capacitance becomes significant at mm-Wave frequencies and ultimately

limits the tuning range. Additionally, the use of more tuning curves will increase

the frequency tuning time since the search space to find the correct tuning curve is

increased. The optimum number of tuning bits is typically between four and six.

In this work, we use a 5-bit C-DAC resulting in 31 coarse tuning curves. The C-

DAC is implemented as a segmented DAC where the two least significant bits (B0-B1)

are binary to save area while the three most significant bits (T0-T6) are thermometer

coded to reduce mismatch between tuning curves [8]. The schematic for a digitally

switched capacitor cell used in the C-DAC is shown in the inset of Figure 2.1. A trade-

off exists between the switch transistor size and the unit capacitor quality factor.

7

When the transistor is very wide, the resistance is low, however, the gate capacitance

also increases lowering the ratio between CON and COFF states leading to a smaller

tuning range. To balance this trade-off, we desire the CON/COFF ratio to be around

three.

The cross coupled NMOS pair is designed to compensate for the losses due to

the passive elements of the tank in the form of a negative resistance. To satisfy the

Barkhausen criterion for oscillation across PVT variations, a design margin of two is

used. In short channel technologies, there is only a weak dependence on current to

increase the gm, therefore the width of the cross coupled pair devices is used to obtain

the necessary transconductance [1]. The resulting capacitance from the cross-coupled

pair (Cxcpl) is added as fixed capacitance in the GA evaluation. This fixed capacitance

accounts for shifts in center frequency and tuning range. This is a critical step since

Cxcpl accounts for around 38% of the total capacitance of the tank at 30 GHz [1], [9].

2.2 Genetic Algorithm Design

Genetic algorithms are a class of evolutionary algorithms that optimize a popu-

lation of individuals stochastically without the use of hill-climbing methods such as

gradient descent or Newton’s Method. In each generation a population is created, in

this work 200 each generation consists of 200 individuals. This type of optimization

algorithm is well suited to problems such as circuit design, which is characterized by

a large search space, especially when a topology is not specified, with many local min-

ima. The goal of a genetic algorithm is to find the region of highest population fitness

and therefore allows for suboptimal individuals to exist in order to further explore the

search space and avoid becoming stuck in local minima. After discovering the region

8

of lowest cost, or equivalently the highest fitness, a gradient-descent method can be

used to find the lowest cost individual in that generation. Despite the fact that genetic

algorithms can not provide a provably optimal solution, they are well suited to circuit

design problems due to the complexity and size of the solution space [6]. Individual

parameters are encoded into a chromosome which can be a binary string or floating

point value. Due to the possibility of Hamming cliffs, floating point and integer values

are used for chromosome encoding in our algorithm design [10]. Selection is performed

using a stochastic uniform distribution with a selection of parent chromosomes mod-

ified using crossover and mutation. Crossover allows for the combination of current

generation genes to form new children. Using crossover, a chromosome with a subop-

timal gene (e.g. varactor width) could be paired with a different complementary gene

(e.g. varactor number of fingers) to generate a superior overall solution. Crossover

does not add new individual genes to the pool but just switches existing genes from

different chromosomes to form a new individual. Mutation introduces small changes

in the chromosome to explore the search space further. These mechanisms are shown

visually in Figure 2.3. For the genetic algorithms used in this study, the most fit

individual is carried over to the next generation unchanged (elitism). This ensures

that the best fitness of the population is always increasing even if the population

overall has decreasing fitness as local minima are encountered.

The cost function is the core of any genetic algorithm and determines how individ-

uals are selected and propagated through new generations. In the genetic algorithm

design, the cost function is minimized or equivalently the fitness is maximized. A

weighted sum of fitness functions are used to create a multi-objective optimization

9

Figure 2.2: Genetic Algorithm Encoding Process

Figure 2.3: Crossover and Mutation Illustration

algorithm [11]. The fitness functions used for this optimization approach are shown

in the genetic algorithm application section.

2.3 VCO GA Optimization Setup

To optimize the VCO, a genetic algorithm is used to solve the multi-objective op-

timization problem by setting fitness goals for each sub-block (C-DAC, cross coupled

pair, inductor, and varactor) of the VCO according to the design practices discussed

in section 2.1. A population size of 200 individuals was used and the individual with

the highest fitness is carried into the next generation. The bounds for the optimizaion

10

are set according to the allowed geometry range from the process design kit (PDK)

or a known feasibility region whichever is more restrictive. Parameters such as the

number of fingers for the varactor are restricted to integers, while continuous valued

variables (e.g. varactor width) are optimized as floating point numbers.

2.3.1 Cost Surface Generation

To construct cost surfaces for the genetic algorithm, we utilized simulation data

from a 45nm CMOS SOI process to create fit surfaces as a function of geometric de-

sign parameters. While predictive process design kits and extensions of long channel

models can be applied to understand trends in short channel devices, the viability of

a component selection algorithm requires simulation with empirically-backed models.

Many component selection methods utilize circuit simulators with in-loop optimiza-

tion to meet this requirement [4,6]. The drawback is that in-loop simulation methods

require significant overhead since electromagnetic and circuit simulations are much

more computationally intensive compared to equation based evaluation. Addition-

ally, this computational load can not be performed in parallel since the next circuit

configuration chosen by the GA is based on the results of the previous iteration. To

address this problem, we have collected a large multidimensional matrix of simulation

test data that is then interpolated using linear or spline methods to produce a con-

tinuous surface as a function of the geometric dimensions. Simulation times for the

sweeps used to generate the cost surfaces are all under 5 minutes for each sub-block

and the GA optimization runs in under one minute.

11

Figure 2.4: VCO Optimization Algorithm

(a) Varactor CV Characteristic (b) Varactor Rp Function

Figure 2.5: Varactor Cost Surfaces

2.3.2 Cost Function Derivation

A flowchart representation of the algorithm used to optimize the VCO is shown in

Figure 2.4. A linear combination of cost functions are used to enable multi-objective12

(a) Inductance Cost Surface (b) Inductor Rp Function

Figure 2.6: Inductance Cost Surfaces

optimization that align with key objectives from the manual design [11]. This ap-

proach is used to tune the VCO more precisely than could be achieved by tuning a

FOM as the sole cost function. Since the desired oscillation frequency is known prior

to design, the data extracted from the circuit simulator is taken at this frequency to

reduce the dimensionality of the data. However, some parameters such as Rp,L are

averaged over the expected tuning range to account for changes during tuning.

The genetic algorithm attempts to minimize the cost function through crossover

and mutation of the parameters in the vector X, which is shown in (2.1). The inductor

value and Rp,L are determined in a pre-processing step using the cost surfaces for the

inductor.

X = [NFsw, Lcap,Wvar, NFvar] (2.1)

NFsw is the number of fingers for the digital switching transistor inside the metal-

oxide-metal (MOM) capacitor structure and Lcap is the length of the MOM capacitors.

13

Increasing the width of the MOM capacitor significantly degrades the Rp, so it is fixed

throughout the optimization. Wvar is the varactor width and NFvar is the number of

fingers for the varactor.

For cost functions, binary true or false values are not particularly useful for a

genetic algorithm as they do not indicate how close the current solution is to the

ideal case. To give the algorithm feedback during the iteration process, the absolute

value of the difference between the current solution and target value is used. This

strategy was adopted for the overlap between curves, center oscillation frequency and

Con/Coff ratio. As the GA improves the solutions, the absolute difference between

the current and target solutions will approach zero, therefore minimizing the cost

function.

To determine the overlap between coarse tuning curves, the top two frequency

curves are used since they represent the worst case overlap. To calculate the parallel

resistance of the tank, the worst case is taken when all digital caps are ON. To

compute the required transconductance from the cross coupled pair, the parallelRp,ON

combination is used, which also reveals the resulting transistor width and parasitic

Cxcpl.

The cost function that is used to optimize the VCO is shown in Equation 2.2. The

α values are used to normalize the cost function such that large values like tuning

range do not dominate the cost. If the cost function is not properly normalized only a

select few of the optimization objectives will be met. For example since TR is on the

order of 1E9, smaller optimization targets such as the Con/Coff ratio will be ignored.

Cost = α1|3−ConCoff

|+ α2

Rp,cap

+α3

Rp,var

+α4|28GHz−fmid|+α5|0.4−overlap|+α6

TR(2.2)

14

The tuning range is specified from the middle region (50% varactor) of the top

and bottom curves. The use of the middle instead of the extremes of the tuning

curves was chosen as to minimize the impact of Kvco since the tuning range could

be extended by making Kvco very large when measuring at the extreme points of the

curves.

Once the resonant tank is determined, the cross-coupled pair can be sized based

on the total parallel resistance of the tank. In this case the design margin in Equation

2.3 is two. The required gm is used along with the fit functions of Figures 2.7 and 2.8

to find the width of the cross coupled pair devices and the added parasitic capacitance

respectively. This parasitic capacitance is voltage dependent so this parasitic analysis

could be made more accurate by running a transient and then averaging the parasitic

capacitance, for this study the Cxcpl was determined using an ac analysis.

gm =2

Rp,T

(2.3)

2.4 Results

The operation of the LC-VCO optimized and sized using the GA has been tested

in a circuit simulator to verify the performance given as output from the GA. The

sizes chosen for the VCO core by the GA are shown in Table 2.1. To illustrate the

tuning characteristics for the GA design VCO, the tuning curves are presented in

Figure 2.10. The simulated TR aligns with the range given from the GA simulation

as they are both 15.8 GHz. It is important to note that the tuning range will be

reduced once extracted layout parasitics, which are outside the scope of this work,

are added. The tuning range will still be maximized through this algorithm, but the

15

Figure 2.7: Fit Surface for Cross-Coupled Pair Width

Figure 2.8: Fit Function for CrossCoupled Pair Parasitic Capacitance

inclusion of extracted layout parasitics will provide for a more accurate value for the

tuning range. The PN is presented in Figure 2.11. Since the PN is not explicitly

optimized in the cost functions of the GA, it is expected that increased performance

can be achieved if this objective is included in a future version. At an offset of 10

MHz the PN performance is -103.2 dBc/Hz. Using the equation for FOMT shown in

Equation 2.4, the LC-VCO achieves a FOMT of -181.2 dBc/Hz when simulating PN

at 10 MHz offset and a center frequency of 28 GHz.

FOMT = PN − 20log

(f0∆f· TR

10

)+ 10log

(P

1mW

)(2.4)

The generation of interpolated fitness functions, particularly in the varactor, is

attributed to the slight error between the frequency predicted in the GA model vs. the

simulated LC-VCO, which was approximately 0.6 GHz for the maximum frequency.

Since the GA needs to fit functions across a high-dimensional matrix there is some

16

Figure 2.9: Sized VCO Design

Figure 2.10: Simulated TuningCurves of the GA-optimized VCO

Figure 2.11: Simulated VCO PhaseNoise Performance

17

Figure 2.12: Genetic Algorithm Convergence

error in any individual curve, and is observed to be limited to a difference of under

5 fF. The algorithm is found to converge to an optimal region rather quickly as

evidenced by the convergence plot presented in Figure 2.12. The lowest penalty

(cost) is monotonically decreasing since the individual with the highest fitness is

always carried into the next generation. The simulated startup and steady state

oscillation of the VCO designed by the GA is presented in Figure 2.13 and shows the

positive and negative output nodes.

2.5 Conclusion

A genetic algorithm using a weighted sum of interpolated cost surfaces is shown to

produce a sized LC-VCO designed for applications requiring a wide TR. This LC-VCO

uses a C-DAC for coarse tuning to allow for a wide TR and low PN. Cost functions

18

Figure 2.13: Oscillation of VCO

19

Table 2.1: Optimized VCO Component Sizes

Variable Optimized ResultNFsw 19Lcap 59.8µmWvar 1.328µmNFvar 9Wxcpl 12.77µm

Ind. Outer Dimension 100µmInd. Width 12.25µmInductance 130.7 pH

Unit Switch Cap (C) 12.4 fFVaractor Low 14.79 fFVaractor High 46.6 fF

based on simulation data are used to provide accurate modeling for component se-

lection while allowing for fast fitness evaluation. Techniques from manual design are

translated into a genetic algorithm to reduce the search space and aid in convergence.

The resulting sized VCO is then simulated in a circuit simulator to verify the results

obtained through the genetic algorithm. This simulation shows the TR is found to

be 15.8 GHz and the PN at 10 MHz offset is -103.2 dBc/Hz. The PN is not modeled

in MATLAB however the TR model in MATALB matches almost exactly with the

simulated tuning range. Enhancements to the optimization algorithm could improve

accuracy by including fitness metrics for phase noise and additional parasitics due to

layout.

20

Table 2.2: Fitness Objectives and Results

Variable Goal Simulation ResultCon/Coff ratio 3 3.84Tuning Range Maximize 15.8 GHz

Center Frequency 28 GHz 29 GHzRp,var Maximize 467.98 ΩRp,cap Maximize 5.34 kΩ

Current Consumption Minimize 5 mA

Table 2.3: Performance Comparison to Manually Designed LC-VCOs

Ref. Tech.CenterFreq.(GHz)

PN @10 MHzOffset

(dBc/Hz)

TR(%)

OutputPower(mW)

FOMT

[12] 32 nm SOI 24.7 -127.3 22.9 24 -188.6[13] 32 nm SOI 28 -110 22 31 181.2[14] 45 nm CMOS 24.8 -121 25 12.1 -186.0[15] 130 nm CMOS 40 -115 27 12 -184.9[16] 32 nm CMOS 39.9 -118 31.6 9.8 -190.1ThisWork

45 nm SOI 28 -103.2 56.4 5 -181.2

21

Chapter 3: Conclusions and Future Work

3.1 Summary

This work has presented a methodology for rapidly designing a VCO suitable for

use at mm-Wave frequencies. The segmented C-DAC topology described in Chapter

3 allows for a wide TR while maintaining low PN. Cost surfaces based on simulation

data allow for rapid fitness evaluation while still maintaining a high level of accuracy.

Additionally, this allows for rapid re-designs in new technology nodes by updating

the cost surface data from the circuit simulator.

3.2 Broader Impacts

The design of a VCO is a time consuming process and also requires expert knowl-

edge to complete a working design. In industry, time-to-market is often a critical

factor and using an evolutionary algorithm such as presented in this work can reduce

the design time by determining a good starting point for further manual tuning if

required. This can especially be helpful when a new technology node is used since

the designer will need to learn new guidelines on how the device sizes correlate to

performance.

22

Defense contractors and government labs also may find this work useful since

their focus is based on missions which are constantly changing. The ability to design

a custom ASIC without expert designers in every RF sub-block is a topic of current

research through the DARPA electronics resurgence initiative (ERI). In defense ap-

plications, some performance degradation from the state-of-the-art may be tolerable

as long as the mission requirements are met.

Both industry and government labs could benefit from the ability to use artificial

intelligence for circuit design by reducing the required engineering hours and free up

designers to consider more creative architectures instead of manually perturbing the

component sizes to determine the optimal conditions.

3.3 Future Work

As technology nodes continue to scale, simulations based on schematic designs are

becoming increasingly poor at predicting performance as layout parasitics become

more dominant. Currently the GA uses parametric sweep data from a schematic-level

simulation and assumes proper layout will give the designer similar (but degraded)

performance. If the layout is generated along with the schematic representation, the

parasitics due to the layout can also be considered leading to a more accurate in-

dication of performance once the device is fabricated. Additionally, for mm-Wave

frequencies the inductor and feed line network should be measured using an electro-

magnetic (EM) simulator and included during the optimization. For this work it was

assumed that the PDK inductor simulation was sufficiently accurate and the feed line

parasitics were negligible. The Berkeley Analog Generator would be a good platform

23

to build a layout aware GA since it has interfaces to both circuit and EM simulators

using layout extracted parasitics in simulation runs [17].

While the GA optimizes for the component sizing, there are still several aspects

which must be designed manually such as the biasing circuitry. The bias circuits not

only have a significant impact on the noise of the device [18], but they also impact

the figure of merit through the power consumption. If the bias current is added as a

parameter in the algorithm, the power consumption could also be optimized automat-

ically instead of tuning based on designer intuition. By optimizing the bias current

the PN can also be minimized by operating at the boundary between the current

limited and voltage limited operating regions for the VCO. Additionally second order

effects such as supply pushing are not considered, but are a critical specification for

many applications.

24

Appendix A: Collaboration

This appendix discusses the collaboration during the completion of this work. The

circuit field is moving away from absolute maximum circuit performance to generator

based design where a circuit generator can design several different custom circuits

based on an initial topology to serve different application requirements. My work

has been some of the first at the CLASS group to address this growing need in the

circuit community for rapid design and optimization. Dr. Shahriar Rashid helped

me to understand the details of traditional circuit design, and in turn, I was able

to further his understanding of how the design space can be mapped into an opti-

mization framework. A similar collaboration occurred with Saeed Alzahrani who also

specializes in VCO design. Over the summer I also did some preliminary work for

VCO optimization with layout parasitics using the Berkeley Analog Generator. This

required installing and customizing environments on our servers to run. Dr. Luke

Duncan later used the BAG environment that I helped setup for his own projects.

25

Appendix B: MATLAB Code

This appendix lists the most important MATLAB scripts and functions required

for the genetic algorithm. The main function is VCO main GA3.m and this is where the

GA run is initiated. This function will call all other necessary functions for the opti-

mization. VCO fitness5.m is the function that determines the fitness of any given so-

lution. The scripts import digitalCapSweep min5mA2.m and S parameter Cleanup.m

are import scripts which do some processing so they are also included for complete-

ness.

code/VCO main GA3.m

1 % Main GA S c r i p t f o r VCO with d i g i t a l tuning caps2 % Matthew Belz 2/22/201934 %[ f itresult CAPH , gof1 ] = fitDigCapWL (w, capL , CapEQ high ) %

Overa l l cap HIGH t r a n s i s t o r dependance5 close a l l67 %f i t f u n c t i o n s f o r the switched cap un i t8 [ f itCapHigh , go f1 ] = fitDigCapWL2 (NF, capL , CapEQ high )9 [ fitCapLow , gof2 ] = fitDigCapWL2 (NF, capL , CapEQ low)

10 [ fitRpON , gof3 ] = fitDigCapWL2 (NF, capL , RP ON EQ)11 [ fitRpOFF , gof4 ] = fitDigCapWL2 (NF, capL , RP OFF EQ)12 [ f itm , go f5 ] = fitDigCapWL2 (NF, capL , mEQ)1314 % Fit f u n c t i o n s f o r c ros s−coupled pa i r15 [ fitGMxWid y , go f ] = fitGMxWxcplY(Gm, Wxcpl ) ;16 [ f itCxcplusingGm , go f ] = gmXCxcplY(Gm, Cxcpl ) ;17

26

1819 % [NF, CapL , varW , varNF ]202122 lb1 =[1 ,3 .2 e−6, 2 .56 e−7, 1 ] ; %l a s t element i s f i x e d cap23 ub1 =[20 ,60 e−6, 10e−6, 2 0 ] ;2425 % L f o r now s e t26 % l a r g e s t width and s m a l l e s t outer dimension s imulated

inductance at 28G27 L=130.7e−12;28 L rp= RpIND avg ; % average Rp f o r OD=100u , Wid=12.25u f r e q

sweep 22−32GHz2930 opts1= opt imopt ions (@ga , . . .31 ’ Popu lat ionS ize ’ , 200 , . . .32 ’ MaxGenerations ’ , 60 , . . .33 ’ El i teCount ’ , 2 , . . .34 ’ Const ra intTo le rance ’ , 5 , . . .35 ’ Funct ionTolerance ’ , 5 , . . .36 ’ PlotFcn ’ , @gap lotbes t f ) ;37 % rng (0 , ’ tw i s t e r ’ ) ;38 [ xbest , fbe s t , e x i t f l a g ] = ga (@( x ) VCO fitness5 (x , f itCapHigh ,

fitCapLow , fitRpON , fitRpOFF , fitm , fitCV0 , fitCV05 , fitRP02 ,f i tCV50percent , fitGMxWid y , fitCxcplusingGm , L , L rp ) , 4 ,[ ] , [ ] , [ ] , [ ] , . . .

39 lb1 , ub1 , [ ] , [ 1 , 4 ] , opts1 ) ;

code/VCO fitness5.m

1 function re tVal = VCO fitness5 (x , f itCapHigh , fitCapLow , fitRpON, fitRpOFF , fitm , fitCV0 , fitCV05 , fitRP02 , f i tCV50percent ,fitGMxWid y , fitCxcplusingGm , L , L rp )

2 % VCO Fi tne s s with switched caps3 % Matthew Belz 2/23/201945 % X = [ tranNF , CapL , varW , varNF ]67 %8 disp ( x (1 )+ ” ” + x (2) )9 C u n i t r a t i o = f i tm ( x (1 ) , x (2 ) )

10 %uni t cap C − b i t b011 C uni t h igh = fitCapHigh ( x (1 ) , x (2 ) )12 C unit low = fitCapLow ( x (1 ) , x (2 ) )

27

13 % b i t b1 , 2C14 C unit h igh2=fitCapHigh ( x (1 ) , x (2 ) ) ∗2 ;15 C unit low2=fitCapLow ( x (1 ) , x (2 ) ) ∗2 ;16 % Thermo b i t s , 4C17 C unit h igh4=fitCapHigh ( x (1 ) , x (2 ) ) ∗4 ;18 C unit low4=fitCapLow ( x (1 ) , x (2 ) ) ∗4 ;192021 % Rp122 Rp2=fitRpOFF ( x (1 ) , x (2 ) )2324 Rp unit=fitRpON ( x (1 ) , x (2 ) ) ; % For C25 Rp 4unit=fitRpON ( x (1 ) , x (2 ) ) /4 ; % f o r 4C26 Rp 2unit=fitRpON ( x (1 ) , x (2 ) ) /2 ; %f o r 2C272829 % VARACTOR30 %Measured s i n g l e−ended with s i n g l e varac to r so I d i v id e by 231 C var high = fitCV05 ( x (3 ) , x (4 ) ) /2 ;32 C var low = fitCV0 ( x (3 ) , x (4 ) ) /2 ;33 C var 50percent=f i tCV50percent ( x (3 ) , x (4 ) ) /2 ;34 Rp var=fitRP02 ( x (3 ) , x (4 ) ) ∗2 % mult ip ly by 2 to account f o r

s i n g l e ended3536 % CROSS COUPLED PAIR3738 %Generate worst case Rp −− Al l ON, 2 binary b i t s , 7

thermometer caps39 Rp allON=1/(1/ Rp unit+1/Rp 2unit+1/Rp 4unit+1/Rp 4unit+1/

Rp 4unit+1/Rp 4unit+1/Rp 4unit+1/Rp 4unit+1/Rp 4unit +1/Rp var+1/L rp )

40 gm needed=2/Rp allON4142 % could use i f statement to make sure gm i s with in bounds43 i f ( gm needed < 0 .0159) && ( gm needed > 0 .004924)4445 Wxcpl=fitGMxWid y ( gm needed )46 Cxcpl=fitCxcplusingGm ( gm needed )47 else48 Wxcpl=0; %not sure what to put here49 Cxcpl=900e−15; % l a r g e cap50 end51

28

5253 %Stray Cf ix capac i tance54 Cf ix=Cxcpl+10e−15; %gm pa i r and guess f o r b u f f e r5556 C mid=2∗C unit h igh4+C unit low4∗5+C uni t h igh+C unit h igh2+

C var 50percent+Cfix ; % middle f requency w i l l be at h a l fcap , mid curve

57 C mid minus1=1∗C unit h igh4+6∗C unit low4+C unit h igh2+C uni t h igh+C var 50percent+Cfix ; % f o r t e s t i n g over lap ,at middle o f curve above middle

58 C mid max= 2∗C unit h igh4+C unit low4∗5+C unit low+C unit low2+C var low+Cfix ; % Max frequency at mid coursetuning curve

5960 C min = 7∗C unit low4+C unit low2+C unit low+C var low+Cfix ;

% Max curve , and max on the curve ( varac to r low )61 C min minus1 mid = 7∗C unit low4+C unit low2+C uni t h igh+

C var 50percent+Cfix ; % Middle o f the curve on max −1curve

62 C min minus1 low= 7∗C unit low4+C unit low2+C uni t h igh+C var low+Cfix ;

63 C min high = 7∗C unit low4+C unit low2+C unit low+C var high+Cfix ; % Max curve , l owest f requency (max cap on that curve)

64 C min mid = 7∗C unit low4+C unit low2+C unit low+C var 50percent+Cfix ; % Max curve , middle f requency

656667 % Pr in t ing the C un i t s f o r c a l c u l a t i o n68 disp (” C unit low4 ” + C unit low4 )69 disp (” C unit low2 ” + C unit low2 )70 disp (” C unit low ” + C unit low )71 disp (” C var low ” + C var low )72 disp (” C min ” + C min )73 % both binary are o f f , add f i x e d cap74 % 01111 in binary i s 2ˆ4 or 15 , h a l f o f 2ˆ5 or 3175 % T7 T6 T5 T4 T3 T2 T1 T0 | B1 B076 % 0 0 0 0 0 1 1 | 1 17778 %C mid minus1 i s 14 or 0011 | 1079 %80 %0 0 0 0 1 1 1 | 1 081 % Low cap i s 0 0 0 0 0 0 0 | 0 0

29

82 % C min=C unit low+C unit low2+7∗C unit low4+Cfix+C var low ;8384 C max=C uni t h igh+C unit h igh2+7∗C unit h igh4+C var high+Cfix

% a l l caps ON85 C max mid=C uni t h igh+C unit h igh2+7∗C unit h igh4+

C var 50percent+Cfix ;868788 f min =1/(2∗pi∗sqrt (L∗C max) ) % abso lu te min f , a l l caps OFF,

varac to r high89 f min mid =1/(2∗pi∗sqrt (L∗C max mid ) ) %Middle o f the lowest

curve9091 f mid =1/(2∗pi∗sqrt (L∗C mid ) ) % middle o f middle curve92 f max high =1/(2∗pi∗sqrt (L∗C min ) ) % abso lu t e max f = a l l caps

o f f ( and varac to r low )93 f max low =1/(2∗pi∗sqrt (L∗C min high ) ) % Highest curve , l owest

f r e q94 f max minus1 = 1/(2∗pi∗sqrt (L∗C min minus1 low ) )% h ighe s t

po int on second h ighe s t curve95 f max mid = 1/(2∗pi∗sqrt (L∗C min mid ) ) % Highest curve ,

middle f requency96 over lap= ( f max minus1−f max low ) /( ( f max high−f max low ) )979899 TR=f max mid−f min mid

100101102103104 % Find the over lap between curves105 % us ing the mid curve106107108 % Weights f o r ” normal ized ” f i t n e s s func t i on109 alpha=1e3 ;110 beta=1e−5;111 gamma=1E−5;112113 retVal = alpha∗abs(3−C u n i t r a t i o ) + beta∗1/Rp2 + 1E4∗1/

Rp var + gamma∗abs (28 e9−f mid ) + 1e6∗abs(0.4− over lap ) + 1E−6∗1/TR

114 %alpha∗abs(3−C u n i t r a t i o )+beta ∗1/Rp1

30

115116117 end

code/import digitalCapSweep min5mA2.m

1 % imports d i g i t a l switched cap sweep v a r i b l e s and p r o c e s s e sthe data

2 % Matthew Belz 2/20/20193456 % Import Sweeps7 m = importMOM2( ’ m swCap 60u . csv ’ , 2 , 102) ;8 caphigh = importMOM2( ’ CapHigh 60u . csv ’ , 2 , 102) ;9 caplow = importMOM2( ’ CapLow 60u . csv ’ , 2 , 102) ;

10 RpON = importMOM2( ’ Rp ON swCap 60u . csv ’ , 2 , 102) ;11 Rp2 OFF = importMOM2( ’ Rp OFF swCap 60u . csv ’ , 2 , 102) ;121314 capL=caphigh ( : , 1 ) ;15 NF= [ 1 : 2 0 ] ;161718 % For m (Con/ Cof f ) r a t i o19 count2 =1;20 for k = 2 : 2 : 4 0 %Import as j u s t cap va lue s without capL

columns21 mEQ( : , count2 )=m( : , k ) ;22 count2=count2 +1;2324 end2526 % For high value o f cap27 count2 =1;28 for k = 2 : 2 : 4 0 %Import as j u s t cap va lue s without capL

columns29 CapEQ high ( : , count2 )=caphigh ( : , k ) ;30 count2=count2 +1;3132 end3334 % For low value o f cap35 count2 =1;

31

36 for k = 2 : 2 : 4 0 %Import as j u s t cap va lue s without capLcolumns

37 CapEQ low ( : , count2 )=caplow ( : , k ) ;38 count2=count2 +1;3940 end4142 % For Rp1 (ON)43 count2 =1;44 for k = 2 : 2 : 4 0 %Import as j u s t cap va lue s without capL

columns45 RP ON EQ( : , count2 )=RpON( : , k ) ;46 count2=count2 +1;4748 end4950 %For RP2 (OFF)51 count2 =1;52 for k = 2 : 2 : 4 0 %Import as j u s t cap va lue s without capL

columns53 RP OFF EQ ( : , count2 )=Rp2 OFF ( : , k ) ;54 count2=count2 +1;5556 end5758596061 %Generate cap Width sweep62 count =1;63 for i =1.22e−6:0.68 e−6:6.66 e−664 w( count )=i ;65 count=count +1;66 end6768 % Import the curves f o r the gm69 GmVsWxcpl = importGmPlot ( ’ gm wxcpl 5mA . csv ’ , 2 , 38) ;70 CxcplVsGm = importGmPlot ( ’ gm cin 5mA . csv ’ , 2 , 38 ) ;7172 %Generate ve c t o r s used in Curve f i t73 Wxcpl=GmVsWxcpl ( : , 1 ) ;74 Gm=GmVsWxcpl ( : , 2 ) ;75

32

76 GmC=CxcplVsGm ( : , 1 ) ;77 Cxcpl=CxcplVsGm ( : , 2 ) ;78798081 % GmVsWxcpl = importGmPlot ( ’GmVsWxcpl2 . csv ’ , 2 , 38) ;82 % CxcplVsGm = importGmPlot ( ’ CxcplVsGm2 . csv ’ , 2 , 3 8 ) ;8384 %Generate ve c t o r s used in Curve f i t85 Wxcpl2=GmVsWxcpl ( : , 1 ) ;86 Gm2=GmVsWxcpl ( : , 2 ) ;8788 GmC2=CxcplVsGm ( : , 1 ) ;89 Cxcpl2=CxcplVsGm ( : , 2 ) ;

code/S Parameter Cleanup.m

1 % S−Parameter Clean−up23 sp28GHzW256nto25uNF1to25Lmin ( 1 , : ) = [ ] ;4 sp28GHzW256nto25uNF1to25Lmin ( : , 4 : 3 : end) = [ ] ;5 sp28 new = zeros (31 , ce i l ( length ( sp28GHzW256nto25uNF1to25Lmin )

/2) ) ;6 sp28 new ( : , 1 ) = sp28GHzW256nto25uNF1to25Lmin ( : , 1 ) ;7 sp28 new ( : , 2 : end) = sp28GHzW256nto25uNF1to25Lmin ( : , 2 : 2 : end) +

. . .8 1 i ∗sp28GHzW256nto25uNF1to25Lmin ( : , 3 : 2 : end) ;9 vo l tage = sp28 new ( : , 1 ) ;

10 s11 = sp28 new ( : , 2 : end) ;11 sp28 new y par t i a l = s11 ( : , 1 : 2 4 9 ) ;12 width =[256e−9 ,300e−9:100e−9:25e−6] ;13 y11 = (1/50)∗(1− s11 ) ./(1+ s11 ) ;14 f c = 28 e9 ;15 cap = imag( y11 ) . / ( 2∗ pi∗ f c ) ;16 c a p p a r t i a l = cap ( : , 1 : 2 5 ) ;17 NF = 1 : 1 : 2 5 ;18 c a p s u p e r p a r t i a l = c a p p a r t i a l ( 1 : 3 1 ) ;19 matr ix cap super = [ vo l tage ’ ; c a p s u p e r p a r t i a l ] ;20 c a p s u p e r p a r t i a l 2 = 1e16∗ c a p s u p e r p a r t i a l ;21 matr ix cap super2 = [ vo l tage ’ ; c a p s u p e r p a r t i a l 2 ] ;22 NF2=1 :1 : 25 ;232425 cap re form = reshape ( cap , 31 , 25 , 249 ) ;

33

26 V0=cap re form ( 7 , : , : ) ; % Not at zero V, at −0.2V f o r mostl i n e a r

27 V0sq=squeeze (V0) ;28 Vw=cap re form ( 7 , 1 , : ) ;2930 V05=cap re form ( 1 3 , : , : ) ; %s e l e c t s V=0.1V31 V05sq=squeeze (V05) ;3233 V50percent=cap re form ( 1 0 , : , : ) ; %s e l e c t s V=−0.05v f o r 50%

over lap measurement34 V50percentSq=squeeze ( V50percent ) ;3536 Rp=1./( real ( y11 ) ) ;37 Rp reform=reshape (Rp,31 , 25 , 249 ) ;38 Rp02=Rp reform ( 1 5 , : , : ) ; %Get Rp at 0 .2V39 Rp02sq=squeeze (Rp02) ;4041 surf ( width ’ , vo l tage ’ , squeeze ( cap re form ( : , 1 , : ) ) , ’ FaceColor ’ ,

’ r ’ )4243 %CO( : , : , 1 ) = ze ro s (31 ,99) ; % red44 %CO( : , : , 2 ) = ones (31 ,99) .∗ repmat ( l i n s p a c e ( 0 . 5 , 0 . 6 , 9 9 ) , 31 ,1 ) ;

% green45 %CO( : , : , 3 ) = ones (31 ,99) .∗ repmat ( l i n s p a c e (0 , 1 , 99 ) , 31 ,1 ) ; %

blue4647 CO( : , 1 ) = zeros (1 , 25 ) ; % red48 CO( : , 2 ) = ones (1 , 25 ) .∗ linspace ( 0 . 5 , 0 . 6 , 2 5 ) ; % green49 CO( : , 3 ) = ones (1 , 25 ) .∗ linspace ( 0 , 1 , 25 ) ; % blue5051 CO = colorSpectrum (25) ;5253 for NF=1:2554 surf ( width ( 1 : 9 9 ) ∗1e6 ’ , vo l tage ’ , squeeze ( cap re form ( : ,NF

, 1 : 9 9 ) ) ∗1e15 , ’ FaceColor ’ , CO(NF, : ) , . . .55 ’ EdgeColor ’ , ’ k ’ , ’ L ineSty l e ’ , ’ : ’ )56 hold on57 end58 xlabel ( ’ Width (\mu m) ’ ) ;59 ylabel ( ’ Voltage (V) ’ ) ;60 zlabel ( ’ Capacitance ( fF ) ’ ) ;6162

34

63 %Generate s u r f a c e f o r V=0V64 [ fitCV0 , go f ] = createFitV0 ( width , NF2, V0sq ) ;65 %Generate func t i on f o r vo l tage at V=−0.266 [ fitCV05 , go f ] = createFitCV05 ( width , NF2, V05sq ) ;67 %Generate func t i on f o r vo l tage at V=0.1;68 [ f i tCV50percent , go f ] = createFitCV05 ( width , NF2,

V50percentSq ) ;69 %Generate func t i on f o r vo l tage at V=−0.05;70 [ fitRP02 , go f ] = createFitRP02 ( width , NF2, Rp02sq )71 %Generate func t i on f o r vo l tage at V=0.5p ;

35

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