A use of sigma-delta modulation in power digital-to-analogue conversion

INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS, VOL. 25, 439–455 (1997)

A USE OF SIGMA-DELTA MODULATION IN POWERDIGITAL-TO-ANALOGUE CONVERSION

ANTHONY J. MAGRATH ∗ AND MARK B. SANDLER

Department of Electronic and Electrical Engineering, King’s College London, Strand, London WC2R 2LS, U.K.

SUMMARY

Power digital-to-analogue (D–A) converters have applications in digital audio, portable equipment and industrial controlsystems. This paper discusses the use of sigma–delta modulation as the primary processing block in power D–A systems.The focus is on the pulse repetition frequency (PRF) of the one-bit output and its suitability for power switching. It isshown that in order to preserve high power e�ciency and tolerance to a non-ideal output stage, the PRF of the outputmay be reduced and made constant by the use of a technique termed bit ipping. The performance of di�erent bit ippingalgorithms is discussed which aim to regulate the PRF whilst maintaining the stability of the modulation process. Resultsare presented which compare the performance of the di�erent systems under the conditions of an ideal and a non-idealoutput stage. ? 1997 by John Wiley & Sons, Ltd.

Int. J. Circ. Theor. Appl., 25, 439–455 (1997).No. of Figures: 15 No. of Tables: 5 No. of References: 18

KEY WORDS sigma-delta modulation; power digital-to-analogue conversion; digital power ampli�cation

1. INTRODUCTION

The basic concept of power digital-to-analogue (D–A) conversion is to convert a digital signal to analogue atpower level without the use of intermediate analogue ampli�cation. The conversion principle is illustrated inFigure 1. The PCM input signal is converted to a high-rate one-bit (two-level) signal using oversampled noise-shaping techniques. The signal is used to control a high-voltage power switch, typically a MOSFET bridgecircuit, and the resulting rectangular wave-form is demodulated using a passive L–C lowpass �lter. The powerswitch and �lter combination is often referred to as a class-D ampli�er. The principal advantages in comparisonwith conventional low-level D–A conversion followed by analogue ampli�cation are the elimination of theanalogue ampli�er and its associated distortions and the possibility of achieving very high power e�ciency,with practical designs reaching over 90%.1

The primary application is for domestic and professional high-�delity audio reproduction, though applicationsalso arise in industrial control applications, such as motor control. The technique is also attractive for low/medium-power portable equipment where power consumption must be kept to an absolute minimum, e.g.personal communication systems and digital hearing aids.The focus of this paper is the generation of a one-bit signal suitable for high-quality e�cient class-D

ampli�cation. For e�cient power conversion it is important that the rate of transitions in the one-bit signalis minimized, since a switch with �nite rise and fall times will dissipate energy on every transition. Thetransition rate is usually described in terms of the average pulse repetition frequency (PRF), which is de�nedas the reciprocal of the average time between consecutive rising edges of the one-bit signal. Using MOSFETswitching devices, a PRF around 350 kHz is acceptable for power conversion with an e�ciency of over 90%.1

In the Appendix it is shown that it is also important for the PRF to be signal-independent in order to preventadditional distortion and noise occurring when a non-ideal output stage is used.

∗ Correspondence to: A.J. Magrath, Department of Electronic and Electrical Engineering, King’s College London, Strand, London WC2R2LS, U.K. E-mail: [email protected].

CCC 0098–9886/97/050439–17$17.50 Received 7 October 1996? 1997 by John Wiley & Sons, Ltd. Revised 14 March 1997

440 A. J. MAGRATH AND M. B. SANDLER

Figure 1. Block diagram of power D–A converter

1.1. Power conversion using pulse width modulation

Previous one-bit converters suitable for power D–A conversion have utilized the combination of noiseshaping and pulse width modulation (PWM) to produce a one-bit signal with a low and constant PRF. Thenoise shaping reduces the wordlength at the PWM input and reduces the time domain pulse quantization byreducing the set of di�erent pulse widths required to represent the set of input amplitudes. Typical PWMsystems use eight-times oversampling and noise shaping to reduce the wordlength at the input of the PWMblock to 8 bits, corresponding to a PRF of 352·8 kHz. A clock frequency of approximately 90 MHz is requiredand this is beyond the frequency of standard ASIC implementation; therefore current implementations use adiscrete logic circuit to generate the PWM output.2

A further problem with PWM is that it is inherently a non-linear process generating harmonic and foldbackdistortion, where, in the latter case, sidebands of the carrier frequency (i.e. PRF) fall into the baseband. Thesedistortions are detailed in Reference 3. The use of oversampling reduces foldback distortion to acceptablelevels, but harmonic distortion must be dealt with using a linearization algorithm1; 3–6 which increases thehardware complexity of the system.These problems suggest that linearized noise-shaped PWM is not ideal and in the remainder of the paper

we consider the use of an alternative technique based upon sigma–delta (��) modulation. The two motivatingfactors for using �� modulation for power D–A conversion are its potential for high linearity and its lowclock rate: �� modulators suitable for audio typically have an oversampling ratio L=64, corresponding toa clock rate of only about 3MHz, leading to the possibility of ASIC implementation. It will be shown inSection 2.2, however, that the average PRF is too high for e�cient conversion. A system which combines theabove advantages with the low PRF of PWM has been described in Reference 7. This technique reorders thepositive and negative bits in a �xed length block of the bistream so that they are grouped by sign. This hasthe e�ect of reducing the PRF. The complexity of this scheme is prohibitive because two feedback loops arerequired—one around the quantizer and the other around the pulse grouper, each with their own loop �lter.In this paper we discuss a di�erent system which has the same advantages as Reference 7, but has relativelylow complexity because it requires only a single feedback loop.

2. SIGMA–DELTA POWER D–A CONVERTERS

In this section we �rst consider some aspects of the theory and design of �� modulators and evalu-ate the time domain properties of the one-bit output, which govern the suitability of the modulation pro-cess for power D–A conversion. �� modulators use a one-bit quantizer embedded in a feedback loop tocode an oversampled multibit PCM input into a one-bit signal with high resolution over a narrow band-width.The block diagram of a discrete-time �� modulator is shown in Figure 2. For a quantization error sequence

E(z) and input signal X (z) the output of the modulator is given by

Y (z)=X (z)STF(z) + E(z)NTF(z) (1)

Int. J. Circ. Theor. Appl., Vol. 25, 439–455 (1997) ? 1997 by John Wiley and Sons, Ltd.

POWER DIGITAL-TO-ANALOGUE CONVERSION 441

Figure 2. Discrete-time block diagram of �� modulator

where

STF(z) =H (z)

1 + H (z)(2)

NTF(z) =1

1 + H (z)(3)

The signal transfer function STF(z) and noise transfer function NTF(z) de�ne the spectra of the signaland noise components of the output signal respectively. For power D–A converters the NTF is de�ned asa highpass �lter to obtain high resolution in the baseband at the expense of increased quantization noise athigher frequencies.

2.1. Noise transfer function design

For the work presented in this paper, the NTFs are designed using Butterworth poles and the zero frequenciesare chosen according to Reference 8 to minimize the baseband quantization noise. The NTF is scaled so thatthe �rst term in the impulse response is unity, which ensures that the modulator is implementable.9 Usingthis design methodology, for a given oversampling ratio L, sampling frequency fs and modulator order N , thestability and noise performance of the modulator is completely de�ned by the power gain of the NTF, whichis given by

Pn =1�

∫ �

0|NTF(�)|2d� (4)

Pn de�nes the ampli�cation of the quantization noise which is present at the output of the modulator.Owing to the constancy of output power of a one-bit signal,10 Pn is important in governing the availablesignal headroom and therefore the maximum input signal prior to instability. The maximum input signal istermed the maximum stable amplitude (MSA). Increased MSA can be obtained by reducing the Butterworthcut-o� frequency, which reduces Pn at the expense of reduced attenuation in the baseband.11

2.2. Pulse repetition frequency of a �� bitstream

In this section we consider the suitability of �� modulation for power D–A conversion in terms of thePRF of the output y(k). The time domain properties of y(k) depend on the composition of periodic patterns,termed limit cycles, associated with periodic orbits in the modulator state space.12 The limit cycle compositionis very complex for high-order modulators, but it is possible to make a generalization about the average PRF.The average PRF for sampling frequency fs and oversampling ratio L is de�ned by

�fp = limM →∞

Lfs4M

M∑k=1

|y(k)− y(k − 1)| (5)

In this expression, every transition contributes a value of two to the summation.The output of the modulator can be considered to consist of a sequence of ‘time slots’ which are �lled by

either +1 or −1. For zero input the output oscillates to maintain a mean output of zero. A maximum PRF of

? 1997 by John Wiley and Sons, Ltd. Int. J. Circ. Theor. Appl., Vol. 25, 439–455 (1997)


Lfs=2 occurs for a periodic sequence {+1, −1, +1 : : :}. As the input level increases, the percentage of slotscontaining +1 increases, resulting in a reduction in PRF. If the modulator maintains stability and accuratelycodes the input signal, for a maximum input x(k)= 1, theoretically y(k)= 1 for all k and the PRF falls tozero. It is shown in Reference 11 that the maximum PRF for DC input x(k)=mx decreases linearly with mx:

f̂pd(mx)=Lfs2(1− |mx|) (6)

For sinusoidal inputs it can be shown11 that for a sine wave input of peak amplitude As the maximum PRFis approximated by

f̂ps(As) ≈Lfs2

(1− 2As

�

)(7)

In these expressions, for the average PRF to follow the maxima, it is necessary that the output bits arearranged so that the 1s and −1s are evenly distributed. This is a fairly good approximation;13 however, it isshown in Section 5.3 that in practice grouped patterns occur at low inputs which cause the PRF to be lowerthan indicated by the above expressions. The results show that for an oversampling ratio L=32 a maximumPRF of the order of 500 kHz is produced. For audio conversion a dynamic range of 98 dB is desirable andto obtain this a seventh-order modulator is required. To achieve lower PRFs, the oversampling ratio needs tobe reduced and as a consequence a higher-order modulator is required, resulting in prohibitive complexity.For power D–A converters, very-high-order �lters are undesirable, because the order and complexity of thepassive reconstruction �lter must be greater to properly attenuate out-of-band quantization noise. Furthermore,the PRF is dependent on the signal amplitude. It is shown in the Appendix that if the PRF is signal-dependent,the linearity and noise performance of the �nal conversion to analogue is destroyed in the case where theoutput switch has unequal rise and fall times.

3. BIT-FLIPPING ALGORITHMS FOR �� POWER D–A CONVERSION

The remainder of this paper focuses on a technique which may be used to reduce the PRF and remove itssignal dependence. The technique is termed bit ipping.The basis of bit ipping is to invert the state of selected samples in order to reduce the PRF. Figure 3

shows the topology of the modulator. The quantizer output is selectively inverted using a bit ipping operator(BFO), which is represented in the diagram by a selective multiplication by +1 or −1. The BFO is positionedwithin the feedback loop, so that errors introduced by the bit ipping are shaped by the NTF.An example of the concept of PRF reduction using bit ipping is shown in Figure 4. The lower se-

quence has a lower PRF than the upper sequence owing to the elimination of the high-transition-rate {1, −1}pattern.

Figure 3. General block diagram of �� modulator with bit ipping algorithm. The BFO is represented by a multiplier



Figure 4. Transition reduction using bit ipping. The upper sequence is bit ipped to produce the lower sequence

3.1. PRF control

We now discuss an algorithm to control the bit ipping, with the aim of making the PRF constant andsignal-independent. The algorithm operates by detecting transitions in the bitstream and reducing the transitionsby activating the BFO if an estimate of the average PRF exceeds a speci�ed constant.A transition occurs if y(k) 6=y(k − 1). The number of transitions up to the current sample k is given by

T (k)= 12

k∑i=1

|y(i)− y(i − 1)| (8)

leading to an estimate of the PRF at sample k:

fe(k)=LfsT (k)=2k (9)

De�ning ft as the target maximum PRF of the bitstream, the BFO is activated for samples in which thefollowing two conditions are met:

y(k) 6= y(k − 1) (10)

fe(k)¿ft (11)

The latter condition is termed the PRF condition. The algorithm can be simpli�ed by combining condition(11) with equation (9):

T (k)=k¿2ft=Lfs (12)

The PRF constant is now de�ned as

Fk = Lfs=2ft (13)

The use of the PRF constant simpli�es the PRF control algorithm. Condition (12) can be now be re-expressed as

T (k)=k¿1=Fk (14)

FkT (k)¿k (15)

FkT (k)− k¿0 (16)

This can be implemented as a counter which adds Fk for every transition and counts down one on everysample. The PRF condition is TRUE if the counter output is positive. For Fk =1; k¿T (k) for all k, thereforethe bit ipping algorithm becomes inactive and the operation of the modulator is that of an unmodi�edmodulator.

4. IMPROVING NOISE PERFORMANCE AND STABILITY MARGINS

In Section 5.2, simulations show that although the bit ipping algorithm is successful at regulating the PRF,this is at the expense of an increase in noise power and a reduction in the MSA. The reason for this is that bit



Figure 5. Bit ipping with alternation constraint

ipping increases the magnitude of the quantizer error within the feedback loop.14 In this section we considertwo methods which modify the particular bits which are ipped in order to enhance the stability and noiseperformance.

4.1. Alternation constraint

The aim of the alternation constraint is to shape the error introduced by the BFO with a highpass charac-teristic to reduce the noise introduced into the baseband.We begin by de�ning the error sequence of the BFO:

eb(k)=y(k)− b(k) (17)

where b(k) is the output of the quantizer.eb(k) has a value of +2 for every positive (1→−1) bit ip and −2 for every negative (−1→ 1) bit

ip. An approximation of the low-frequency content of eb(k) can be found by passing the error through adiscrete-time integrator, which emphasizes low frequencies:

ew(k)=k∑i=1

eb(i) (18)

A method of ensuring that the peak–peak value of ew(k) is minimized is to minimize the number of equi-sign ips. The tightest constraint is that every negative ip is followed by a positive ip and vice versa. Thisensures that the maximum peak–peak value of ew(k) is minimized to two. Examples of this are given inFigure 5.Limiting the peak–peak value of ew(k) has the e�ect of limiting the variance of the weighted error, be-

cause the maximum sample-by-sample variance contribution is reduced. The e�ect is to control the basebandnoise power introduced by the bit ipping. The algorithm is implemented using counters which measure themaximum number of negative and positive bit ips.11

The bit ipping algorithm with PRF and alternation control combined is as follows. Activate the BFO ifall the following conditions are satis�ed:

y(k)6=y(k − 1) (19)

fe(k)¿ft (20)

Cm61 (21)

where Cm is the number of consecutive positive or negative bit ips.The performance of the bit ipping algorithm with alternation constraint is evaluated in Section 5.

4.2. Look-ahead

The look-ahead algorithm improves the stability of the �� modulator with bit ipping by detecting andeliminating delays which can occur though the bit ipping unit for some bit patterns. For example, consideringthe bit pattern of Figure 6(a) and assuming for the moment that the PRF constraint is relaxed, bit ipping



Figure 6. Delay introduced by bit ipping

Figure 7. Block diagram of conceptual look-ahead system

occurs whenever there is a transition between the present and previous bits and the alternation constraint issatis�ed. For these bit patterns a delay occurs through the BFO, yet there is no reduction in transitions.A method of avoiding the delay is to precisely calculate possible future bit patterns to prevent bit ipping

when there will be no reduction in transitions.The principle of look-ahead has been used in Reference 6 to prevent delays in a PWM feedback correction

algorithm. Applied to the �� modulator, the basic idea is to delay the input to the modulator and usethe resulting ‘advance’ input to feed an identical modulator (��2 in Figure 7). The look-ahead output of��2 (yla(k)) is therefore a prediction of the next output of ��1 (y(k + 1)). The idea of look-ahead is touse the advance output to in uence the decision made by the BFO.

4.2.1. Violation of Causality. There are two fundamental problems with this system. Firstly, it is clear fromFigure 7 that any bit ipping of ��1 will cause the predictions made by ��2 to be incorrect in subsequentsamples. Secondly, a violation of causality is provoked by attempting to use a prediction of y(k+1) to controlthe system which produces y(k).The non-causal loop can be broken by calculating yla(k) for the case where no bit ipping occurs in sample

k and using this value to in uence the control algorithm. If the decision of the algorithm is to activate theBFO, yla(k) is recalculated so that the predictions made by ��2 will be correct in subsequent samples. Fulldetails of an e�cient implementation of this algorithm are presented in Reference 11.

4.2.2. One level of Look-Ahead. The simplest look-ahead algorithm uses one level of look-ahead (1LA). Inthis algorithm the current output y(k) is used in conjunction with the previous output y(k−1) and look-aheadoutput yla(k) to identify the following high-transition-rate patterns.

1. {y(k − 1); y(k); yla(k)}= {1;−1; 1}.2. {y(k − 1); y(k); yla(k)}= {−1; 1;−1}.



Table I. Possible patterns before and after bit ipping for 1 LA

Before BF After BF

y(k − 1), y(k), yla(k) T y(k − 1), y(k), y(k + 1) T

−1, 1, −1 2 −1, −1, −1 0−1, −1, 1 1

Table II. Possible patterns at the input and output of bit ipping unit for 2 LA. Only detectedinput patterns are shown

Input Output

y(k − 1); y(k); yla(k); y2la(k) T y(k − 1); y(k); y(k + 1); y(k + 2) T

−1, 1, −1, 1 3 −1, −1, −1, −1 0−1, −1, −1, 1 1−1, −1, 1, −1 2−1, −1, 1, 1 1

−1, 1, −1, −1 2 −1, −1, −1, −1 0−1, −1, −1, 1 1−1, −1, 1, −1 2−1, −1, 1, 1 1

−1, 1, 1, −1 2 −1, −1, −1, −1 0−1, −1, −1, 1 1−1, −1, 1, −1 2−1, −1, 1, 1 1

If either of these patterns occurs, the BFO is activated to invert y(k). Since y(k+1) is dependent on y(k),there are two possible bit patterns for each of the above patterns which result from the inversion of y(k).These are shown in Table I for pattern 2 above. The table shows that bit ipping of sample y(k) will alwaysresult in a reduction in transitions, regardless of the outcome of y(k + 1).

4.2.3. Two Levels of Look-ahead. By bit ipping only upon the detection of {−1, 1, −1} or {1, −1, 1}triplets, there is a limit to the reduction in PRF possible. In the two-level look-ahead (2LA) algorithm anadditional output y2la(k) is generated by the modulator, representing a prediction of y(k + 2) for the casewhere no bit ipping occurs in sample y(k) or y(k + 1). This makes it possible to predict and eliminate theoccurrence of the following patterns.

1. {y(k − 1); y(k); yla(k)}= {1;−1; 1}:2. {y(k − 1); y(k); yla(k)}= {−1; 1;−1}:3. {y(k − 1); y(k); yla(k); y2la(k)}= {1;−1;−1; 1}:4. {y(k − 1); y(k); yla(k); y2la(k)}= {−1; 1; 1;−1}:

This allows the PRF to be reduced further than with the 1LA algorithm.In the case of bit patterns 3 and 4, two adjacent bit ips are required, i.e. both y(k) and y(k + 1) need

to be inverted. This is accommodated naturally by the algorithm, since inverting y(k) in pattern 3 or 4 willproduce pattern 1 or 2 on the next sample. See Table II.The performance of the look-ahead algorithms is evaluated in Section 5.



5. INVESTIGATION AND RESULTS

In this section we present simulations of standard �� and bit ipping algorithms. The aims are twofold:�rstly, to assess the relative gains of the bit ipping algorithms over standard modulation with an ideal and anon-ideal output stage; secondly, to evaluate the system parameters required to achieve performance suitablefor audio conversion. To this end we aim to achieve in excess of 98 dB dynamic range and a PRF of theorder of 350 kHz. The modulator NTF is designed according to the methodology of Section 2.1. For allsimulations the sampling rate is fs = 44·1 kHz. We begin by evaluating the PRF characteristics of the basicalgorithms, followed by detailed noise evaluation. The following results are for an assumed ideal output stage.Results for a non-ideal output stage are presented in Section 5.5.

5.1. PRF Characteristics

We begin by evaluating the PRF characteristics of standard and bit ipping modulators for the followingexample parameters: oversampling ratio L=64, order N =4 and power gain Pn = 2·0 dB. The average PRFis evaluated using the following equation with M =100; 000 simulation samples:

fpe =Lfs4M

M∑k=1

|y(k)− y(k − 1)| (22)

In Figures 8 and 9 the average PRF is plotted against the input level for DC and sinusoidal inputs re-spectively with Fk =1; 2. The curve for Fk =1 represents a standard modulator with the bit ipping inactive.Plotted on the same axis are the theoretical PRF maxima evaluated from equations (6) and (7).It can be seen that for the standard modulator the maxima are followed fairly closely, especially in the DC

case, with convergence occurring at high amplitudes. At low amplitudes the measured PRF falls considerably.Time domain simulations have shown that this is due to an increased occurrence of groups of adjacent 1sand −1s samples. For example, at zero input the repeating pattern {1, 1, −1, −1, 1, 1, −1, −1,: : :} occursrather than the higher-transition pattern {1, −1, 1, −1, 1, −1, : : :}.With the bit ipping modulator for Fk =2 the PRF remains at a constant 705·6 kHz (as predicted by

equation (13)) for both DC and sine wave inputs, until the PRF of the unmodi�ed modulator falls below the

Figure 8. Average PRF against input level for L=64; N =4; Pn = 2·0 dB for DC input with PRF control and Fk =1; 2. Also shown is themaximum theoretical PRF f̂pd.



Figure 9. Average PRF against input level for L=64; N =4; Pn = 2·0 dB for 1 kHz sine wave input with PRF control and Fk =1; 2.Also shown is the maximum theoretical PRF f̂ps

Figure 10. Wideband spectrum of bit ipping system output with PRF constraint and Fk =2

PRF of the bit ipping algorithm. In practical designs, which achieve maximum dynamic range for a givenorder, the MSA is in the region of 0·2–0·35; therefore the modulator would normally become unstable beforethe PRF falls and so the PRF remains constant over the operating range of the modulator.The bit ipping reduces the stability of the modulator and for Fk¿2 the system is unstable at all input

levels. In Figure 10 the wideband spectrum is shown for the above parameters with Fk =2 and a 1 kHz sinewave input of amplitude As = 0·3. The high-amplitude spectral tone at 705·6 kHz demonstrates the periodicityin y(k) at the PRF.In Figure 11 results are shown for the bit ipping algorithm with the alternation constraint active. The

alternation constraint increases the stability of the bit ipping, allowing lower PRFs to be obtained. At very



Figure 11. Average PRF against input level (1 kHz sine wave) for bit ipping modulator “with parameters: L = 64; N = 4; pn = 2·0 dB”,with PRF control and alternation constraint

Figure 12. Average PRF against input level (1 kHz sine wave) for bit ipping modulator “with parameters: L = 64; N = 4; pn = 2·0 dB”,with PRF control and one level of look-ahead

low PRFs the PRF becomes amplitude-dependent. This is because the alternation constraint restricts the numberof allowable equi-signed bit ips and in doing so imposes a lower bound on the PRF.We now consider the e�ectiveness of the look-ahead algorithm in conjunction with the PRF control.

In Figure 12 results are shown for one level of look-ahead. It can be seen that the look-ahead has a similare�ect to the alternation constraint—a lower bound is introduced onto the PRF and the stability of the modula-tor is improved. The lower bound is at a slightly higher PRF than with the alternation constraint (Figure 11);however, this restriction is relaxed for 2 LA, as shown in Figure 13. Compared with the alternation constraint,the stability of the modulator is improved using look-ahead.



Figure 13. Average PRF against input level (1 kHz sine wave) for bit ipping modulator “with parameters: L = 64; N = 4; pn = 2·0 dBwith PRF control and two levels of look-ahead

5.2. Noise Performance

In this section we evaluate the noise performance of the basic algorithms and also assess the performanceof combinations of the algorithms. The following algorithms are compared.

1. System A: ‘standard’ �� system.2. System B: bit ipping algorithm with PRF control only.3. System C: bit ipping algorithm with PRF control and alternation constraint.4. System D: bit ipping algorithm with look-ahead and PRF control.5. System E: bit ipping algorithm with look-ahead, alternation constraint and PRF control.

Where the algorithms are combined, all the conditions of the individual algorithms must be satis�ed forthe BFO to be triggered.

5.2.1. Obtaining parameters for target performance. The previous examples have shown that the stabilityand hence MSA of the modulators using bit ipping depend upon the algorithm and parameters. As discussedin Section 2.1, a trade-o� exists between the baseband noise power and stability of the modulator. To fullycompare the performance of the di�erent algorithms, the modulators are �rst optimized so that with thealgorithm under test they have the same MSA of 0·3. This is within the range normally associated withmodulators with maximal dynamic range.15 For each algorithm and associated parameters the NTF parametersto achieve this MSA have been obtained by �nding the maximum value of Pn before instability occurs witha 1 kHz sinusoidal input of amplitude 0·3. The maximum value of Pn provides a measure of the inherentstability of the algorithm, with higher Pn implying better stability since the modulator can accept a greaternoise ampli�cation.A simulation is then performed at the maximum power gain and input level to determine the baseband

noise power Pb. PRF measurements using equation (22) are then made over the input range. These tests havebeen performed for orders N =4–8, oversampling ratios L=32 and 64 and di�erent bit ipping parameters.

5.3. System A: standard sigma–delta system

We begin with the standard �� modulator. The results are summarized in Table III. The PRF is themaximum evaluated over the input range of the modulator. The results show that the target PRF of 352·8 kHz



Table III. Summary of performance of standard modulator (System A) with L=32 and 64

L=32 L=64

N Max. PRF (kHz) Pn Pb (dB) Max. PRF (kHz) Pn Pb (dB)

4 497·5 4·20 −92·2 993·9 4·25 −119·15 496·3 4·15 −100·2 1004·1 4·05 −132·06 504·6 4·10 −106·8 1003·5 4·00 −144·17 505·2 4·00 −111·1 1007·9 4·00 −154·58 502·8 4·05 −116·4 1013·4 3·95 −164·0

Table IV. Summary of results for bit ipping algorithms with L=64. The values of Pn and Pb are in dB

N Fk PRF System B System C System D System E

( kHz) Pn Pb Pn Pb Pn LA Pb Pn LA Pb

4 2 705·6 2·35 −96·0 2·30 −97·1 3·20 1 −104·6 3·10 1 −109·73 470·4 1·50 −79·7 2·20 −95·4 2·80 1 −99·6 2·55 2 −100·44 352·8 1·05 −68·4 2·05 −96·4 2·40 2 −90·8 2·55 2 −100·1

5 2 705·6 2·25 −104·0 2·15 −105·0 2·85 1 −112·6 3·00 1 −120·43 470·4 1·40 −84·3 2·10 −104·8 2·70 1 −109·4 2·55 2 −110·34 352·8 1·05 −71·8 2·05 −104·8 2·15 2 −97·3 2·50 2 −110·0

6 2 705·6 2·10 −109·4 2·10 −111·7 2·75 1 −120·7 2·95 1 −129·43 470·4 1·45 −89·5 2·10 −112·1 2·55 1 −116·1 2·50 2 −118·64 352·8 1·05 −74·1 2·05 −111·8 2·15 2 −104·6 2·45 2 −118·0

7 2 705·6 2·10 −115·1 2·10 −117·4 2·70 1 −127·6 2·90 1 −137·13 470·4 1·40 −91·5 2·10 −118·0 2·45 1 −121·6 2·55 2 −126·34 352·8 1·00 −73·1 2·10 −118·3 2·00 2 −107·3 2.50 2 −125·7

8 2 705·6 2·00 −121·1 2·10 −122·5 2·70 1 −134·5 2·90 1 −144·33 470·4 1·35 −91·9 2·10 −123·0 2·40 1 −126·5 2·55 2 −132·74 352·8 1·10 −77·2 2·10 −123·4 1·90 2 −109·1 2·50 2 −131·9

cannot be achieved for the oversampling ratios shown. To achieve the target PRF, a lower oversampling ratiois required, with a commensurate order increase to achieve the target baseband noise power.

5.4. Systems B–E: bit- ipping algorithms

Table IV shows the results for the di�erent bit ipping algorithms with L=64. For all algorithms thenoise power increases with Fk and the maximum power gain Pn reduces with Fk , indicating that the stabilitydecreases with Fk . This is because a higher rate of bit ipping is required to achieve lower PRFs and thiscompromises both the noise performance and stability of the modulator. The main exception to this is System C(PRF control and alternation constraint), where the reduction in stability and increase in noise power withFk are fairly small. The alternation constraint is very successful at improving the modulator performance,with signi�cant gains in performance over System B, especially at low PRFs. For Fk =2; 3 even greater gainsin performance are achieved by the use of look-ahead (System D). For Fk =4 the look-ahead algorithm isinferior to the alternation constraint because two levels of look-ahead are required to achieve the low PRF



Table V. Performance of example systems with mismatched rise and fall times

System N Pn Fk Alt. LA Pb (ideal) Pb (mismatch) Max. PRF(dB) (dB) (dB) amp. (dB)

A 7 4·00 — — — −111·9 −83·6 —C 6 2·05 4 Yes — −111·8 −92·5 −14·4D 8 1·90 4 — 2 −109·1 −106·0 −0·07E 5 2·50 4 Yes 2 −110·0 −91·3 −16·1

Figure 14. Baseband spectral responses for (a) System A and (b) System C

(owing to the lower PRF bound introduced by the look-ahead algorithm). The additional level of look-aheadcompromises stability and noise performance.The best performance is achieved by System E which uses all three algorithms: PRF control, alternation

constraint and look-ahead. Notice that for this algorithm two levels of look-ahead are now required for Fk =3,resulting in a higher noise power than would otherwise be achieved. This is because a greater restriction isplaced on the bit ipping than with the individual algorithms. The lower PRF bound is therefore tighter andtwo levels of look-ahead are required to relax the bound.The three systems which achieve the target performance of a PRF of 352·8 kHz with a dynamic range of

98 dB (for MSA=0·3, Pb = 108·5 dB) with minimum possible NTF order are shown in the table in bold type.

5.5. Performance with non-ideal output stage

In this section we assess the performance of these three systems for an output switch with mismatchedrise and fall times and compare the performance with that of a standard �� modulator (L=32; N =7 inTable III). The four systems are summarized in Table V.The mismatch is simulated by modifying the output y(k) of the modulator using equation (32) of the

Appendix and a simulation is performed to determine the spectrum of the modi�ed output. This is comparedwith the spectrum of the ideal output. A mismatch of 1 ns has been chosen.The spectra obtained for the systems are shown in Figures 14 and 15. In all cases the upper curves are for

a rise=fall mismatch of 1 ns and the lower curves are for an ideal output stage. The results are summarizedin Table V. The table also shows the amplitude of the tone present at the PRF measured from wideband



Figure 15. Baseband spectral responses for (a) System D and (b) System E

spectral plots. Especially good results are obtained for System D. The out-of-band spectral response of thissystem is characterized by a high-amplitude tone at the PRF. This indicates very strong periodicity in thebitstream; therefore the PRF is very uniform and there is low sensitivity to mismatched rise and fall times.A possible reason for the strong periodicity is that this system has no alternation constraint, so it is usuallypossible to ip a bit immediately upon deviation from the average PRF (assuming that the look-ahead does notseriously constrain the bit ipping). Conversely, when the system is controlled by the alternation constraint,the system may have to wait before bit ipping is allowed. This would result in an instantaneous deviationfrom the average PRF, observed spectrally as a reduction in the amplitude of the tone at the PRF. Therelationship between the amplitude of the tone at the PRF and the sensitivity to mismatched rise and falltimes is con�rmed in Table V, which shows that the sensitivity to mismatch increases as the tone amplitudereduces.All the bit ipping algorithms have superior performance to the �� system with no bit ipping.

6. CONCLUSIONS

In this paper we have shown how �� modulation may be applied to power D–A converters. It has been arguedthat pulse width modulation systems are non-ideal owing to the high clock rate, which makes implementationdi�cult, and the requirement of a linearization algorithm. �� modulation is an attractive alternative owingto its low clock rate and high linearity; however, the average pulse repetition frequency (PRF) is too highfor e�cient conversion and input signal dependence leads to the introduction of noise and distortion in thepresence of a non-ideal output stage.The technique of bit ipping has been used to regulate and lower the PRF. Various algorithms have been

discussed which control the bit ipping in such a way as to minimize the resulting increase in baseband noisepower and degradation to stability. By means of simulations it has been shown that a combination of thetechniques of look-ahead and alternation constraint leads to optimal performance with an ideal output stage.With an output stage with unequal rise and fall times the optimal algorithm has PRF control and look-ahead.The spectral response indicates strong periodicity at the PRF; however, this leads to poor coding e�ciency, asindicated by the requirement of a high-order noise-shaping �lter and hence a high-order analogue reconstruction�lter. There is therefore a trade-o� between the system complexity and the sensitivity to a non-ideal switch.



APPENDIX: POWER SWITCH NON-IDEALITIES

In this appendix we brie y consider how unequal rise and fall times in the power switch in uence theperformance of a �� power D–A converter. In terms of linear errors, �nite switching times cause themagnitude response to be attenuated at high frequencies. 6 The main concern here, however, is the e�ect ofnon-linear errors, i.e. how the linearity of the conversion to analogue is a�ected.A simple model for the non-linear artefacts of �nite switching times has been proposed in Reference 16,

in which the change in area under the output wave-form due to �nite rise and fall times is expressed in thedigital domain as an error impulse which occurs on every transition. This technique is based upon the methodused in Reference 17 for modelling clock jitter errors with multibit signals. The main assumption made is thatthe errors occur at the sample instant rather than being smeared with time—this assumption is more valid forsmaller rise and fall times.On every transition the error impulse is obtained by expressing the error area as a ratio of the oversampling

period Ts.17 For an output signal of ±1 the error impulse for a rising edge of time tr has strength

er = − 2(tr=2Ts

)= − tr

Ts= − Lfstr (23)

and the error impulse for a falling edge of time tf is

ef = Lfstf (24)

A simpli�ed approach to analysing the e�ects of these errors is to consider how the DC component varieswith the input signal level.18 For a PWM system the PRF is constant, so the DC component is independentof the input signal. Unequal rise and fall times will result in a constant DC o�set which is proportional tothe PRF.It is shown in Section 5 that the PRF of a �� modulator varies non-linearly with the input amplitude. For a

DC input a DC error will be introduced which varies non-linearly with the input amplitude. By modellinga band-limited time-varying input as a slowly varying DC input, it can be seen that for a band-limited inputa ‘short-term’ DC error will occur which varies non-linearly with the input level. In Section 5.5 it is shownby simulation that this variation gives rise to harmonic distortion18 and intermodulation (foldback) noise.An error sequence is now derived for a one-bit converter with rise and fall times tr and tf respectively. For

an ideal output sequence y(k) a transition will occur whenever y(k) 6=y(k−1). The following two expressionsrepresent sequences which have the value of unity for a rising transition (i.e. −1→ +1) and falling transition(i.e. 1→ − 1) respectively:

14 (y(k)− y(k − 1))(1 + y(k)) (25)

14 (y(k)− y(k − 1))(1− y(k)) (26)

These two expressions can be combined to derive the error sequence

�(k) = 14 (y(k)− y(k − 1))[(1 + y(k))er + (1− y(k))ef ] (27)

=Lfs4(y(k)− y(k − 1))[(1 + y(k))tr + (1− y(k))tf ] (28)

De�ning the di�erence in rise and fall times as �t= tr − tf , equation (28) can be re-expressed as�(k)= �l(k) + �n(k) (29)

where

�l(k) =Lfs2(y(k)− y(k − 1)) (30)

�n(k) =Lfs�t4(y(k)− y(k − 1))(y(k)− 1) (31)



The term �l(k) represents a linear �ltering operation. The term �n(k) represents the non-linear componentof the error and is equivalent to the error sequence derived in Reference 16. The magnitude of this errordepends on the di�erence in rise and fall times and the frequency of occurrence of the error is related to thebitstream transition rate. Owing to the squaring of the term y(k), second-harmonic distortion is likely.16

Taking into account the non-linear component only, the system output including this error source is

y′(k)=y(k) + �n(k) (32)

This sequence has been modelled and simulated with the bit ipping system and results are presented inSection 5.5.

REFERENCES

1. M. S. Pedersen, ‘All digital power ampli�er based on pulse width modulation’, 96th Convention of the Audio Engineering Society,J. Audio Eng. Soc. (Abstracts) 42(5) (May 1994), Amsterdam, Preprint 3809.

2. R. E. Hiorns, ‘Digital signal processing and circuit design for PWM DACs’, Ph.D. Thesis, King’s College, University of London,1994.

3. S. P. Leigh, P. H. Mellor and B. M. G. Cheetham, ‘The implementation and performance enhancement of a completely digitalpower ampli�er’, Proc. Inst. Acoust. 12(8), 67–75 (1990).

4. J. M. Goldberg and M. B. Sandler, ‘New high accuracy pulse width modulation based digital-to-analogue converter=power ampli�er’,Proc. IEE, 141, pt. 315–324 (1994).

5. M. O. J. Hawksford, ‘Dynamic model-based linearization of quantized pulse-width modulation for applications in digital-to-analogueconversion and digital power ampli�cation systems’, J. Audio Eng. Soc., 40, 235–251 (1992).

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8. R. Schreier, ‘An empirical study of high-order single-bit delta–sigma modulators’, IEEE Trans. Circuits and Systems, CAS-40,461–466 (1990).

9. R. W. Adams, P. F. Ferguson Jr., A. Ganesan, S. Vincelette, A. Volpe and R. Libert, ‘Theory and practical implementation of a�fth-order sigma–delta A=D converter’, J. Audio Eng. Soc., 39, 515–528 (1991).

10. P. T. Maguire and Q. Huang, ‘Quantizer gain in N th-order sigma–delta modulator linear models: its determination based on constantoutput power criterion’, Proc. IEEE Int. Symp. on Circuits and Systems, IEEE, New York, 1994, pp. 333–336.

11. A. J. Magrath, ‘Algorithms and architectures for high resolution sigma–delta converters’, Ph.D. Thesis, King’s College, Universityof London, 1996.

12. O. Feely, ‘Theory of lowpass and bandpass sigma-delta modulation’, IEE Colloq. on Oversampling and Sigma-Delta Strategiesfor DSP, UK ISSN 0963-3308–Reference 1995/217, November 1995.

13. M. Motamed, A. Zakhor, S. Sanders and T. Lee, ‘Spectral characteristics of the double-loop �� modulator’, Proc. IEEE Int.Symp. on Circuits and Systems, IEEE, New York, 1996, pp. 457–460.

14. A. J. Magrath and M. B. Sandler, ‘Non-linear deterministic dithering of sigma–delta modulators’, IEE Colloq. on Oversamplingand Sigma–Delta Strategies for DSP, UK ISSN 0963-3308–Reference 1995/217, November 1995.

15. L. Risbo, ‘Sigma–Delta modulators – stability analysis and optimisation’, Ph.D. Thesis, Technical University of Denmark, 1994.16. L. Risbo, ‘FPGA based 32 times oversampling 8th order sigma–delta audio DAC’, 96th Convention of the Audio Engineering

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A use of sigma-delta modulation in power digital-to-analogue conversion