Solid-State Ekct,vnics Vol. 23. pp. 687-692 0 Pergamon Press Ltd., MO. Printed in Great Britain

A UMOS POWER FIELD EFFECT TRANSISTOR

DAVID A. SMITH and C. A. T. SALAMA

Department of Electrical Engineering, University of Toronto, Toronto, Ontario, Canada, MSS IA4

(Received 16 March 1979; in revised form 27 October 1979)

Abstract-A power MOST switch fabricated using a U-shaped groove anisotropically etched in silicon is described. The structure provides a short channel while maintaining a reasonable breakdown voltage. Devices with a channel length of 2-3 /.~rn and an active area of 0.23 mm* exhibit breakdown voltages ranging from 35 to 45V with a current handling capability of IA and a switching time of less than 5 “sec.

INTRODUCTION

MOS transistors have recently been developed to com- pete with bipolar transistors in the medium and high frequency power amplification and switching fields. As high frequency power amplifiers and switches MOS transistors have several advantages. Because MOSTs have very high input impedances, their inputs are more easily matched to standard 5Ofi high frequency systems. In addition the drain current of a MOST has a negative temperature coefficient, thus making the device thermally stable at high power levels and permitting devices to be connected in parallel for high current applications. Also MOSTs do not suffer from the minority carrier storage effects associated with bipolar transistors and they are, in general, simpler to fabricate.

Within certain bounds, the current handling capability per unit area and the switching speed are improved by shortening the channel length. Advances in the area of electron beam and x-ray lithography have made possible the realization of MOS devices with drain-to-source spacings of the order of I-2pm. Unfortunately the drain-to-source breakdown voltage for such short chan- nel MOSFETs is limited to very low levels by drain-to- source “punch-through”, making them impractical as high power devices.

Several novel enhancement-mode power MOST structures [ I-31, suitable for high-speed switching and amplification applications, have been developed in the last few years to improve the voltage capability of short channel MOS devices. These include the double diffused MOST (DMOST) [l], the V-groove MOST (VVMOST) [2] and the angle evaporated MOST (AEVMOST) [3].

This paper describes the structure and operating characteristics of a n-channel MOS power transistor which is fabricated on a p-type (100) substrate using an anisotropic etch to form a trapezoidal U-shaped groove (UMOS), which isolates the source and drain regions and defines the channel [4,5]. The resulting device has high transconductance and current handling capability per unit area due to the fact that the channel is on the (100) plane which is characterized by high carrier mobility and saturation velocity. Furthermore, the device’s break- down voltage is maintained at a reasonable level without the use of a high resistivity drift region, thus minimizing

687

the on-resistance. As will be shown, this device offers certain advantages over both the DMOST and VVMOST structures particularly from the point of view of sim- plicity of fabrication.

STRUCTURE

The cross section of a portion of the UMOS power transistor is shown in Fig. 1. The device is fabricated on an n’/p (100) silicon substrate. A trapezoidal U-shaped notch, anisotropically etched into the n+ layer, is used to define the channel at the surface of the p-type substrate. This structure offers several advantages. The channel length L is determined by the depth of the notch 4 and the width of the window W opened in the oxide and is given by L = W - v(2Xi). The dimensions W and Xj can be accurately controlled to permit the fabrication of short channel devices without the use of submicron photolithography. Since the source-drain junctions depletion regions extend almost vertically into the sub- strate, their effect on the channel length is minimized, resulting in large punchthrough voltages. Furthermore, the parasitic drain and source resistances are low since the n+ regions are as deep as the grooves (- 2pm).

DESIGN CONSIDERATIONS

The power capability of an MOS transistor is limited by its drain-to-source breakdown voltage and its current handling capability per unit area. An additional con- straint is that the channel temperature must be kept below a certain maximum value (typically 175°C). Thus the power capability of the mounted and packaged tran- sistor is limited by its ability to dissipate, into the sur- rounding ambiept, power generated in the device.

i I

P si (100) f

b, Fig. 1. Cross-section of a portion of the UMOS power transistor.

688 D. A. SMITH and C. A.T. SALAMA

The performance of a MOST operated as a switch is characterized by its current handling capability, its transconductance, its threshold voltage, its on resistance, its breakdown voltage and its switching time. These electrical characteristics can be related to device and material parameters so as to specify the design criteria for optimization of overall device performance.

A simple theory for the UMOST taking into account velocity saturation effects and gate voltage dependence of the mobility was presented previously [5]. Assuming negligible penetration of the source and drain space charge regions into the channel the threshold voltage is given by the standard equation;

where &,s is the metal-semiconductor work function, & is the Fermi potential, Qss is the oxide charge per unit area, Qs is the bulk charge per unit area, and Co is the gate oxide capacitance per unit area. The on resistance of the UMOST is given by

where

p - PCOZ L

(2)

(3)

and V, is the gate voltage p is the mobility of electrons in the channel, C, is the gate oxide capacitance per unit area, Z is the channel width and L is the channel length. The channel mobility p is gate voltage dependent and is given by

tL= l ; “:- VT

(4)

VK

where p. is the zero field mobility and V, is the effective gate voltage at which the measured mobility of electrons is $ of its value at Vc - VT = 0. The source and drain series resistances can be neglected in the UMOST. Considering eqn (2), the factors C, and ( Vc - VT) are critical in determining yield and reliability and are con- sidered fixed. The value of the mobility p is determined by the quality of the etched surface at the bottom of the groove. Therefore in order to minimize on-resistance the design goal is to maximize Z/L. The minimum value of L is related to the maximum drain voltage. Furthermore for a constant area chip, the higher the channel density (channel width per unit area) the lower the on-resistance.

Under velocity saturation operation, the maximum current handling capability is limited by the maximum allowable effective gate voltage ( Vc - VT) (restricted by gate dielectric breakdown considerations to ap- proximately IW) and is given by

I &on) = C,Zu,( VC - VT) (5)

where v.? is the saturation velocity. In practical, high channel-density power devices, the current is often limited by current density constraints in the metallization 161.

The maximum transconductance under velocity saturation is given by

&(rlw, = cozv, (6)

and is independent of the drain and gate voltages as well as the channel length.

Therefore, in order to maximize current handling capability and transconductance, large values of Z and u, are required when the channel length is short enough to cause velocity saturation.

In the short channel UMOST, the drain to source voltage capability is limited by two mechanisms: drain to source punchthrough and avalanche breakdown at the drain junction. In order to obtain an approximate esti- mate of the voltage handling capability of the UMOST simple expressions derived for standard MOSTs were used. A more accurate estimate of the breakdown characteristics of the UMOST requires a two dimen- sional analysis which was not attempted here.

Punchthrough occurs when the drain space charge region reaches the source space charge region. The punchthrough voltage VpT of a standard MOST can be estimated from the following expression[7]

(7)

where N,., is the doping concentration in the p-type substrate, l s is the dielectric constant of silicon, & is the drain junction barrier potential, ri is the junction radius of curvature near the Si-SiOz interface and L’ is the effective channel length given by

From eqn (7) it is obvious that to increase the punchth- rough voltage one has to increase Na and decrease rj.

Since the UMOS structure effectively simulates a MOST with very shallow junction depth, eqn (7) can be used to estimate the punchthrough breakdown of the UMOST.

The avalanche breakdown of the drain diode in a standard MOST is strongly dependent on the impurity doping concentration in the substrate and is also affected by the points of maximum curvature (hence the junction depth) of the drain diffusion and by the proximity of the gate electrode to the depletion region located near the drain end of the channel.

In the UMOS structure, the junction curvature effect is minimized and the avalanche breakdown occuring near the surface is mainly affected by the proximity of the gate electrode. The avalanche surface breakdown voltage can be estimated from an expression derived by de Graaf[l] relating the breakdown field ERR and the

A UMOS power field effect transistor

Fig. 2. Photomicrograph of the UMOS power transistor.

689

Fig. 6. Experimental switching characteristics (output: upper

waveform; input: lower waveform; source impedance: 500).

A UMOS power field effect transistor 691

breakdown voltage VBR. This expression was developed using a two-dimensional plane diode approximation of the drain n’/p junction area and introduces an empirical parameter k which is proportional to the depth under- neath the gate oxide at which the electric field near the drain is assumecl to depart from the normal to the surfacet. For the case in which the substrate doping is not too high and the oxide thickness is not too thick (NA < 5 x IOZOX,~ “2; xoo in Angstrams) the expression is

PI

I/Z

where xoo and e0 are the gate oxide thickness and dielec- tric constant respectively. The surface avalanche break- down voltage is therefore proportional to the square root of the gate oxide thickness. Therefore in order to opti- mize the voltage handling capability of the UMOST a proper choice of the substrate doping and gate oxide thickness must be made.

A useful figure of merit for the switching speed of the device is the time constant obtained from the product of the on-resistance and the gate capacitance. This time constant must be minimized. In order to reduce the total gate capacitance in the UMOST it is necessary to mini- mize the overlap capacitance over the n+ sidewall regions in the groove. This can easily be done by taking advantage of the fact that the linear growth rate constant of the thermal oxide grown on the heavily doped n+ type (I Ii) sidewalls is considerably larger than on the p-type (100) substrate [IO]. For thin oxide layers, the oxide thickness on the sidewalls can be 1.5-2 times greater than at the bottom of the groove. In general, the total input gate capacitance of the UMOST is given by

c,N=z[~t~(y)~3+~yo”} (IO)

where xoo is the oxide thickness over the (100) plane at the bottom of the groove, x0, is the oxide thickness over

the (I I I) sloping sides of the groove, x,,f is the field oxide thickness and yO,, is the overlap of the gate metallization over the field oxide.

EXPERIMENTAL RESULTS

To study the performance of the structure, power devices were fabricated on p-type (100) orientation sili- con substrates 6.9ohm-cm resistivity. A micrograph of the fabricated UMOS power transistor structure is shown in Fig. 2. The minimum linewidth used in the mask layout was 7 ym. The device has a channel width of 5500 pm, a channel length of 3 +m and an active area of 0.23 mm*. The typical IV characteristics of the device

Walues of k --I&m and EBR =60V/pm have been found by de Graaf[E] to give the best fit for surface breakdown over a

wide range of MOS transistors. Values of k - 0.5 pm have also

been reported by Klaassen[9] for short channel shallow junction MOSTs.

$These characteristics were obtained on probed unencap-

sulated devices.

are shown in Fig. 3. The threshold voltage for this particular device was 0.4 volts at -4V substrate bias. The saturation of the characteristics is clearly visible at higher drain voltages. The looping at higher currents is

mainly due to heating effects.4 Threshold voltages, measured with the gate shorted to

the drain and at a drain current of 0.5 mA, agreed fairly well with threshold values obtained from the extrapola- tions of the I/& vs V, plots. The threshold voltage of the devices with a channel length larger than 2pm was found to be almost independent of drain voltage an indication of lack of short channel effects associated with spreading of the drain depletion region into the channel.

The on-resistance of a 3pm channel length device is shown in Fig, 4. For this particular device, the mobility at low gate voltages was found to be 500cm2/volt-set in agreement with reported values for standard NMOSTs fabricated on (100) orientation silicon [ 111. At higher gate voltages mobility reduction takes place and the on-resis- tance increases. A fit of eqn (4) to the experimental data resulted in a value of V, = 10 V. The R,, x Z product for the device is 3.3 ohm-cm at VG = 10 V which com- pares very favourably with that of other MOS power transistor structures[4]. The increase of R,. with in- creasing temperature is approximately 1.3%“C and is mainly attributed to the negative temperature coefficient of mobility.

The maximum current handling capability of the device (duty cycle = 1%) is 1.6 A at a gate voltage of 16 V. However restricting the current density in the source and drain metallization to 5 x 10' A/cm* implies that the current in the device (with a metallization thickness of I pm) must be limited to 900 mA. This value was taken as the maximum rated current I,,,,, in power calculations.

The transconductance vs gate voltage of the device saturates at a value of g,,,/Z = 17.3 mho/mm. The cor- responding saturation velocity is u, = 4.6 x IO6 cm-sec. The transconductance exhibits a negative temperature coefficient of 0.14%/Y. This temperature coefficient is

mainly attributed to the temperature dependence ol” the saturation velocity[l2] and results in a device which is thermally stable and free of thermal runaway problems.

Drain to source breakdown at low current levels (I mA) occurs around 3545 V and is characterized by the hard breakdown attributed to gate controlled

v, (W

Fig. 4. On-resistance vs gate voltage.

*t

and by using short gate branches. Reducing the line width and line separation to 5 pm would also result in a

-10 0 VGD PO +‘O considerable increase in packing density and current

Fig. 5. Input, output and feedback capacitances of the UMOST. handling capability. Finally, the dc power dissipation can be improved by thinning down the substrate and by using

avalanche multiplication. The measured experimental a more appropriate package such as a TO-3. breakdown voltages agreed very well with the values predicted from eqn (9). No evidence of soft punch- Acknowledgements-This work was supported by the National

through breakdown was observed. Science and Engineering Council of Canada.

The power handling capability of the transistor is limited by the maximum allowable channel temperature

REFERENCES

(175°C) of the UMOST and by the thermal resistance of I. H. J. Siag, G. D. Vandelin, T. D. Gauge and J. Koesis, IEEE

Trans. E[&tron Deu. ED-19, 45 (1972). the chip and the package. For the particular devices 2. M. V. Kooi and L. Raele. Electronics 49. 98 (19761

under consideration, the maximum power dissipation Pd 3. J. G. Oakes, R. A. Wickstrom, D. A. Tremere and T. M. S.

was found to be 2.1 W and the intrinsic thermal resis- Heng, IEEE Trans. Microwave Theory and Techniques MTT-

tance of the chip and package was ‘JO”C/Wi’. 24, 305 (1976).

4. C. A. T. Salama and J. G. Oakes, IEEE Trans. Electron Lb. The input, output and feedback capacitance charac- EIL25, 1222 (1978).

teristics of the device are shown in Fig. 5 and were 5. C. A. T. Salama, Solid-St. Electron. 20, 1003 (1977).

measured at 1 MHz using a 3-terminal bridge. 6. H. R. Camenzind, Electronic Integrated System Design, p.

The switching response of the device, operated as a 184. Van Nostrand Reinhold. New York (1972).

I. G. Merckel, Process and l&ice Model/inn for Intearated simple inverter with a load of 33fl and a supply voltage Circuit Design, (Edited by F. Van de Wiele,-W. L. Engl and of 15 V, was measured and the typical waveforms are P. J. Jespers), p. 705. Noordhoff, Amsterdam (1977).

illustrated in Fig. 6. The rise and fall times of the device 8. H. C. De Graaf, Philips Res. Repts. 25, 21 (1970).

are typically 5 ns. 9. F. M. Klaassen, Solid-St. Ele&on. 21, 565 (1978).

IO. C. P. Ho, J. D. Plummer and J. D. Meindl. J. Electrochem. Sot. 125,665 (1978).

692 D. A. SMITH and C. A. T. SALAMA

CONCLUSION

The capabilities of the UMOST structure as a power transistor switch were investigated in this paper. The structure compares favourably with other MOS power structures, especially in the area of high current, high speed switching. The fabrication process for the UMOST is far simpler than that of other high power MOS devices and the UMOST has the added flexibility of being a 4-terminal device.

The UMOST device characteristics can easily be optimized. The drain to source breakdown voltage can be increased by increasing the gate oxide thickness, this increase occurs at the expense of a corresponding in- crease in on-resistance. The device layout can be opti- mized for high speed applications by minimizing metal- lization overlap over the field oxide, by reducing parasi- tic capacitances associated with the gate and drain pads

tThe devices were fabricated on a 220 pm thick substrate and 11. D. L. Critchlow, R. H. Dennard and S. E. Schuster, IBMJ. Res. mounted in T@S packages which severely restrict their power Den 16, 1407 (1973). dissipation capabilities. 12. F. F. Fang and A. B. Fowler, J. Appl. Phys. 44, 1825 (1970).