A typical design flow involves subsequently refined layout steps. The first step is a course planning of the chip called floorplanning. This is followed by IO and cell placement, special net routing, clock tree synthesis, in-place optimization, and finally global and detailed routing.Between most of these steps we perform a timing analysis on the circuit to determine its performance and see if we need to back up. The timing analysis is run with the following commands: buildTimingGraph timeDesign -preCTS -idealClock -numPaths 10 -prefix preCTS

The options to the command timeDesign will change depending on which part of the flow you are in.Your design is read in by modifying the .conf file in the flow. There are specific lines to specify: the IO pads (.io), the input netlist (.mapped.v), the Synopsys design constraint file (.sdc), the timing library format (.tlf) file, the layout exchange format (.lef) file (which is the actual cell pins and boundaries), and numerous other parameters. This is loaded with the following command: loadConfig ./encounter.conf commitConfig

FloorplanningThe floorplan stage defines the rows that the standard cells will go in. For small designs, it is sufficient to make a single floorplan and place everything in the hierarchy at once. This is called "flat" placement. If you have a large design or memories, you may have to customize this floorplan a little more by specifying the relative locations and sizes of the different blocks (sub-modules of your entire design) and the locations of the fixed size memories.You can create a flat floorplan like this: floorplan -r 1.0 0.9 1 1 1 1This says that it should have a 1.0 aspect ratio (height to width), 90% row utilization, and have space of size "1" around the core. (This is probably in the default units specified in the .lef file.)After you specify the rows, you also need to specify how the vdd and gnd signals connect to the rows. This is done by adding a power ring around the perimter of the design and stripes internal to the design. To really know the size of these wires, you will have to do power grid analysis after placement. This is not required in this project. addRing -spacing_bottom 10 -width_left 10 -width_bottom 10 -width_top 10 -spacing_top 10 -layer_bottom metal3 -width_right 10 -around core -center 1 -layer_top metal3 -spacing_right 10 -spacing_left 10 -layer_right metal4 -layer_left metal4 -nets { gnd vdd } addStripe -set_to_set_distance 100 -spacing 5 -xleft_offset 50 -layer metal4 -width 5 -nets { gnd vdd }

PlacementAfter the power is specified, you can place the cells in your design using the following command: placeDesignSpecial Net RoutingOnce the cells are placed, you can connect the power stripes and rings to the standard cell rows. sroute -noBlockPins -noPadRingsYou should also perform a trial routing to see if any cell pins are inaccessible due to power routing: trialroute

In-Place OptimizationAt this time, it is a good idea to do Pre-CTS Timing Analysis: buildTimingGraph timeDesign -preCTS -idealClock -numPaths 10 -prefix preCTSThis will give you an idea if your placement is way off and there is no chance for timing. If this is the case, you can first try to do "in place" optimization to fix the timing. This is done with the following commands: optDesign -preCTSIf that doesn't meet timing, you will have to change your IO assignment or change your floorplan.

Clock Tree SynthesisThe previous timing analysis used an "ideal clock" with zero skew since the clock was not implemented yet. You can now create a clock tree using the following commands: createClockTreeSpec -output encounter.cts addCTSCellList CLKBUF1 CLKBUF2 CLKBUF3 clockDesign -clk clkwhere your clock is named "clk". You can investigate the results of the clock tree synthesis (CTS) by extracting the clock wire parasitics and analyzing the clock tree: extractRC reportClockTree -postRoute -localSkew -report skew.post_troute_local.ctsrpt

Post-CTS In-Place OptimizationThis is now a good time to check the timing of your placement with a real clock tree. The clock synthesis could have moved some cells to place clock buffers or could have too much skew to meet timing: setAnalysisMode -checkType setup -asyncChecks async -skew true -clockPropagation sdcControl buildTimingGraph timeDesign -postCTS -numPaths 10 -prefix postCTSIf there are problems with the timing, you can perform a post-CTS in-place optimization with a new parasitic mode to include the clock design: setExtractRCMode -engine preroute -assumeMetFill extractRC optDesign -postCTSThen you can check timing again: buildTimingGraph timeDesign -postCTS -numPaths 10 -prefix postCTS

Filler CellsAt this point, you will have to add "filler" cells wherever there are no cells so that the power rails in the rows are connected. These filler cells often also have "fill" material to improve CMP by increasing density of different layers: addFiller -cell FILL -prefix FILL -fillBoundaryRoutingYour placement is now fixed and you need to begin the routing. You first must specify how to connect the special pin types in the library: globalNetConnect vdd -type tiehi globalNetConnect vdd -type pgpin -pin vdd -override globalNetConnect gnd -type tielo globalNetConnect gnd -type pgpin -pin gnd -overrideThen you can route the entire design: globalDetailRouteand perform post-routing timing analysis:

setExtractRCMode -engine postRoute extractRC buildTimingGraph timeDesign -postRoutealong with an optional in-place routing optimization: optDesign -postRoute

Final ChecksAt this point, you should perform a final "sign-off" timing analysis inside Encounter using accurate parasitic extraction: setExtractRCMode -engine signOff extractRC buildTimingGraph timeDesign -signOff Right now, this is not working because we do not have "qrc" (the extractor) installed properly. You can use "-postRoute" instead for now.You should also make sure there are no geometry (DRC) or connectivity (LVS) errors: verifyGeometry verifyConnectivity -type allNote that for a real final design, you would perform DRC and LVS in Virtuoso much like you did in the custom design homeworks.Save OutputAs a final step, you can save the layout: streamOut final.gds2 -mapFile gds2_encounter.map -stripes 1 -units 1000 -mode ALL(for streamOut to work the file gds2_encounter.map must be in the folder you run encounter in) and the modified Verilog netlist: saveNetlist -excludeLeafCell final.vand the parasitics for all of your routing: rcout -spf final.dspfThe gds2 file is sent to a fabrication plant for manufacturing while the final.v and final.dsp files are used for your sign-off timing analysis in Primetime.Overview of File Types.lib/.db - Synopsys "liberty" file for Design Compiler. This contains information about the logic function, timing, and power of all the cells in your library. The db file is just a compiled (binary) version..lef - Cadence Library Exchange Format for Encounter. This contains the geometric information about your library cells such as pin locations/layers, boundary, and routing blockages..tlf - Timing Library Format for Encounter. This contains the timing information of the library cells..tcl/.scr - TCL scripts that could be for Design Compiler, Encounter, or Primetime..v/.mapped.v - The unsynthesized and synthesized (gate-level) netlist, respectively..io - A proprietary file for Encounter that specifies which IO pads should be used for which IOs on your top module..sdc - Synopsys Design Constraints. This is a file that contains the definitions of your clocks, input/output delays and other design constraint information to pass between tools. Synopsys saves this file after you set up the constraints and Encounter/Primetime can read the file later so that the same constraints are used.Notes on 45nmIf you want to synthesize a design using the Nangate FreePDK45 cell library, you need to make a few changes:1) You need to compile the Nangate .lib into a .db and use that. To do this, run:dc_shell-tThen execute these commands:read_lib /mada/software/techfiles/NangateOpenCellLibrary_PDKv1_3_v2009_07/liberty/NangateOpenCellLibrary_typical_conditional_ccs.lib write_lib NangateOpenCellLibrarywhich will create a file NangateOpenCellLibrary.db. Move that to your project directory.2) Then, these lines change to the compile_dc.tcl:set search_path [concat $search_path . ]set link_library [set target_library [concat [list NangateOpenCellLibrary.db ] [list dw_foundation.sldb]]]

3) In the encounter.conf, you need to reference the .lib file instead of the .tlf file. You also need to point to the .lef file. Specifically, these lines change:set OSUcells /mada/software/techfiles/NangateOpenCellLibrary_PDKv1_3_v2009_07set rda_Input(ui_timelib) "$OSUcells/liberty/NangateOpenCellLibrary_typical_conditional_ccs.lib"set rda_Input(ui_leffile) "$OSUcells/lef/NangateOpenCellLibrary.lef"