A Tutorial on Timing Equations by S Schwartz (TUG 2000 Paper)

7/31/2019 A Tutorial on Timing Equations by S Schwartz (TUG 2000 Paper)

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A Tutorial on Timing Equations

Steve SchwartzMotorola


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Printed in Teradyne Users Group Proceedings, 2000

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Steve Schwartz, Motorola

Abstract

This paper presents the fundamental principles of timing equations for ATE with "on the fly" timing. The

technique will show how to generate robust functional tests that can be shmoo'ed over a wide range of operating

conditions and parameters. Several examples are presented with the results showing the robustness of theequations.

Introduction

This paper is going to present and apply the fundamentals of generating robust timing for the complex ICs that

are being developed today. The methods are applied to a conceptually simple device with the features to showhow to implement these principles.

The J971 tools are used extensively to show all of the views of the operation of the device that an engineer

would use. The fundamental principles are common knowledge. It is the application of those principles that

produce robust functional tests.

Fundamental Principles

The most important principle of digital IC timing is that outputs switch due to the switching of some input. (See

Fig 1) In the "old" days, the time difference between the input edge and the output edge was called propagation

delay or prop delay for short and the symbol was tpd. More recently, they have transformed into "output valid"times.

This principle holds for both simple gates such as NANDs, and NORs and also for latches and flip-flops whichmake up the registers and states of our digital world. With these memory elements, the inputs are differentiated

between clocks that cause outputs to change state and data that doesn't. This leads to the next fundamental

principle of input setup and hold times.

For a sequential circuit to work properly, the data presented to each memory element must be held at the correctstate at the appropriate time with respect to the clock. For each bit there is a point in time where the level on the

input determines the value that the bit will hold. (See Fig 2)

Output

Input

Fig 1


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In this simple world, the setup time and the hold time correspond to the same thing - that critical instant that the

data is sampled and saved. It is only when there are multiple bits involved that the setup and hold times definea span of time that the multiple data line must be held static for all the correct values to be loaded into those

bits.

If the 2 latches have the same internal setup time the external setup and hold times are a function of the

individual clock and data paths. (See Fig 3) The external setup time is equal to the internal setup time plus thedata path delay minus the clock path delay. For multiple bits, the earliest setup time of all the bits is the setup

time for the whole register. The latest setup time corresponds to the hold time for the whole register.

Definition:

Input Setup Time is the time before the clock when the data must be held valid.

Therefore positive setup times occur before the clock and negative setup times occur after the clock.

Definition:Input Hold Time is the time after the clock when the data must be held valid.

Therefore positive hold times occur after the clock and negative hold times occur before the clock.

CLK

Datai

Dataj

Fig 3

Clock

Early Input

Late Input

Setup

Time

=> Bit goes to a 1

=> Bit goes to a 0

Fig 2


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3

Not all combinations are possible. The setup time must occur before the hold time. This is an excellent check

to see if you are generating bogus data when making these measurements.

Positive SU Times

Negative Hold Times

Negative Setup Times

Positive Hold Times

Clock

Fig 4


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4

Further Developments

For a digital circuit to perform an interesting and useful function, many of the timing events previouslydescribed have to be performed in a sequence. Typically, this sequence is performed at a prescribed frequency.

Consider a simple counter. It has a clock Data inputs, Data outputs, and at least 1 control input to tell it tocount, load new data, or possibly stop counting and hold the data. We will ignore the reset pin for now.

To exercise this device, a pattern can be written to load some data, let the counter count for several clocks, loada new value, and count some more. (See Fig 6)

Along with the pattern info, timing for the pins must be defined. We start by defining the specs or variables thatwe will plug into the timing equations to set the actual times for events to occur.

DIN7:0 Q7:0

LD

CLK

8 8

RST

TC

Fig 5

Fig 6


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5

The key points are as follows:

1) The clock period, which is also the test cycle is a spec. This will be changed as needed. An RZ (Return toZero) format has been chosen for the clock.

2) The Data inputs have a programmable input setup time while the hold time is not. This is due to the NRZformat. A more complex format can be used to characterize the hold times but are not used in a simplefunctional test.

3) The LD control input has its own setup time spec. There are occasions where this pin would be includedwith the other data input pins. This pin is active high so an RZ format is also a possibility to test the hold

time.

Fig 7

Fig 8


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6

4) The outputs are strobe by a specified time after the rising edge of the clock. The equation is written such

that a change in the rising edge of the clock causes does not change the relationship between the clock andthe output strobe time. An edge strobe has been chosen rather than a window strobe. Either method can

certainly work in this application.

5) There is only 1 edge set. It can handle all the behaviors of the device.

For this simple device, the operating range of the test can now be evaluated. The voltage range that it worksover and the frequency range that it works over are the first thing to be evaluated. This of course assumes thatthe tester is capable of exceeding the operating ranges of the device.

Shmoo 1

Often things don't go quite this simply. Parts can behave as the above shmoo plot shows only if the prop delaysare always shorter than the minimum clock period. Shmoo 2 is what you can expect to see on devices where

low power is optimized rather than speed.


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Shmoo 2

The region in the upper left of Shmoo 2 is where the strobe runs into the output hold time of the device. Theoutput strobe time is pushed out in time far enough for the long prop delays associated with low voltage

operation. (See Fig 9) As the frequency goes up the window that the output may be strobed shrinks.


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The solution to the problem is to strobe earlier for the high voltage test and strobe later for the low voltage test.

The values for the strobe times should be chosen to maximize the strobe timing margins. To do this it's requiredto have a "fastest" unit to determine the minimum output hold time and a "slowest" unit to determine the

maximum prop delay. Then, given the required period, the optimum timing can be chosen.

This phenomenon can be looked at another way. A shmoo plot of the prop delay vs period illuminates the

concept. (See Shmoo 3)

HighVoltage

Operation

Low

Voltage

Operation

Strobe late to get the wide voltage

operation

Strobe Window

Strobe window shrinks with period.

Fails Output Hold at this frequency

Fig 9


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Shmoo 3

Of course, shmoo plot 3 is for only one unit at a given voltage but characterization routines that extract this data

can be used to choose the optimum timing values.

A more complex device

Consider a more complex counter with an asynchronous reset pin and another output called TC or Terminal

count. When the reset pin asserts by going low, all the outputs go to their reset condition. Let's define that tobe all highs. After the reset pin negates (i.e. goes high), the counter may begin normal operation.

This leads to two important new behaviors.

1) There are now 2 different prop delay paths for the outputs. The clock rising to output delay and the reset

asserting to output delay. Different edge sets are a natural way to address this.

2) The reset pin acts like a clock when it asserts but it acts like a data pin when it negates. The pin must negate

a specified time before the clock can resume normal operation. Again, a second edge set will work here.


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10

There is another issue to address. If the actual prop delay from reset asserted to output valid is significantlydifferent from the clock to output, then it makes sense to use another spec in the QOUT c1 equation for the rst

edgeset. It would be something like:

QOUT c1 = RST.d1 + QVR, where QVR is the new spec

We will ignore that complication.

Fig 10

Fig 11


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Another trick is to move the assertion of the RST pin so that the outputs become valid at the normal time. For

example, if the typical clock->Q is 10ns and RST->Q is 15ns, then do the following in the rst edgeset:

RST.d1 = CLK.d1 - 5ns

QOUT .c1 = RST.d1 + QV + 5ns ; RST tpd ~= CLK tpd + 5ns

Let's say the TC pin also has a special design "feature". When it asserts, it goes low on the falling edge of theclock and then goes high on the rising edge of the clock 1.5 cycles later. This behavior is also handled withedge sets.

There are a few subtle issues to address here. It is important to have a clear view of the events that occur within

a test cycle. Inputs are relatively easy - you set them and they do what you tell them (and hopefully what you

meant). For outputs, we return to the first fundamental principle that outputs switch due to some input event.The corollary of this principle is to strobe outputs after the output event i.e. strobe the new state.

15ns

CLK

QOUT

RST

Fig 12


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Do not be tempted to strobe TC early in cycle N just because it is stable for most of the cycle. Remember the

first fundamental principle. If you don't have the correct timing equation, you will not be able to tell measurethe prop delay. If you try to do it, then it will be a function of the period.

Another subtle point concerns what happens during cycle N+1. The output does not switch. If we strobe late

we decrease the timing margin to the output hold time. So, the correct choice is to strobe early in cycle N+1

and N+2. Then, the full timing margin will be maintained. Shmoo 4 shows the problem of strobing cycle N+1late. The output hold timing margin is compromized. A half of a period of margin is lost. The shmoo cells

with the "C" in them are the ones that fail due to strobing late in cycle N+1.

Shmoo 4

CLK

TC

Cycle N Cycle N+1 Cycle N+2

Fig 12


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Next we look at this behavior when TC asserts the fastest rate possible.

We now have 2 output events in cycle N+2. There are a couple of possible solutions. The low speed solution isto split the cycle into 2 test cycles with half the period. Then the CLK is an NRZ signal and both states of TC

can be strobed. The solution I now recommend is to strobe for the final state of the cycle. So, cycle N and N+2will be tc cycles and cycle N+1 and N+3 will be std cycles. All 4 cycles will strobe for a Low and it's the

edgeset changes that tell you what is happening. Fig 14 shows the patedit view of this.

Cycle N Cycle N+1 Cycle N+2 Cycle N+3 Cycle N+4

CLKTC

Fig 13

Fig 14


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Real Results

On wireless baseband processors, these techniques have been applied. These devices have outputs switching on

both edges of the clock. There are outputs with 2 different prop delays depending on whether they are in afunctional mode or are programmed as GPIO pins. The frequencies are not high but the prop delays push the

strobe times out into the 2 next cycles. Shmoo 5 is a 3D shmoo plot of period, vdd, and strobe times.

It is a way to get a view of the full operating range of the device. In it we can see the late strobe times requiredfor the low voltage operation. Also, we can see the output hold time requirements for the high voltage

operation.

Shmoo 5


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A Tutorial on Timing Equations 15

Conclusions

Complex digital ICs are a challenge to test. By applying a small set of principles to the test timing and test

pattern generation methodologies, a test engineer can produce robust functional tests. These techniques enablethe test engineer to determine and understand the timing margins of the device. With this knowledge, he is the

expert and can quickly determine and explain problems as they come up over time.

Documents

A Tutorial on Timing Equations by S Schwartz (TUG 2000 Paper)