A Test Generation Framework for Quantum Cellular Automata Circuits

24 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 15, NO. 1, JANUARY 2007

A Test Generation Framework for QuantumCellular Automata Circuits

Pallav Gupta, Student Member, IEEE, Niraj K. Jha, Fellow, IEEE, and Loganathan Lingappan, Member, IEEE

Abstract—In this paper, we present a test generation frameworkfor quantum cellular automata (QCA) circuits. QCA is a nanotech-nology that has attracted recent significant attention and showspromise as a viable future technology. This work is motivated bythe fact that the stuck-at fault test set of a circuit is not guaran-teed to detect all defects that can occur in its QCA implementation.We show how to generate additional test vectors to supplement thestuck-at fault test set to guarantee that all simulated defects in theQCA gates get detected. Since nanotechnologies will be dominatedby interconnects, we also target bridging faults on QCA intercon-nects. The efficacy of our framework is established through its ap-plication to QCA implementations of MCNC and ISCAS’85 bench-marks that use majority gates as primitives.

Index Terms—Computer-aided design (CAD) for nanotechnolo-gies, quantum cellular automata (QCA), test generation.

I. INTRODUCTION

FOR TWO decades, bulk CMOS technology has con-sistently provided the required dimension scaling for

implementing high-density, high-speed, and low-power VLSIsystems. However, such an aggressive scaling is accompaniedby many problems. These problems are, to name a few, highleakage current, high power density levels, and very highlithography costs. It is predicted that these issues will result inthe conclusion of the CMOS revolution within the next 10–15years [1]. The short time remaining exerts the need for activeresearch in novel nanoscale technologies to help determineviable alternatives.

One possible replacement technology candidate that has beenproposed is quantum cellular automata (QCA) [2]–[5] in whichlogic states, rather than being encoded as voltage levels, as inconventional CMOS technology, are represented by the config-uration of an electron pair confined within a quantum-dot cell.QCA promises small feature size and ultra-low power consump-tion. It is believed that a QCA cell of a few nanometers canbe fabricated through molecular implementation by a self-as-sembly process [6]. If this does hold true, then it is anticipatedthat QCA can achieve densities of devices/cm and operateat terahertz frequencies [7].

Since its initial proposal, QCA has attracted significant atten-tion. Consequently, various researchers have addressed different

Manuscript received December 29, 2005; revised May 27, 2006. This workwas supported by the National Science Foundation under Grant CCF-0429745.

P. Gupta and N. K. Jha are with the Department of Electrical Engineering,Princeton University, Princeton, NJ 08544 USA (e-mail: [email protected]; [email protected]).

L. Lingappan is with NVIDIA Corporation, Santa Clara, CA 95050 USA.Digital Object Identifier 10.1109/TVLSI.2007.891081

computer-aided design problems for QCA. In [8], the authorshave discussed a majority logic synthesis tool for QCA calledMALS. Majority logic synthesis has also been addressed in [9].In the SQUARES formalism [10], a series of basic QCA com-ponents are described that can be connected arbitrarily. This al-lows a designer to lay out a QCA circuit systematically withstandardized components. Models to minimize layout area anddead space are presented in [11]. They address the main short-comings of the SQUARES formalism. A tool called QCADe-signer for manual layout of QCA circuits has been presented in[12]. This tool also offers various simulation engines, each of-fering a tradeoff between speed and accuracy, to simulate thelayout for functional correctness. The authors of [7] and [13]characterize, in detail, the types of defects that are most likelyto occur in the manufacturing of QCA circuits.

The main question facing the testing community is whetherthe conventional CMOS test flow will have to be radically al-tered in order to accommodate testing of nanotechnologies, suchas QCA. In testing of CMOS circuits, test generation is usuallydone using the single stuck-at fault (SSF) model. In this model,a line in a circuit is assumed to be permanently stuck-at-one(SA1) or stuck-at-zero (SA0). It has been observed that the SSFtest set can detect a large proportion (80%–85%) of all man-ufacturing defects in CMOS even though the SSF model doesnot fully capture the behavior of all such defects [14]. For thosedefects that remain uncovered, additional test generation is per-formed using other fault models. To test for defects on the inter-connect, the bridging fault model is commonly used in which apair of lines is assumed to be shorted. A similar approach is alsoapplicable to testing of QCA circuits, as we will see later.

This work addresses the problem of automatic test patterngeneration (ATPG) for combinational QCA circuits. Eventhough fault modeling has been addressed for QCA circuitsbefore in [7] and [13], we are unaware of any other work thathas addressed the general ATPG problem before. The maincontributions of this paper are as follows.

• This is the first comprehensive test generation method-ology for combinational QCA circuits.

• Based on the QCA defect characterization results from[7] and [13], we show how to supplement an SSF test setwith additional vectors so that we can guarantee that everytestable defect in modeled gates in a QCA circuit can ac-tually be detected.

• Our test generation methodology also targets bridgingfaults on QCA interconnects.

The remainder of this paper is organized as follows. InSection II, we present background material. We explain, witha motivational example, why a test generation methodologyfor QCA is needed in Section III. Section IV describes our

1063-8210/$25.00 © 2007 IEEE

GUPTA et al.: TEST GENERATION FRAMEWORK FOR QCA CIRCUITS 25

Fig. 1. QCA cell. The logic states are encoded in the electron pair configura-tion.

test generation methodology in detail. We discuss implemen-tation details of our methodology and experimental results inSection V and conclude the paper in Section VI.

II. PRELIMINARIES

In this section, we provide some background material thatwill be helpful in understanding the remainder of this paper.

A. QCA Cell

A QCA cell, shown in Fig. 1, contains four quantum dots po-sitioned at the corner of a square, and two electrons that canmove to any quantum dot within the cell through electron tun-neling [2]. Due to Coulombic interactions, only two configura-tions of the electron pair exist that are stable. Assigning a po-larization, , of 1 and 1 to distinguish between these twoconfigurations leads to a binary logic system.

B. QCA Gates

The fundamental logic gate in QCA is the majority gate. Athree-input majority gate , is logic high if two or more of itsinputs are logic high. That is

(1)

From this point onwards, a three-input majority gate will besimply referred to as a majority gate.

Computation in a QCA majority gate is performed by drivingthe device cell to its lowest energy state, as shown in Fig. 2(a).This is achieved when the device cell assumes the polarizationof the majority of the three input cells. The reason why the de-vice cell always assumes a majority polarization is because it isin this polarization state that the Coulombic repulsion betweenelectrons in the inputs cells is minimized [2]. The polarizationof the device cell is then transfered to the output cell.

The schematic diagrams of an inverter and basic intercon-nects are also shown in Fig. 2. There are several other ways forobtaining the inverting function in QCA. However, the invertershown in Fig. 2(b) is preferred as it is very robust. In the QCA bi-nary wire shown in Fig. 2(c), information propagates from left toright. An inverter chain, shown in Fig. 2(d), can be constructedif the QCA cells are rotated by 45 . Furthermore, it is possible toimplement two-input AND and OR gates by permanently fixingthe polarization of one of the input cells of a majority gate to 1(logic 0) and 1 (logic 1), respectively. Finally, a majority gate

Fig. 2. QCA (a) majority gate, (b) inverter, (c) binary wire, and (d) inverterchain.

Fig. 3. Four-phase clocking scheme for QCA. Each phase incurs a 90 phasedelay.

and inverter are functionally complete (i.e., they can implementany arbitrary Boolean function).

C. QCA Clocking

Fig. 3 shows a pipelined clocking scheme that must be em-ployed for a QCA circuit to function properly. In this scheme,the clock is divided into four phases with each phase incurringa 90 phase delay. The phases are called switch, hold, release,and relaxed [6], [15]. The clocking scheme allows an array ofcells to perform a certain computation, have its state frozen bythe raising of the inter-dot potential barriers, and have the result


Fig. 4. Majority network and its QCA implementation utilizing a four-phaseclock.

of the computation serve as the input to the successor array ofcells. During the computation, the successor cell array is keptunpolarized so that it does not influence the computation. Fi-nally, neighboring cell arrays concurrently receive neighboringclock phases.

In the switch phase, the initial state of the QCA cell is unpo-larized and the inter-dot potential barriers are kept low. The bar-riers are then raised and the cells become polarized according tothe state of their neighboring (input) cells. It is in this state wherethe actual computation is performed. In the hold phase, the cellstates are fixed and the potential barriers are held high so that thecells can serve as inputs to the next stage. In the release phase,the potential barriers are lowered and the cells are allowed torelax to the unpolarized state. Finally, in the relaxed state, thepotential barriers remain low and the cells remain unpolarized[16]. Fig. 4 shows a majority network and its QCA implemen-tation utilizing the four-phase clocking scheme of Fig. 3. Thedifferent shades in Fig. 4(b) represent different clock phases.Inputs – are supplied in the first clock phase and outputis available one clock cycle (i.e., four clock phases) later.

D. QCA Defects

The types of defects that are likely to occur in the manufac-turing of QCA devices have been investigated in [7], [13], and[17] and are illustrated in Fig. 5. They can be categorized as fol-lows.

1) In a cell displacement defect, the defective cell is displacedfrom its original position. For example, in Fig. 5(b), thecell with input is displaced to the north by fromits original position.

2) In a cell misalignment defect, the direction of the defectivecell is not properly aligned. For example, in Fig. 5(c), thecell with input is misaligned to the east by fromits original position.

3) In a cell omission defect, the defective cell is missing ascompared to the defect-free case. For example, in Fig. 5(d),the cell with input is not present.

For a QCA majority gate, all possible combinations of dis-placement of cells with respect to the center cell under dif-ferent distances and misalignments in different directions weresimulated [13] using QCADesigner [12]. It was reported that

Fig. 5. (a) Defect-free majority gate. (b) Displacement defect. (c) Misalign-ment defect. (d) Cell omission defect.

Fig. 6. (a) Fault-free binary wire. (b)–(d) Binary wire with a bridging fault.

these defects result in different logic values in the fault-free (de-fect-free) and faulty (defective) cases. In addition, it was men-tioned that a particular SSF test set could detect all of the sim-ulated defects [7]. However, a QCA majority gate has nine pos-sible minimal SSF test sets and the question as to which of thesetests sets can detect all of the simulated defects was left unan-swered. We will answer this question in this paper.

For QCA interconnects, cell displacement and omission de-fects on binary wires and inverter chains were also consideredin [17]. These defects could be better modeled using a dominantfault model in which the output of the dominated wire is deter-mined by the logic value on the dominant wire. There are manypossible scenarios that could occur in the presence of a bridgingfault and are illustrated in Fig. 6. In the first scenario shown inFig. 6(b), the second cell is displaced to the north from its orig-inal position by . In this case, the dominated wire will


have a logic value equal to that of the dominant wire . How-ever, if the fourth cell is displaced, as shown in Fig. 6(c), then

will have a logic value equal to the complement of the logicvalue on (i.e., ). Finally, if multiple cells are dis-placed, as shown in Fig. 6(d), then will also equal .

It was also shown that binary wires are more defect-tolerantthan inverter chains. Inverter chains are typically used to imple-ment coplanar wire crossings. In such a wire crossing, a wirerunning along the horizontal or vertical direction is a binarywire, while the second wire is an inverter chain running in theperpendicular direction. However, it has been shown that cir-cuits containing coplanar wire crossings are very likely to fail[18]. A multilayer wire crossover scheme has been proposed toremedy this problem.

E. Test Generation Basics

Fault activation and fault effect propagation are the key ele-ments of test generation. Fault activation is the process of cre-ating a fault effect at the output of the faulty circuit element.Fault effect propagation is the process of assigning values to cir-cuit lines such that the fault effect propagates from the output ofthe faulty circuit element to a primary output of the circuit.

A vector detects a fault in circuit if the response ob-tained at at least one of the outputs of , due to the applicationof at its inputs, is the complement of that obtained at the corre-sponding output of the faulty circuit . If no test vector existsfor a fault, then the fault is untestable. Given a test vector ,the process of fault simulation derives all the faults in circuitdetected by .

The number of faults that need to be targeted in a circuitduring test generation can be significantly reduced using faultequivalence and fault dominance relationships. Two faultsand in a circuit are said to be equivalent if the corre-sponding faulty versions of the circuit, and , respec-tively, have identical input-output logic behavior. Consequently,one of the two faults can be dropped from the fault list. Faultis said to dominate if the set of vectors that detects is a su-perset of the set of vectors that detect . Consequently, canbe dropped from the fault list [14].

F. Satisfiability (SAT)-Based Test Generation

Boolean SAT-based formulations are commonly used for testgeneration [14]. In SAT, a satisfying assignment on the variablesof a Boolean function is sought such thatevaluates to 1. If no such assignment can be found, then issaid to be unsatisfiable. Typically, is represented in conjunc-tive normal form (CNF) which is a conjunction of disjunctiveclauses. A disjunctive clause is a disjunction of one or more lit-erals where a literal is a variable or its complement.

SAT-based test generation [19] is performed by constructingthe CNF of the fault-free and faulty circuits. If a satisfiabilitysolver can find a satisfying assignment on the variables of theCNF formed by concatenating the CNF of the fault-free andfaulty circuits, the values assigned to the inputs of the circuitform a test vector for that particular fault. If an assignmentcannot be found, the fault is proven to be redundant and isuntestable.

III. MOTIVATIONAL EXAMPLE

In this section, we present an example to motivate the needfor our testing methodology for QCA circuits.

Consider the majority circuit shown in Fig. 7(a) whichcontains three majority gates – , seven primary inputs

– , and one primary output . Since there are ten lines inthis circuit, there are 20 SSFs. However, we only need to targetSA0/SA1 faults at the primary inputs in this circuit to guaranteedetection of all 20 SSFs, as we will see in Section IV. Sincethere are seven primary inputs, there are 14 SSFs that need tobe targeted during test generation. Fig. 7(b) shows a minimalSSF test set for the circuit. FSIM [20] was extended to performfault simulation on the majority circuit using the generated testset. For each test vector in Fig. 7(b), all the SSFs detected byit are also shown.

Given the test set in Fig. 7(b), the input vectors that the in-dividual majority gates of the circuit receive in the fault-freecase are shown in Fig. 7(c). For example, it can be seen that

receives input vectors 001, 011, 100, and 101. Now, con-sider fault SA0 which is detected by three test vectors, namely1100110, 0110110, and 0001011. Given the application of vec-tors 1100110 and 0110110, will receive input vector 110 inthe fault-free case. If vector 0001011 is applied, will receiveinput vector 011. In all these cases, the expected fault-free log-ical value at output is logic 1. However, in the presence ofSA0, output becomes logic 0, thus detecting the fault.

It can be seen from Fig. 7(c) that receives input vectors000, 001, 011, 100, and 110. Even though these vectors form acomplete SSF test set for a majority gate, they are not a com-plete test set for detecting all simulated defects that were pre-sented in [7], [13], and [17]. The QCADesigner [12] was usedto perform defect simulation and confirm this assertion. In fact,five defects (three misalignments and two displacements on theQCA cells in ) cannot be detected by these input vectors. Ifwe add vector 0100110 to our original test set, then will alsoreceive input vector 010. Note that the effect of the last four ofthe previous five vectors is also propagated from the output of

to output . This is now a complete test set for all simulateddefects in . Gates and already receive input vectorswhich form a complete defect test set and, hence, require noadditional test vectors (the effect of these vectors is also propa-gated to output ).

Fig. 7(d) shows a possible QCA layout for the circuit inFig. 7(a) (different shades in QCA cells indicate different clockphases). Consider the QCA cell displaced from the binarywire of input so that there exists a bridging fault betweeninputs and . In this case, dominates . Furthermore, itis unknown whether the bridging fault will result in or

. To be able to detect this defect, we need vectors totest for two of four possible conditions. Condition SA0 with

or SA1 with must be tested and conditionSA1 with or SA0 with must be tested. We willexplain how we obtained these conditions in Section IV. Thefirst and second conditions can be tested by vectors 0001011and 0010011 that are already present in our test set. However,we currently have no vector that can test either of the latter twoconditions. Therefore, additional test generation is required and


Fig. 7. (a) Example majority circuit. (b) Minimal SSF test set. (c) Input vectors received by each majority gate. (d) QCA layout of the circuit with a bridging faultbetween inputs C and D.

vectors 0000011 and 0011011 are derived as tests for the thirdand fourth conditions, respectively. Adding either of these twovectors is sufficient as we only need to satisfy either the third orfourth condition for fault detection. The bridging fault between

and , when is dominant and is dominated, can nowbe completely tested for all simulated defects.

The previous example illustrates that the SSF test set of acircuit cannot guarantee the detection of all simulated defectsin the QCA majority gates. Therefore, test generation will berequired to cover the defects not covered by the SSF test set. Inaddition, test generation will also be needed to cover bridgingfaults on QCA interconnects.

IV. ATPG FOR QCA CIRCUITS

In this section, we present our methodology for ATPG forcombinational QCA circuits.

A. Fault Collapsing for Majority Gates

In traditional Boolean testing, fault collapsing is performedon the circuit to reduce the number of faults that need to betargeted during test generation. As mentioned earlier, faultequivalence and dominance relationships between the inputsand output of a gate are used to reduce the fault list. As an

example, consider the majority circuit shown in Fig. 8(a). Sincethere are seven lines in this circuit and since each line can beeither SA0 or SA1, there are 14 SSFs that need to be tested.However, if we look at the equivalent Boolean circuit shownin Fig. 8(b), we can see that there are 50 SSFs that need to betested.

Since the Boolean circuit is irredundant, using traditionalfault collapsing techniques, we only need to target SSFs at theprimary inputs and fanout branches to guarantee detection ofall SSFs in the circuit [14]. Thus, the number of faults to betested is reduced from 50 to 34. Furthermore, it is known thatall input SA0 faults in an AND gate are equivalent [14]. Thus,we can further collapse the fault list and, as shown in Fig. 8(b),there are 28 SSFs that remain in the final fault list. Note thatthis is twice the number of faults in the original majority circuit.

In general, there are no fault equivalence relationships be-tween the inputs and outputs of a majority gate. However, anoutput SA0 (SA1) fault dominates an input SA0 (SA1) fault.Consider the first case. A vector is a test for an input SA0 faultin a majority gate if and only if the fault-free and faulty values atthe output are 1 and 0, respectively. This is because when testingfor an input SA0, the other two inputs must have values 0 and 1,respectively, or vice versa in order to enable the propagation of


Fig. 8. Fault collapsing for majority circuits. Fewer faults need to be targeted in the (a) majority circuit than its (b) Boolean equivalent counterpart.

Fig. 9. Faults that each possible test vector detects in a majority gate.

the fault through the gate. This is evident from the definition of amajority gate given in (1). Thus, any vector that detects an inputSA0 fault will also detect an output SA0 fault. This can also beconfirmed by looking at Fig. 9 which shows the SSFs detectedby each vector ranging from 000 to 111 ( , , and are theinputs and is the output). Similarly, for the case of an inputSA1 fault, the fault-free and faulty values at the output must be 0and 1, respectively. Hence, any vector that detects an input SA1fault will also detect an output SA1 fault. Consequently, there isno need to test for SSF faults on the output.

The previous observation leads to the following theorems fortesting of irredundant majority circuits.

Theorem 1: In a fanout-free combinational majority circuit, any test set that detects all SSFs on the primary inputs

detects all SSFs in .Proof: Since is fanout-free, there exists only one path

from a primary input to a primary output. If we start at a primary

output and traverse backward until we reach a primary input, allthe intermediate lines on the path need not be tested for SSFs asthey are the output of some predecessor gate. It has been estab-lished before that an output fault dominates an input fault. Theonly lines that remain once this process terminates are the pri-mary input lines. Therefore, if detects all SSFs on the primaryinputs, then it detects all SSFs in .

Theorem 2: In an irredundant combinational majority circuit, any test set that detects all SSFs on the primary inputs and

fanout branches detects all SSFs in .Proof: This is a general case of Theorem 1. The proof is

virtually the same except that fanout branches must be testedfor SSFs because they do not necessarily dominate any line.The stem of an internal fanout line dominates an input line oranother fanout branch and does not need to be tested. Therefore,if detects all SSFs on the primary inputs and fanout branches,then it detects all SSFs in .

Returning to the circuit in Fig. 8(a) and given the previoustheorems, we do not need to test for SA0/SA1 faults on lineand output . Consequently, we only need to test for 10 SSFsto guarantee detection of all SSFs in the circuit.

B. High-Level Overview

Fig. 10 gives a high-level overview of our approach. The inputto our methodology is a logic-level circuit description consistingof majority gates and inverters only and the output is a testset which can detect all simulated defects in the gates and in-terconnects in the corresponding circuit. Initially, we performSAT-based test generation for the logic-level circuit by targetingall SSFs on the primary inputs and fanout branches of the circuit.The targeted faults are derived based on the fault collapsing the-orems for majority logic presented in Section III. SAT-based test


Fig. 10. High-level diagram showing our ATPG approach for combinational QCA circuits.

generation requires the CNF of a majority gate which is givenbelow ( , , and are its inputs and its output)

(2)

Next, fault simulation on the logic-level circuit is performedusing the generated test set. The fault simulator keeps track of allthe input vectors that are received by every majority gate in thecircuit. If there exists a majority gate(s) which does not receivea 100% defect test set, additional test generation is performed

by using SAT-based ATPG to justify and propagate the effectsof the extra vectors. Once all the defects have been covered, atest set containing the SSF test set and additional QCA vectorsis obtained. This new test set and a bridging fault list is given tothe fault simulator to determine whether all bridging faults arecovered or not. The fault simulator generates a list of those de-fects that remain uncovered. We supply this QCA bridging faultlist for further test generation to the SAT-based ATPG engine.If the designer has the QCA layout information available, thebridging fault list can be constructed based on adjacent wiresin the layout. If the QCA layout information is not available,


Fig. 11. Minimal SSF test sets for a majority gate. Some of these test sets, however, are not a 100% defect test set for a QCA majority gate.

Fig. 12. Testing of defects in a QCA majority gate.

the designer can supply all possible wire pairs assuming theworst-case scenario. Once all bridging faults have been covered,the final test set is provided as output.

C. Targeting QCA Defects in a Majority Gate

For a majority gate, there are nine minimal SSF test sets, eachcontaining four test vectors. These minimal test sets were ap-plied to a QCA majority gate and all defects described in [7],[13], and [17] were simulated using the QCADesigner [12].Fig. 11 shows our results for this experiment. Of the nine min-imal test sets, three test sets were unable to detect all the simu-lated defects.

Consider the majority gate in Fig. 12 that is embedded ina larger network. Suppose that after SSF test generation for theentire circuit, it is determined that receives input vectors 010,011, 100, and 101. According to Fig. 11, this is not a completedefect test set as three defects remain uncovered. We can makeit complete by ensuring that also receives either 001 or 110as its input vector. Thus, the condition given to the SAT-basedATPG would be

with

or

with

Given the previous conditions, the CNF of the faulty gate wouldbe

(3)

or

(4)

If a test vector can be generated for either fault, then wouldbe completely testable for all simulated defects.

D. Targeting QCA Defects on Interconnects

It is very important to test for defects on QCA interconnectsbecause it is predicted that interconnects will consume thebulk of chip area in future nanotechnologies [21]. As shownin Fig. 6(b)–(d), a displacement of the QCA cells on a wirewill result in a bridging fault between the two wires. Usingthe QCADesigner [12], it was verified that such defects can bemodeled using the dominant bridging fault model [7]. However,depending upon the displacement distance, the lower wire willassume either the upper wire’s logic value or its complement.

Fig. 13 shows the possible scenarios that can result if abridging fault is present between two wires. The scenario thatwill occur depends upon the displacement distance of thedefective cell and/or the number of cells that get displaced.It also shows the conditions that must be satisfied in order todetect the particular scenario. In the first scenario in Fig. 13(a),the lower wire’s logic value is equal to that of the upper wirewhile in Fig. 13(b), the lower wire’s logic value is equal tothe complement of that of the upper wire. If the first scenariooccurs, then a vector is required to test for one of the twoconditions shown in Fig. 13(a). Similarly, if the second sce-nario occurs, a vector is required to test for either of the twoconditions shown in Fig. 13(b). In reality, it will not be knownwhich scenario occurred in the presence of the defect because

will not be known beforehand. Consequently, we need tohave vectors that test for both scenarios to be able to have a testthat can completely detect this bridging fault.

As an example, consider once again the majority gate inFig. 12. Assume there is a bridging fault between inputs and

and it is not known whether the defective cell is on wire orwire . In addition, is unknown. In order to test for this fault,four conditions need to be satisfied (the first two result fromdominating , while the last two result from dominating ).The conditions are as follows:

with or with

with or with

with or with

with or with

The CNFs for the previous conditions are

or

or

or

or


Fig. 13. Modeling of bridging faults in a QCA binary wire.

where and are the CNFs of the gates with out-puts and , respectively. If the test set contains vectors thatcan satisfy the previous conditions, then this bridging fault canbe detected. Otherwise, the fault is not completely tested.

Given a QCA circuit with lines, there are at mostpossible bridging faults involving two wires. This is based onthe assumption that layout information is not available. Conse-quently, conditions will need to be satisfied in orderto obtain a test set for all bridging faults. However, it should benoted that at least (i.e., 50%) of these conditions willalready be satisfied, given any complete SSF test set. This is be-cause, given a pair of wires, when testing for a SA0/SA1 faulton one wire the other line must have a value of 0 or 1. In thispaper, we assume that the QCA layout of the circuit is availableand the designer knows a priori which pairs of wires to test forbridging faults.

E. Multiple Faults Under a Single Defect

It is possible that a single cell defect (whether it be misalign-ment, misplacement, or omission) may affect multiple majoritygates or wires at the same time. This will result in multiplestuck-at fault (SAFs) in a majority circuit. Since there aremultiple SAFs in a circuit with lines, it is impractical to targetall multiple SAFs for any reasonably large value of . In theBoolean CMOS world, it has been shown that the test set de-rived using the SSF model can detect a high percentage of mul-tiple SAFs [22], [23]. In Section V, we will show that the SSFtest set detects a very large fraction of multiple SAFs in ma-jority circuits as well. Thus, even though the behavior of thesingle QCA cell defect can be more complicated than a singleSAF, the test set derived using the SSF model is highly likely todetect multiple SAFs as well.

F. Using Other ATPG Paradigms

The main motivation behind using SAT-based ATPG is that ithas been shown to be the most efficient test generation schemewith respect to CPU time and test set size [24]. Though SAT-based ATPG is a nonstructural testing paradigm, we describe thepossibility of using structural test generation paradigms, suchas the -algorithm [25] and the path oriented decision making(PODEM) algorithm [26], to perform test generation for QCAcircuits. In reality, any test generation paradigm can be used.

TABLE ISINGULAR COVER OF A MAJORITY GATE

The main steps that comprise the -algorithm are fault exci-tation, fault propagation, and line justification. During fault ex-citation, local value assignments must be considered at the faultsite to excite the fault to the gate output. However, in the caseof generating a test vector to detect a defect in a majority gate,it is already known what values must be assigned to the ma-jority gate. Consequently, this then dictates the fault that needsto be tested for. For example, in Fig. 12, when we apply ,

, and , this implies a fault-free/faulty value of 0/1at . Thus, we test for an SA1 fault at . If the -algorithm isused, it should be understood that the constraints constitute thelocal value assignment needed for fault excitation. Thus, thereis no need to consider alternative local value assignments. Allwe need to perform is fault propagation and line justification.

Propagation -cubes are used in the -algorithm to sensitizea path from the fault site to one (or more) primary output(s). Wecan resort to algebraic substitution to determine the propaga-tion -cubes of a majority gate by using the -notation [14].For example, to obtain the propagation -cubes of SA1 in

, substituting for in we get. For the fault to propagate, it is required

that only the cubes containing (or ) get “activated” in .Thus, the propagation D-cubes for SA1 are and . Ofcourse, and are also propagation -cubes. The prop-agation -cubes for and are and

, respectively. These can be stored in atable and used for fault propagation.

Line justification is required once fault propagation has beenachieved. Singular covers of a gate are used in this processwhich are basically compacted truth tables, as shown in Table I.This can also be stored in a table to be used by the -algorithm.Thus, it is possible to employ the -algorithm to perform testgeneration targeting defects in QCA majority gates as well.


Fig. 14. Mapping of faults (f � f ) between a majority circuit and its Boolean gate-level equivalent circuit.

In PODEM, the first step is again local value assignment andthen backtracing these local value assignments to the inputs.As mentioned earlier in the case of the -algorithm, PODEMalso knows the local value assignment to make at the fault sitea priori and only needs to justify this assignment using back-tracing. If it is unable to justify, then there is no need to proceedfurther because it is clear that a test vector will not be found withthe given constraints (i.e., the local value assignment). If justifi-cation is successful, PODEM can then proceed as usual and tryout different values at the inputs and perform forward implica-tion until the fault gets propagated to a primary output. Thus,PODEM can also be used to perform test generation targetingdefects in QCA majority circuits.

G. Performing Gate-Level ATPG

If one desires to perform gate-level ATPG, it is possible toconvert a majority circuit into an equivalent Boolean gate-levelcircuit and employ structural ATPG algorithms discussed inSection IV. If the designer does not want to use the SAT-basedATPG, he/she can use the fault collapsing theorems for ma-jority circuits to generate the fault list first. Then, the majoritycircuit can be converted to a Boolean gate-level equivalent byreplacing each majority gate with a subcircuit that implementsthe function . The gate-levelcircuit and the fault list can then be used to perform ATPG. Caremust be taken to ensure that the faults are mapped properlybetween the two circuits.

As an example, Fig. 14 shows the gate-level equivalent cir-cuit for the example that was discussed in Section III. It alsoshows the mapping of some faults between the majority circuitand its Boolean counterpart. For example, if one wants to testfor fault located at line in the majority circuit, then thecorresponding fault in the Boolean circuit is the stem (and notbranch) of line . The same holds true for faults and .

V. EXPERIMENTAL RESULTS

In this section, we present our experimental results on bench-marks from the MCNC [27] and the ISCAS’85 [28] benchmark

suites. All the benchmarks were first synthesized into multi-level majority networks using the logic synthesis tool MALS[8]. All experiments were conducted on a Dell PowerEdge 600SC server featuring a Pentium IV 1.6-GHz processor, 512-KBcache, 1-GB RAM, and running Fedora Core 4.

A. Implementation Details

The Boolean fault simulator FSIM [20] was extended to aQCA defect simulator. In addition to maintaining an SSF list, italso keeps track of the vectors that are received by each majoritygate during fault simulation. The vectors that are kept track ofare those vectors whose fault effects get propagated to a primaryoutput. For example, if a majority gate received vectors 001,010, 011, 101, and 110, and the effect of 011 was not propagatedto the output, we would record vectors 001, 010, 101, and 110only. The set of five vectors is not a complete defect test setbecause even though it contains vectors that could potentiallyform a complete defect test set, the fault effect of vector 011 isnot propagated to the output.

A 2-D matrix data structure is utilized where the rows repre-sent the majority gates in the circuit and the columns representthree-bit vectors. The size of this matrix is where is thenumber of majority gates. Once a given test has been simulated,the matrix is analyzed to see which gates receive a 100% defecttest set. Such gates are marked and discarded. For those gatesthat do not receive a 100% defect test, a defect-based fault list isgenerated which specifies the conditions that need to be tested.These conditions were explained in Section IV.

FSIM was also extended to a QCA bridging fault simulator.The user supplies a bridging fault list which contains a list ofpairs of wires. During fault simulation, for each pair of wires,we keep track of the conditions specified in Fig. 13 that aresatisfied. Again, a matrix data structure is utilized and we onlymark those conditions as being satisfied in which the fault effectis propagated to the output. At the end of fault simulation, apass through the matrix is made, and for those pairs of wiresfor which the conditions are not completely satisfied, a bridging


TABLE IIQCA DEFECT TEST GENERATION ON MCNC BENCHMARKS

fault list is generated specifying the additional constraints thatneed to be applied during test generation.

The modifications made to FSIM amount to about 1000 linesof C code.

B. Results

Tables II and III show the number of primary inputs (PI) andoutputs (PO), circuit gate count, size of the SSF test set, numberof additional vectors needed to cover all defects in majoritygates, and CPU time. The CPU time indicates the time for testgeneration of additional QCA vectors only. Note that the addi-tional vectors cover all defects in majority gates only. They donot include vectors that may be needed to cover bridging faultsbetween interconnects. It should also be noted that reverse-orderfault simulation was performed on the test set to reduce its size.The SSF test set was generated using the SAT-based ATPG en-gine in SIS [29]. In most of the smaller benchmarks, it can beseen that no additional vectors are required. This is probably be-cause of the presence of fewer reconvergent fanouts, making iteasier to satisfy the additional conditions. However, for

TABLE IIIQCA DEFECT TEST GENERATION ON ISCAS’85 BENCHMARKS

larger benchmarks the opposite seems to be true, as they requireadditional vectors. For example, for the apex6 benchmark, 108additional vectors were generated.

Rather than giving a table of results for test generation forQCA bridging faults, we present results for an example whichwas manually laid out. The reason why we do not give resultsfor all the previous benchmarks is that in this work we have as-sumed that the layout is available a priori. Since circuits haveto be manually laid out in the QCADesigner, currently, it is verydifficult to lay out a large circuit (any circuit in excess of 25gates) and validate it for functional correctness. On the otherhand, if we do not make this assumption, then one has to target

bridging faults. Clearly, this is not feasible. As a compro-mise, we have presented a methodology of how to test bridgingfaults and present one layout-based example. It should be keptin mind that generating a test for a bridging fault is no harderthan generating a test to detect a defect in a majority gate. Inboth cases, constraint-based test generation is needed. As men-tioned earlier, any SSF test set already guarantees the detectionof 50% of all the bridging faults in QCA circuits.

The QCA layout for the cm82a benchmark is shown inFig. 15. The layout uses two layers in which the crossover wiresrun on different layers. The wire crossover scheme is describedin [18]. The layout was obtained using the QCADesigner [12]and the circuit was simulated for functional correctness. Thecircuit has five inputs, three outputs, five inverters, and 16majority gates. Note that two-input AND and OR gates are im-plemented by fixing one of the inputs of a majority gate to logic0 and logic 1, respectively. Based on the layout information,Fig. 15 also shows the wire pairs that need to be targeted forbridging fault detection. Given the bridging fault list and theSSF test set for this benchmark from Table II, we fault simu-lated this circuit and determined that additional test generationwas necessary to cover all bridging faults. The conditions thatneeded to be satisfied were

with or with

with or with

with or with

with or with

with or with

It turns out that all of the previous conditions are unsatisfiable.This can be explained by looking at Fig. 15. It can be seen that


Fig. 15. QCA layout of the cm82a benchmark and wire pairs that need to betested for possible bridging faults.

wire 2 carries complement values to wire 1, wire 4 carries com-plement values to wire 3, and so on. Thus, testing for an SA1(SA0) fault on a line with the condition that the other lines havea value of 0 (1) is not possible. Hence, for this particular ex-ample, the SSF test set detects all the detectable bridging faults.However, if the layout was changed then clearly there could bea need for additional test generation. In addition, for larger cir-cuits, one can expect the need for additional test vectors to coverdefects on QCA interconnects.

To determine if the test vectors generated based on the singleQCA defect model have the capability to detect multiple SAFs,we introduced double, triple, and quadruple SAFs in somesample majority benchmarks. In the case of double SAFs, allpossible pairs were fault simulated using the test set generatedin Table II. In the case of triple and quadruple SAFs, 1 000 000random groups were fault simulated. The results are shownin Table IV. As can be seen, only for the cm82a benchmarkwas the test set unable to detect all double SAFs. Furthermore,the test set was able to detect all triple and quadruple faultsthat were supplied for simulation. However, it should be keptin mind that this number is a small percentage of all possibletriple and quadruple faults. Clearly, it is impractical to try tofault simulate all such groups for a reasonably sized circuit. As

TABLE IVFAULT SIMULATION OF MULTIPLE SAFS

All pairs of faults simulated.

1 000 000 groups of faults simulated.

in the case of CMOS, the only conclusion that can be drawnis that the test set derived from the SSF model is likely todetect a large percentage (but not all) of multiple SAFs in QCAmajority circuits. Thus, performing test generation using thesingle QCA defect model is appropriate.

VI. CONCLUSION

In this paper, we presented the first comprehensive testingmethodology for combinational QCA circuits. First, we devel-oped some fault collapsing theorems for majority circuits. Weshowed that if traditional fault collapsing is used, there wouldbe a significantly larger number of SSFs that would need tobe tested. Thus, using traditional fault collapsing would be avast overkill. Based on the fault list derived from our fault col-lapsing theorems, we generated an SSF test set using a SAT-based solver. We showed that although an SSF test detects everySSF in the circuit, it is not guaranteed to detect all the simu-lated QCA defects in the majority gates. Consequently, furthertest generation is required and we showed how to generate ad-ditional test vectors that would guarantee that all defects in themajority gates are covered.

Interconnects are likely to consume the bulk of chip area innanotechnologies such as QCA. Therefore, we also analyzedbridging faults in QCA circuits. Based upon fault modeling re-sults presented by other authors, we showed the necessary con-ditions that must be satisfied to detect a bridging fault between apair of QCA wires. For a pair of wires, only two of the four con-ditions (one from each scenario) need to be satisfied. In order toimplement the previous methodology, a Boolean SSF simulatorwas modified to handle QCA defect and interconnect simula-tion.

ACKNOWLEDGMENT

The authors would like to thank Prof. K. Walus from theUniversity of British Columbia for his help in answering theirqueries about the usage of the QCADesigner.


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Pallav Gupta (S’99) received the B.S. degree in computer engineering withhonors (summa cum laude) from The University of Arizona, Tucson, in 2002.He is currently pursuing the Ph.D. degree at Princeton University, Princeton,NJ.

His research interests include computer-aided design for emerging nanotech-nologies such as quantum cellular automata, resonant tunneling diodes, carbonnanotubes, reversible logic, and computing paradigms for emerging technolo-gies.

Mr. Gupta was a recipient of the Wallace Memorial Fellowship fromPrinceton University for the 2005–2006 academic year.

Niraj K. Jha (S’85–M’85–SM’93–F’98) receivedthe B.Tech. degree in electronics and electricalcommunication engineering from the Indian Instituteof Technology, Kharagpur, India, in 1981, the M.S.degree in electrical engineering from the State Uni-versity of New York (SUNY) at Stony Brook, NY, in1982, and the Ph.D. degree in electrical engineeringfrom University of Illinois at Urbana-Champaign, in1985.

He is a Professor of Electrical Engineeringat Princeton University, Princeton, NJ. He has

coauthored Testing and Reliable Design of CMOS Circuits (Kluwer, 1990),High-Level Power Analysis and Optimization (Kluwer, 1998), and Testing ofDigital Systems (Cambridge Univ. Press, 2003). He has also authored six bookchapters. He has authored or coauthored more than 300 technical papers. Heis currently serving as an Associate Editor of the IEEE TRANSACTIONS ON

CIRCUITS AND SYSTEMS—II: REGULAR PAPERS, the IEEE TRANSACTIONS

ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, theIEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS,and the Journal of Low Power Electronics. He has served as an Editor ofthe Journal of Electronic Testing: Theory and Applications (JETTA) in thepast. He has served as the Guest Editor for the JETTA special issue onhigh-level test synthesis. He served as the Director of the Center for EmbeddedSystem-on-a-chip (SoC) Design funded by the New Jersey Commission onScience and Technology. He has received 11 U.S. patents. His research interestsinclude nanotechnology, thermal analysis and optimization, computer-aideddesign of integrated circuits and systems, digital system testing, and computersecurity.

Dr. Jha is a Fellow of the ACM. He is the recipient of the AT&T FoundationAward and NEC Preceptorship Award for research excellence, NCR Awardfor teaching excellence, and Princeton University Graduate Mentoring Award.He has co-authored seven papers which have won the Best Paper Award atICCD’93, FTCS’97, ICVLSID’98, DAC’99, PDCS’02, ICVLSID’03, andCODES’06. A paper of his was selected for “The Best of ICCAD: A collectionof the best IEEE International Conference on Computer-Aided Design papersof the past 20 years,” and another by IEEE Micro as being among the best of2005 Computer Architecture conference papers. He has served as the ProgramChairman of the 1992 Workshop on Fault-Tolerant Parallel and DistributedSystems and the 2004 International Conference on Embedded and UbiquitousComputing.

Loganathan Lingappan (M’06) received the B.Tech. degree in electrical en-gineering from the Indian Institute of Technology, Madras, India, in 2001 andthe M.A. and Ph.D. degrees in electrical engineering from Princeton University,Princeton, NJ, in 2003 and 2006, respectively.

He is currently with NVIDIA Corporation, Santa Clara, CA.

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A Test Generation Framework for Quantum Cellular Automata Circuits