A Test Circuit Based on a Ring Oscillator

Array for Statistical Characterization of

Plasma-Induced Damage

Won Ho Choi1, Saroj Satapathy1, John Keane2,

and Chris H. Kim1

1 University of Minnesota, Minneapolis, MN

2 Intel Corporation, Hillsboro, OR

choi0444@umn.edu

2/21

Agenda

• Plasma-Induced Damage (PID)

• Proposed PID characterization circuit

Based on a Ring Oscillator Array

• Antenna Design

• Statistical Experiment Results

• Conclusions

3/21

Plasma-Induced Damage (PID)

• Plasma charge generated during the fabrication process

leads to damage in the gate dielectric manifesting as

latent device lifetime issue.

• The contiguous metal structure referred to as “antenna”

Receiver Driver

Gate dielectric Junction

M1

M2

M3

M4

Plasma charge

Charge build up during back-end process

Long metal interconnect (Antenna)

Z. Wang, et al., ICICDT 2005

4/21

(a) PID in Inverter Chain

PID

Driver Receiver

M1

M2

M3

Long metal wire

Receiver

Receiver

Reverse

biased

P-diode

Reverse

biased

N-diode

(b) PID Solution:

Jumper Insertion

(c) PID Solution:

Protection Diode

(1) Increased Vth shift

>> Delay↑

(2) Aggravated TDDB

>> Lifetime↓

Inserting vias

>> R↑, Delay↑

>> EDA tool support

>> Time to market ↑

Inserting diodes

>> C↑, Delay↑

>> Leakage current↑

>> EDA tool support

>> Time to market ↑

Long

metal wireLong

metal wire

M4

Jumper

Circuit Impact and Mitigation Techniques

P. H. Chen, IEEE Circuits & Devices Magazine 2004

• Mitigation techniques incur speed, power, cost, and

time-to-market overhead

• PID impact on circuits need to be accurately assessed

5/21

Pros

Cons

Impact of

latent PID

BTI Test

High sensitivity

Short test time

Difficult to collect high quality data

(fast BTI, unwanted recovery)

Increased ∆Vth

Mechanism

n+ p+ n+ p+Si

H

+Si

H

Si

H

VDD

NBTI Stress

+

n+ p+ n+ p+Si

H

Si

H

Si

H

VDD

NBTI Recovery

+

VDD

VDD

Characterizing Latent PID:

BTI (Bias Temperature Instability) Test

6/21

Increased Vth Shift by “Latent” PID

0

1

2

3

4

5

6

7

0 10E+3 15E+3

No

rma

lize

d Δ

Vth

(a

.u.)

Stress Time (a.u.)5E+3

PID

-In

du

ce

d Δ

Vth

Increased

ΔVth

w/ PIDw/o PID

• Initial Vth shift occurs on the device by “latent” PID

• After the device is being used, the Vth shift increases

7/21

Comparison with Prior Art

2D Array 2D ArraySingle device

Parameter of

interestTDDB

Increased ΔVth

TDDBIncreased Δf

Schematic

Measurement

resolutionLimitedHigh High

Sampling

Time

Short

(Parallel stress)

Long

(Serial stress)

Short

(Parallel stress)

Circuit based systemDevice probing

Measurement

time

Depends on tester speed

(several milliseconds)N/A

Short time interruption

(>1μs*)

An

ten

na

BLIGCurrent-to-digital converter

Counting number

* For a 0.01% frequency shift Resolution and a ROSC period of 10ns, enable to minimize the unwanted BTI recovery

Beat frequency system

Counting number

SmallLarge SmallSilicon area

1D Array

Initial ΔVth

High

-

(No stress purpose)

Depends on I/O BW

(several milliseconds)

Small

An

ten

na

S

G

D

An

ten

na

ID

Note: one stress cell is shown

D

G

S

An

ten

na

G

An

ten

na

`

An

ten

na

An

ten

na

An

ten

na

f BL

[2] [3][1] This work

Cell feature

[1] T.B. Hook, et al., IRPS 2000 [2] P. Simon, et al., TSM 2000 [3] W.H. Choi, et al., IRPS 2013

8/21

Proposed PID Characterization Circuit

• 10x4 stress ROSC cells (two types: PID protected,

damaged) array allows parallel stress/serial

measurement capability

• 3 reference ROSCs trimmed to various points in

stressed ROSC frequency distribution

Ro

w P

eri

ph

.

Column Periph.

Ref. ROSC 1

Three

Beat Frequency (BF)

Detection Systems

SCANOUT

RESULTS

FSM

+

Scan

Chain

Ref. ROSC 2

Ref. ROSC 3

BITLINE

NOTE: Ref. ROSC identical to PID Protected ROSC

NI DAQ Board, LabVIEWTM

interface

4

10

Protected

ROSC

Damaged

ROSC

Protected

ROSC

Damaged

ROSC

Protected

ROSC

Damaged

ROSC

Protected

ROSC

Damaged

ROSC

9/21

PID Protected and Damaged ROSCs

with Antenna Structures

6 bit trimming caps

Antenna Antenna Antenna Antenna Antenna AntennaAntenna

Output Stages

SUPPLY SUPPLY SUPPLY SUPPLY SUPPLY SUPPLY SUPPLY

SH

AR

ED

BIT

LIN

E

I/O device (tox: 5nm)

1 (measurement)

0 (stress)

SUPPLY

VDDVSTRESS

SUPPLY Switch Block

PBTI stress on NMOS

NBTI stress on PMOS

{M/S

M/S

M/SM/S M/S

RECOVER

M/S

P: 800/280nm

N: 400/280nmROSC DUT Dimensions {

• 5V DC stress, nominal 2.5V for the measurement

• The primary degradation mechanism is NBTI

• PID for 7 DUTs, NBTI degradation on PMOSs of 3 DUTs

10/21

Cross-sectional View of a Single Stage

• AR values of 4.4k (Metal) and 0.7k (VIA) were

implemented in a single inverter stage

M1

M2

M3

M4

M5

M6

M7

Plate antennas

PID Protected ROSC

VIASmall Jumper

Plate antennas

PID Damaged ROSC

total surface area of antenna structure

gate areaAR =

11/21

Simulated Frequency Difference

Between Two ROSC Types

• Simulations showing negligible freq. difference between

two ROSC types

292

294

296

298

300

302

0 0.05 0.10 0.15 0.20 0.25 0.30

Fre

qu

en

cy

(M

Hz)

Time (μs)

PID Protected ROSCs (Avg.: 297.58MHz)

PID Damaged ROSCs (Avg.: 297.60MHz)

Post Layout, VDD=2.5V, TT, 26ºC

Avg. Frequency Difference w/ No PID:

0.02MHz (0.0067%)

12/21

Beat Frequency Detection System

(PID Protected or Damaged ROSC)

Phase

Comp.

Beat

Frequency

CounterB

A

A

B

fstr : 0.99GHz

fref : 1.00GHz

Stressed ROSC

Reference ROSC(PID Protected ROSC)

• Phase comparator is used to generate the beat frequency

• 3 benefits: high resolution (>0.01%), insensitive to

common mode noise, fully-digital scan-based interface

T.H. Kim, et al., VLSI Circuits 2007

13/21

Beat Frequency for a High Resolution

(PID Protected or Damaged ROSC)

Phase

Comp.

Beat

Frequency

CounterB

A

A

B

PC_OUT

(fbeat = fref - fstress)

C

C

Count:

N=100

Stressed ROSC

Reference ROSC(PID Protected ROSC)

• Phase comparator output: fbeat=fref-fstress

• Counter counts the number of reference cycles in one

period of the beat signal

14/21

Beat Frequency for a High Resolution

(PID Protected or Damaged ROSC)Stressed ROSC

Reference ROSC(PID Protected ROSC)

Phase

Comp.

Beat

Frequency

CounterB

A

PC_OUT

(fbeat = fref - fstress)

C

Count:

0.99

0.98

fStress

(GHz): fref : 1.00GHz

N=100

N=50

• 1% frequency difference before stress N=100

• 2% frequency difference after stress N=50

• Δf or ΔT sensing resolution is 0.01%

15/21

Measured Fresh Frequency Distributions

• 1.15% degradation in average frequency as a result of

PID

0

5

10

15

20

25

30

35

40

236 238 240 242 244 246 248 250

Oc

cu

rre

nc

es

(%

)

ROSC Frequency (MHz)

μ =241.6

μ=244.4

PID Protected ROSCsPID Damaged ROSCs

Fresh, 26 C,O

1.15% Avg.

frequency (μ)

degradation

Chip #1 ~ #4

16/21

Chip-to-Chip Variation

• Degradation trend in the average fresh frequency is

consistent across different chips

0

0.4

0.8

1.2

1.6

2

2.4

#1 #2 #3 #4 #5 #6 #7 #8 #9

Chip #

PID

-In

du

ce

d Δ

f (%

)

Max: 1.39%

Min: 0.88%

Fresh, 26 CO

17/21

Measured Freq. Degradation

after 15000s, 3.6V DC Stress

Oc

cu

rre

nc

es

(%

)FreshAfter 15000s Stress

3.6V DC Stress, 26 C

ROSC DUT Frequency (MHz)

μ =227.8

FreshAfter 15000s Stress

μ=241.9

PID Protected ROSCs

PID Damaged ROSCs

O

3.2% freq. shift

0

5

10

15

20

25

30

35

40

220 225 230 235 240 245 250

μ =236.9

μ=244.8

0

5

10

15

20

25

30

35

40

220 225 230 235 240 245 250

5.8% freq. shift

18/21

Measured BTI-Induced Frequency Shift

0

1

2

3

4

5

6

7

0 10E+3 15E+3

No

rma

lize

d Δ

f, M

ea

n (

%)

Stress Time (s)

3.6V DC Stress, 26 C, 80 ROSCsO

5E+3

1.1

5%

2.6

%

PID Damaged ROSCsPID Protected ROSCs

• The initial frequency shift of 1.15% between both ROSC

types increases to 2.6% after 15000s, 3.6V DC stress

19/21

PID-Induced BTI Lifetime Projection

from Measured Statistics

101

102

103

104

105

106

107

108

109

1010

3 4 5

PID

-In

du

ce

d B

TI L

ife

tim

e (

s)

Voltage (V)

PID Damaged ROSCsPID Protected ROSCs

Operating Lifetime: 10yrs

VMAX, DAMAGED

DC Stress, 26 C, measured at 2.5VO

VMAX, PROTECTED

• The proposed test circuit would be equally useful in the

prediction of PID-induced BTI lifetimes with different

ARs in any type of device with any topology of antenna

structure under any fabrication process

20/21

65nm Die Photo and Chip Features

Measure

Interrupt

Process65nm LP

CMOS, 7M

Core / IO

Supplies1.2V / 2.5V

2.5V

Δf

Resolution> 0.01%

> 1μs

Stress

Voltage

Measurement

Voltage

P: 800/280nm

N: 400/280nm

ROSC DUT

dimensions

3.6V, 3.8V, 4.0V

496x767 μm2Total

Area

IO devicesDUT Type

VSTRESS DECAP

Ro

w p

eri

ph

.+ V

DD

H D

EC

AP

10x4 ROSC Array

Column periph.

VDDL

DECAPFSM +3 ref. ROSCs

+ 3 BF Systems

PID Protected ROSC

PID Damaged ROSC

• Measured with LabVIEW & NI DAQ board

21/21

Conclusions

• ROSC array-based PID characterization circuit with

antenna structures fabricated in a 65nm process

– To collect high quality massive PID-induced BTI statistics

– It provides a high measurement precision (>0.01%) with a short

measurement interrupt (>1μs)

• Measurement results confirm that circuits undergo

PID-induced frequency degradation even before they

are being used and therefore, the BTI lifetimes are

reduced down the road.