A T-Type Isolated Zero Voltage Switching DC–DC Converter With … em periódicos... · 4210 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 32, NO. 6, JUNE 2017 A T-Type Isolated

4210 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 32, NO. 6, JUNE 2017

A T-Type Isolated Zero Voltage Switching DC–DCConverter With Capacitive OutputDelvanei Gomes Bandeira Jr., Member, IEEE, and Ivo Barbi, Fellow, IEEE

Abstract—A novel isolated dc–dc converter is proposed, usingthe T-Type topology with zero voltage switching and pulse widthmodulated with a capacitive output filter. It uses four switches, twoof which are subjected to the input voltage, and the other two tohalf the input voltage. All switches commutate under zero voltageover a wide load range. The proposed converter has the followingfeatures: (a) symmetrical operation of the isolation transformer,(b) modulation by pulse width with constant frequency, (c) zerovoltage switching, and (d) three-level voltage applied to the primarywinding of the transformer. Theoretical analysis, design example,and experimental data for a 2 kW, 400 VDC input, 400 VDC output,and 50 kHz switching frequency laboratory prototype, working intwo operating points are included in this paper. The measuredefficiency was 95% at 950 W.

Index Terms—DC–DC converter, power supplies, T-type, zerovoltage switching.

NOMENCLATURE

D Duty cycle.fs Switching frequency.iLr Resonant inductor current.Io Load current.Io Normalized load current.Io min Normalized minimal load current for ZVS switching.n Transformer turns ratio.Np Number of turns in the transformer primary coil.Ns Number of turns in the transformer secondary coil.Ld Transformer leakage inductance.q Static gain.Ts Switching period.td Dead time.Vo Converter output voltage.V ′

o Converter output voltage reflected to the transformerprimary winding.

V1 Converter input voltage.

Manuscript received January 18, 2016; revised May 30, 2016; accepted Au-gust 8, 2016. Date of publication August 16, 2016; date of current versionFebruary 11, 2017. This work was supported by CAPES–Brazilian FederalAgency for Support and Evaluation of Graduate Education within the Ministryof Education of Brazil, Federal University of Santa Catarina and Power Elec-tronics Institute (INEP). Recommended for publication by Associate Editor R.Ayyanar.

D. G. Bandeira is with the Power Electronics Institute, Department of Elec-trical Engineering, Federal University of Santa Catarina, Florianopolis, SC88040-970, Brazil (e-mail: [email protected]).

I. Barbi is with the Department of Automation and Systems, FederalUniversity of Santa Catarina, Florianopolis, SC 88040-970, Brazil (e-mail:[email protected]).

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TPEL.2016.2600654

I. INTRODUCTION

I SOLATED dc–dc converters with capacitive output filtersare widely used in applications to meet the requirements of

galvanic isolation and voltage conversion ratio, such as hybridelectric vehicles, solar, telecom, automotive, eolic, ultracapaci-tor system, uninterruptible power system, battery energy storagesystem, and others [1]–[7].

The full-bridge zero voltage switching modulated by pulsewidth with phase shift dc–dc converter (FB-ZVS-PWM-PS) issuitable for such applications due to the following features: highpower density, zero voltage switching, bidirectional power trans-fer capability, modular, symmetric structure, and high-frequencygalvanic isolation [8]–[14].

The three-level zero voltage switching modulated with pulsewidth dc–dc converter (TL-ZVS-PWM) is used for high powerand high input voltages because it enables the use of low voltage-rated semiconductor devices that have small on-state resistance,small parasitic capacitance, and reduced reverse recovery of theintrinsic diode of MOSFETs, when compared to higher voltagerated devices [15]–[20].

It can be seen that both FB-ZVS-PWM-PS and TL-ZVS-PWM share similar features, but the rated dc-bus voltagedefines which one should be used. These features lead to highefficiency power conversion and generation of many othertopologies, starting from these two cells and improving someissues, such as ZVS over a restrict load range, reactive powercirculation, and others.

Considering two level dc–dc converters, the isolated asym-metrical half-bridge zero voltage switching modulated by pulsewidth (HB-ZVS-PWM) is a low cost solution, since it has fewercomponents when compared to other solutions [21]–[24]. How-ever, due to asymmetrical operation, this topology works withrestricted duty cycle range in order to avoid saturation of thetransformer, also the rectifier voltage stresses are different andload dependent. In addition, the filter capacitor voltage changeswith the control duty cycle [25].

In order to overcome the issues of the HB-ZVS-PWM andimprove the primary winding voltage to a three level one, theT-type structure, recently proposed and successfully tested insingle and three-phase inverters, can be used [26], [27].

The aim of this paper is to investigate the utilization of the T-type structure in the design of isolated dc–dc converters. It willbe demonstrated that the proposed converter has features similarto the FB-ZVS-PWM-PS and TL-ZVS-PWM converters, suchas operation at constant switching frequency, soft switching(ZVS) and symmetrical operation of the isolation transformer.

0885-8993 © 2016 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.See http://www.ieee.org/publications standards/publications/rights/index.html for more information.

BANDEIRA AND BARBI: T-TYPE ISOLATED ZERO VOLTAGE SWITCHING DC–DC CONVERTER WITH CAPACITIVE OUTPUT 4211

Fig. 1. Power stage diagram of the proposed TT-ZVS-PWM converter.

However, while the voltages across two power switches areequal to the dc-bus voltage, two other switches are subjectedto half the input voltage, which allows the utilization of lowervoltage switches. To improve the ZVS load range of the circuit,a small inductance is added in order to improve the load rangeto a full range, improving the efficiency. Moreover, to overcomethe reverse recovery issue in the secondary winding rectifierdiodes, a capacitive filter clamps its voltage, and also imposesa linear rate of change in the primary inductor currents. Thecommutation of the rectifier diodes occurs with zero current,thus, improving the efficiency of the converter.

In Section II, the operation of the proposed converter is de-scribed, and theoretical analysis is presented in Section III.Section IV deals with the commutation analysis, Section V pro-poses a design procedure, and experimental results taken froma laboratory prototype are presented in Section VI.

II. T-TYPE DC–DC CONVERTER

The proposed TT-ZVS-PWM dc–dc converter is depicted inFig. 1. It consists of two capacitors Cb1 and Cb2 , where volt-ages are equal to half the input voltage, two main switches,namely S1 and S2 , a bi-directional switch Sb , where (b) and (c)present different configurations for switches implementation.The commutation capacitors (Cr1 . . . Cr3) include the intrinsicparasitic capacitors of the switches. Lr represents the resonantinductance, which includes transformer leakage and parasiticinductances along the circuit. La represents an auxiliary induc-tance that improves the soft switching load range. The outputfilter is composed of the capacitors Co1 and Co2 which areconnected to the secondary winding of the transformer via avoltage doubler rectifier formed by diodes Dr1 and Dr2 . Thecircuit of Fig. 1 can be represented by the equivalent circuit ofFig. 2(a)–(f) provided the following assumptions are made, asfollows:

1) each capacitor of the output filter is represented by a di-rect voltage source with Vo/2 volts and reflected to thetransformer primary side (V ′

o/2);2) the transformer turns ratio is n = Ns/Np and both the

magnetizing inductance and La are neglected along theanalysis;

3) capacitors Cb1 and Cb2 are represented by direct voltagesource with half of the input voltage;

4) all components, including the power semiconductors, areideal.

The proposed converter has three different operation schemes,namely Continuous Conduction Mode (CCM), Boundary Con-duction Mode (BCM) and Discontinuous Conduction Mode(DCM). The operation in CCM will be discussed, since the op-eration in BCM and DCM is similar. Considering CCM, thereare six operating modes within each half of the commutationcycle. They are presented as follows, with the converter mainwaveforms of voltages and currents depicted in Fig. 3, for op-eration in (a) CCM and (b) DCM.

A. t1 ≤ t ≤ t2 [see Fig. 2(a)]

At the instant t = t1 , switch S1 begins to conduct and voltageacross the transformer secondary winding becomes equal toVo/2. The current through the resonant inductance iLr increaseslinearly; thus, the diode Dr1 begins to conduct and power istransferred to the load.

B. t2 ≤ t ≤ t3 [see Fig. 2(b)]

At the instant t = t2 , iLr(t2) = I1 and S1 is turned off. Thecurrent iLr starts flowing through S3 and D4 , the voltage acrossthe resonant inductance is the negative of Vo/2; thus the currentiLr begins to decrease linearly. The next operating stage startsat the instant t = t3 , where S3 is turned off.

C. t3 ≤ t ≤ t4 [see Fig. 2(c)]

At the instant t = t3 , iLr(t3) = I2 when S1 is turned off. Thecurrent iLr flows through the diode D2 . The voltage vab becomesnegative. The current iLr decays linearly to zero, eventuallyreaching zero at the instant t = t4 , where the diode Dr1 currentreduces to zero, and the reverse recovery is eliminated. Duringthis time interval, the switch S2 is gated on.

D. t4 ≤ t ≤ t5 [see Fig. 2(d)]

At the instant t = t4 , iLr becomes negative and starts flowingthrough the switch S2 , the diode Dr2 begins to conduct, andthe voltage across the transformer secondary winding becomesequal to −Vo/2. This stage ends at the instant t = t5 , when theswitch S2 is turned off. The converter operation over the timeinterval Ts/2 ≤ t ≤ Ts is similar, with the topological stagesillustrated in Fig. 2(a) and (d)–(f).

III. THEORETICAL ANALYSIS

A. Voltage Gain at CCM

The converter duty cycle D is defined by (1), considering aswitching period of Ts , both presented in Fig. 3(a). The voltageacross the inductance Lr , depicted in Fig. 3(a), has a null av-erage value, this means that (3) can be used with (1) and (2) todetermine the time instants Δtk , k = 1 . . . 3

Δt1 + Δt2 =DTs

2(1)

Δt3 =(1 − D) Ts

2(2)

(V1/2 − V ′o/2) Δt1 − (V1/2 + V ′

o/2) Δt2 − (V ′o/2) Δt3 = 0.

(3)


Fig. 2. Topological stages of the proposed TT-ZVS-PWM converter.

Fig. 3. Typical theoretical waveforms of the proposed TT-ZVS-PWM converter for operation in (a) CCM; and (b) DCM.


Fig. 4. Static voltage gain of the TT-ZVS-PWM converter as a function of thenormalized load current, for different duty cycles.

The peak currents during each interval are calculated with(4) and (5). The rectifier diode current io waveform is illus-trated in Fig. 3(a), which is used to obtain the average of theoutput current, calculated by (6). The converter static gain q isdefined by (7)

I1 = LrV1/2 − V ′

o/2Δt1

(4)

I2 = LrV1/2 + V ′

o/2Δt2

(5)

Io =I1Δt1

2+

I2Δt22

+(I1 − I2) Δt3

2(6)

q =V ′

o

V1. (7)

With (1)–(7), the static gain q can be obtained as a functionof the converter parameters, shown in (8), whereas the outputcurrent is normalized with (9)

q =√

D (2 − D) − 8Io (8)

Io =4LrfsIo

nV1. (9)

The static gain versus the normalized load current is rep-resented in Fig. 4. Identical behavior is found in the classicFB-ZVS-PWM [18], [28]–[31].

B. Voltage Gain at DCM

Fig. 3(b) shows the key waveforms for operation in the DCMmode. The converter operates in the DCM mode when I2 = 0,because there is not enough energy stored in the Lr inductance.Thus, the current reaches null value during Δt3 time interval.By evaluating the same equations in CCM for I2 = 0, the staticgain is obtained as follows:

q =D2

D2 + 4Io

. (10)

C. Boundary Between CCM and DCM

In the boundary condition, current reaches the null value rightat the time instant equivalent to half of the switching period. This

Fig. 5. Commutation schemes for the primary side switches and auxiliarycommutation inductance configuration.

leads to the following consideration:

LrV1/2 + V ′

o/2Δt2

= 0 (11)

therefore

D = q (12)

Dcrit =1 ±

√1 − 16Io

2. (13)

By replacing the duty cycle in (8), it returns the equation thatshows the boundary between CCM and DCM modes, depictedin (13).

IV. COMMUTATION ANALYSIS

Referring to the topological stages of Fig. 2, there are twocommutations for primary side switches along half of theswitching period, both depending on the Lr stored energy.One commutation starts with iLr(t) = I1 , whereas the otherwith iLr(t) = I2 . As previously demonstrated, I2 = 0 in theDCM mode. Hence, the ZVS load range is inside the CCMarea delimited in Fig. 4. The same limitation is found in theclassic FB-ZVS-PWM. The commutations are described as fol-lows, and a solution to overcome the limited ZVS load range isintroduced.

A. Main Switches Commutation Analysis

Before S1 is turned off,vCr1(t−2 ) = 0, vCr2(t−2 ) = V1 ,vCr3(t−2 ) = 0, vCr4(t−2 ) = V1/2, and iLr(t−2 ) = I1 . The loadcurrent, reflected to the transformer primary side, flows throughS1 and Lr . At the instant t = t2 , S1 is turned off and its cur-rent starts flowing through the switches parasitic capacitors asshown in Fig. 5(a), vCr1 rises linearly from zero to V1/2, vCr4decays linearly from V1/2 to zero, and vCr3 remains equal tozero. Switch S3 remains gated on during this time interval. Thebehavior of the voltage across the equivalent capacitor is rep-resented by (14), from which the commutation time, given by(15) is obtained

CrΔvCr

Δt=

I1

3(14)

tc1 =3CrV1

2I1. (15)


Fig. 6. Auxiliary inductance impact on currents waveforms: (a) CCM; and (b) DCM.

B. Auxiliary Switches Commutation Analysis

Prior to this commutation, the current flows through Lr , S3 ,and D4 , according to Fig. 2(c), with value iLr(t−3 ) = I2 . Atthe instant t = t3 , switch S3 is turned off. The capacitor Cr3begins to charge linearly in parallel with capacitors Cr1 and Cr2 .The corresponding topological stage is shown in Fig. 5(b). Thisstages finishes when vCr2 = 0, vCr1 = V1 and vCr3 = V1/2.The switch S2 is gated on while diode D2 is conducting toensure commutation with zero voltage. Equation (16) can bederived to this commutation, from which the time interval tc2can be evaluated, resulting in (17)

CrΔvCr

Δt=

I2

3(16)

tc2 =3CrV1

2I2. (17)

From (15) and (17), the commutations interval can be ob-tained. As the load decreases, the time interval calculated in (17)tends to increase more than the time interval from (15). There-fore, this time interval is the reference for the dead time (td )necessary to achieve zero voltage switching on main switches;thus

td > tc2 . (18)

C. Commutation in DCM

Considering the operation in the DCM mode, it is verified inwaveforms of Fig. 3(b) that iLr current reaches null value before

the auxiliary switches turns off. At this point, no energy is avail-able in the resonant inductor to perform the charge/dischargein parasitics capacitors of switches; thus, the voltage acrossswitches S1 and S2 before this commutation will bedifferent from zero, and hard switching is obtained. The aux-iliary switches commutations depend on the Lr stored energy,meaning that soft switching will be lost when the converter op-erates at the DCM mode. In fact, this behavior is found in thetraditional full bridge converter with phase shift [29], [30]. Aproper solution for this scheme is to use an auxiliary inductance(La ) in parallel with switches S3 and S4 , and has been shownin Fig. 5(c). The design of this inductance must ensure a currentsource behavior during the auxiliary switches commutation inDCM. The peak value of the current flowing through La (ILa)can be evaluated as follows:

ILa =V1 (DminTs + tc2)

8La. (19)

Replacing I2 by ILa in (16) and solving for La , it returns

La =DminTstc2

12Cr. (20)

By choosing a minimal load to obtain ZVS, calculating theduty cycle for this load (Dmin ), and substituting into (20), itreturns the inductance value to achieve soft switching during theDCM mode. A modification in the circuit current distributiondue the auxiliary inductance is verified in Fig. 6. The iLa currentflows through the primary side switches and passive elements,but does not affect the converter mechanisms.


TABLE IT-TYPE ISOLATED DC–DC CONVERTER SPECIFICATIONS

Symbol Quantity Value (Unit)

Po Output power 2 kWV1 Input voltage 400 VVo Output voltage 400 Vfs Switching frequency 50 kHz– Soft switching load range 20–100%

V. DESIGN PROCEDURE

Given the specifications set listed in Table I, an operationpoint must be chosen, which leads to the static gain q and thenormalized output current Io . In order to validate the auxil-iary inductance behavior, the operation point where q = 0.5,D = 0.7, and Io = 0.123 is adopted; this leads to a small loadrange of soft switching. Using these specification values and(7), the transformer turns ratio is evaluated by the followingequation:

n =400

400 × 0.5= 2. (21)

The resonant inductance value can be obtained from (9). Theexternal parasitic capacitance to achieve ZVS in CCM mode isevaluated with (16). Performing these calculations, it results inthe following equation:

Lr =0.0828 × 400

4 × 50 000 × 2 × 5= 16.51µH. (22)

At this operation point, the available load range for ZVSswitching can be derived from (13) and (6), where the loadnecessary to enter in the BCM mode is the lower limit, in whichIo = 0.062 for q = 0.5. This leads to a small load range of softswitching (75–100%), by choosing the lower limit as 78%, thenormalized current at this load can be evaluated by (9)

Io min =4 × 16.51 × 10−6 × 50 000 × 2

400× 2000 × 0.785

400

= 0.065. (23)

For Io min = 0.065 and q = 0.5, the curves in Fig. 4 returnsD = 0.51, the peak current I2 for this condition can be evaluatedemploying (5). The dead time required for soft switching is thenevaluated using (16). Choosing 3% of the switching period asthe dead time, the commutation capacitor required is obtained,as follows:

Cr =20 × 10−6 × 0.036 × 2 × 1.846

3 × 400≈ 2.2 nF. (24)

In order to improve the load range from 75–100% to 20–100%despite the chosen operating point, the auxiliary inductance isemployed. The normalized current at 20% of load is evaluatedwith (9) as Io = 0.017, the duty cycle Dmin is evaluated atq = 0.5, substituting in (20), returns the following:

La =0.261 × 20 × 10−6 × 250 × 10−9

12 × 2.2 × 10−9 ≈ 45µH. (25)

TABLE IICOMPONENTS USED IN PROTOTYPE

Symbol Parameters Value

Cr 1 , ..., Cr 4 Commutation capacitor 2.2 nF (polyphropilene)Cb 1 , Cb 2 DC link capacitor 2 × 20 µF (polyphropilene)Co 1 , Co 2 Output filter capacitor 200 µF (polyphropilene)La External auxiliary inductance 45 µH -gap = 1 mm

N87-E50 (epcos)LITZ wire (487 × 32 AWG)

Lr External resonant Inductance 15.47 µH-gap=1 mmN87-E40 (epcos)

LITZ wire (487 × 32 AWG)Tr High frequency transformer Np = 4, Ns = 8,Ld = 0.3 µH

N87-E60(epcos)LITZ wire (487 × 32 AWG)

S1 , S2 Main switches IPW60R041C6 (Infineon)S3 , S4 Auxiliary switches IRFP4332PBF (IR)

Fig. 7. Prototype of the proposed TT-ZVS-PWM converter.

VI. EXPERIMENTAL RESULTS

In order to validate the analysis results, a 2-kW proto-type was designed, built, and tested. Table I summarize theprototype specifications, whereas Table II shows passive com-ponents based on results of Section V with semiconductors em-ployed in the prototype construction, which is depicted in Fig. 7.The parameters have been combined to ensure soft-commutation(ZVS) for 20–100% of load range; thus, an external inductanceof 45 µH was added in parallel with the primary winding of thetransformer. An external inductance of 15.65 µH was added inseries with the leakage inductance of the transformer to providethe desired resonant inductance.

The waveforms presented in Fig. 8(a)–(f) illustrate the op-eration in DCM of the proposed converter. The voltage acrossthe auxiliary switches depicted in (a) have half the input volt-age, without significant overshoot due to ZVS commutation,obtained even with iLr reaching the null value during the con-verter operation. In Fig. 8(b), the auxiliary inductor current(iLa) is show with the voltage across one main switch and oneauxiliary switch, both with ZVS commutation. A scaled viewof Fig. 8(b) illustrated in Fig. 8(c) shows the critical commu-tation in DCM, performed by the peak value of iLa , whichis predicted in Section IV-C. In Fig. 8(d), ZVS commutationof the main switch S1 is verified by the gate signal of main


Fig. 8. Experimental results for DCM operation (Po = 400 W). (a) Auxiliary switches drain source voltages (100 V/div) and resonant inductor current iLr(10 A/div). (b) Main switch drain source voltage vS 1 (100 V/div), auxiliary switch drain source voltage vS 3 (100 V/div) and auxiliary inductor current iLa(5 A/div), where (c) details the commutation. (d) Gate source voltage vg 1 (20 V/div), main switch drain source voltage vS 1 (100 V/div) and gate source voltagevS 4 (20 V/div). (e) Gate source voltage vg 2 (20 V/div), auxiliary switch drain source voltage vS 3 (100 V/div) and gate source voltage vg 3 (20 V/div).

switch S1 (vg1) changing level right after the voltage acrossswitch S1 reaches null value, as predicted in Sections IV-Band IV-C. In Fig. 8(e), ZVS commutation of switch S3 is ver-ified by the gate signals of switches S3 (vg3), S2 (vg2) and thevoltage across the switch S3 (vg3), since vg3 reaches the nullvalue a half-period before switch S3 turns on, as predicted inSection IV-A.

Considering the operation in BCM and CCM, the resultsare presented in Fig. 9(a) and (b)–(f), respectively. The voltageacross the auxiliary switches and iLr are presented in Fig. 9(a)for the operation in BCM. The waveforms presented in Fig. 9(b)show the current flowing through the resonant inductor and thevoltage across the transformer primary winding with the threelevels, corresponding to the expected theoretical waveforms inCCM. Fig. 9(c) shows ZVS commutation of the main switch S1and Fig. 9(d) shows ZVS commutation of the auxiliary switchS3 , with the same mechanism described earlier. Fig. 9(e) shows

the capacitor dc-link voltages, both stable with and equal tohalf of the input voltage, due to the symmetrical behavior ofthe converter in open loop operation. Fig. 9(f) shows the outputvoltage and current for nominal load conditions.

The converter efficiency was measured employing a Yoko-gawa WT300 power analyzer and is shown in Fig. 9(g). Forq = 0.5, the maximum value, equal to 94.2%, occurs at 41% ofthe rated load power, whereas at the rated power, the measuredefficiency is 92.6%. Several efficiency tests for the same spec-ifications and a different operation point (defined by q = 0.65,D = 0.9, and Io = 0.07084) are plotted, with efficiency equiv-alent to 95%. A further investigation in efficiency reveals thatconduction losses increases when operating with La , as demon-strated in Fig. 9(h) and (i). An improvement in conduction lossesalso is achieved in the second operation point, demonstrated inFig. 9(i). Therefore, a proper parameter combination can leadto high efficiency.


Fig. 9. Experimental results for BCM and CCM operation (Po = 1:3 kW and Po = 2 kW). (a) Auxiliary switches drain source voltages (50 V/div) and resonantinductor current iLr (20 A/div) for BCM operation. (b) Primary winding transformer voltage vab (100 V/div) and resonant inductor current iLr (20 A/div).(c) Auxiliary switch gate source voltage vg 4 (20 V/div), main switch gate source voltage vg 1 (20 V/div) and drain source voltage vS 1 (90 V/div). (d) Gate sourcevoltage vg 2 (20 V/div), auxiliary switch drain source voltage vS 3 (50 V/div) and gate source voltage vg 3 (20 V/div). (e) DC bus capacitance voltages vcb1 andvcb2 (100 V/div); (f) Output voltage vo (100 V/div) and output current Io (5 A/div). (g) Measured efficiency versus the load power of the proposed TT-ZVS-PWM,for different static gains. (h) Conduction losses on the transformer primary side elements. (i) Conduction losses for two operation points.


VII. CONCLUSION

A new four-switch power-circuit topology, for realization ofisolated dc–dc converters with capacitive output filter was pro-posed, analyzed, designed, and tested in the laboratory. Fromthe theoretical and experimental results presented in this paper,the proposed topology is well suited to economical realizationof high power density and high efficiency power supplies.

ACKNOWLEDGMENT

The authors would like to thank A. L. S. Pacheco andL. M. Coelho for the support during the prototype assemblyand CAPES for the financial support.

REFERENCES

[1] M. Yilmaz and P. Krein, “Review of the impact of vehicle-to-grid tech-nologies on distribution systems and utility interfaces,” IEEE Trans. PowerElectron., vol. 28, no. 12, pp. 5673–5689, Dec. 2013.

[2] M. Yilmaz and P. Krein, “Review of battery charger topologies, chargingpower levels, and infrastructure for plug-in electric and hybrid vehicles,”IEEE Trans. Power Electron., vol. 28, no. 5, pp. 2151–2169, May 2013.

[3] S. Y. Kim, H.-S. Song, and K. Nam, “Idling port isolation control ofthree-port bidirectional converter for EVs,” IEEE Trans. Power Electron.,vol. 27, no. 5, pp. 2495–2506, May 2012.

[4] T. Hirose and H. Matsuo, “Standalone hybrid wind-solar power generationsystem applying dump power control without dump load,” IEEE Trans.Ind. Electron., vol. 59, no. 2, pp. 988–997, Feb. 2012.

[5] H. Fakham, D. Lu, and B. Francois, “Power control design of a batterycharger in a hybrid active PV generator for load-following applications,”IEEE Trans. Ind. Electron., vol. 58, no. 1, pp. 85–94, Jan. 2011.

[6] H. Wu, P. Xu, H. Hu, Z. Zhou, and Y. Xing, “Multiport converters basedon integration of full-bridge and bidirectional DC-DC topologies for re-newable generation systems,” IEEE Trans. Ind. Electron., vol. 61, no. 2,pp. 856–869, Feb. 2014.

[7] J. Sabate, V. Vlatkovic, R. Ridley, F. Lee, and B. Cho, “Design consid-erations for high-voltage high-power full-bridge zero-voltage-switchedPWM converter,” in Proc. 5th Annu. Appl. Power Electron. Conf. Expo.,Mar. 1990, pp. 275–284.

[8] D. Costinett, D. Maksimovic, and R. Zane, “Design and control for highefficiency in high step-down dual active bridge converters operating athigh switching frequency,” IEEE Trans. Power Electron., vol. 28, no. 8,pp. 3931–3940, Aug. 2013.

[9] B. Zhao, Q. Song, and W. Liu, “Efficiency characterization and Optimiza-tion of isolated bidirectional DC-DC converter based on dual-phase-shiftcontrol for DC distribution application,” IEEE Trans. Power Electron.,vol. 28, no. 4, pp. 1711–1727, Apr. 2013.

[10] H. Bai and C. Mi, “Eliminate reactive power and increase system efficiencyof isolated bidirectional dual-active-bridge DC-DC converters using noveldual-phase-shift control,” IEEE Trans. Power Electron., vol. 23, no. 6,pp. 2905–2914, Nov. 2008.

[11] A. Jain and R. Ayyanar, “PWM control of dual active bridge: Comprehen-sive analysis and experimental verification,” IEEE Trans. Power Electron.,vol. 26, no. 4, pp. 1215–1227, Apr. 2011.

[12] Y. Xie, R. Ghaemi, J. Sun, and J. Freudenberg, “Implicit model predictivecontrol of a full bridge DC-DC converter,” IEEE Trans. Power Electron.,vol. 24, no. 12, pp. 2704–2713, Dec. 2009.

[13] B. Zhao, Q. Song, W. Liu, and Y. Sun, “Dead-time effect of the high-frequency isolated bidirectional full-bridge DC-DC converter: Compre-hensive theoretical analysis and experimental verification,” IEEE Trans.Power Electron., vol. 29, no. 4, pp. 1667–1680, Apr. 2014.

[14] G. Yadav and N. Narasamma, “An active soft switched phase-shiftedfull-bridge DC-DC converter: Analysis, modeling, design, and implemen-tation,” IEEE Trans. Power Electron., vol. 29, no. 9, pp. 4538–4550,Sep. 2014.

[15] J. Duarte, J. Lokos, and F. van Horck, “Phase-shift-controlled three-levelconverter with reduced voltage stress featuring ZVS over the full operationrange,” IEEE Trans. Power Electron., vol. 28, no. 5, pp. 2140–2150,May 2013.

[16] W. Li, S. Zong, F. Liu, H. Yang, X. He, and B. Wu, “Secondary-sidephase-shift-controlled ZVS DC/DC converter with wide voltage gain forhigh input voltage applications,” IEEE Trans. Power Electron., vol. 28,no. 11, pp. 5128–5139, Nov. 2013.

[17] W. Li, P. Li, H. Yang, and X. He, “Three-level forward-flyback phase-shiftZVS converter with integrated series-connected coupled inductors,” IEEETrans. Power Electron., vol. 27, no. 6, pp. 2846–2856, Jun. 2012.

[18] B.-R. Lin and C.-H. Chao, “Analysis, design, and implementation of asoft-switching converter with two three-level PWM circuits,” IEEE Trans.Power Electron., vol. 28, no. 4, pp. 1700–1710, Apr. 2013.

[19] P. Das, M. Pahlevaninezhad, and A. Kumar Singh, “A novel load adaptiveZVS auxiliary circuit for PWM three-level DC-DC converters,” IEEETrans.Power Electron., vol. 30, no. 4, pp. 2108–2126, Apr. 2015.

[20] J. Pinheiro and I. Barbi, “The three-level ZVS-PWM DC-to-DC con-verter,” IEEE Trans. Power Electron., vol. 8, no. 4, pp. 486–492, 1993.

[21] J. Feng, Y. Hu, W. Chen, and W. Chau-Chun, “ZVS analysis of asymmet-rical half-bridge converter,” in Proc. 32nd Annu. IEEE Power Electron.Spec. Conf., 2001, vol. 1, pp. 243–247.

[22] O. Garcia, J. Cobos, J. Uceda, and J. Sebastian, “Zero voltage switchingin the PWM half bridge topology with complementary control and syn-chronous rectification,” in Proc. 26th Annu. IEEE Power Elect Spec. Conf,Jun. 1995, vol. 1, pp. 286–291.

[23] W. Chen, P. Xu, and F. Lee, “The optimization of asymmetric half bridgeconverter,” in Proc. 26th Annu. IEEE Appl. Power Electron. Conf. Expo.,2001, vol. 2, pp. 703–707.

[24] P. Imbertson and N. Mohan, “Asymmetrical duty cycle permits zeroswitching loss in PWM circuits with no conduction loss penalty,” IEEETrans. Ind. Appl., vol. 29, no. 1, pp. 121–125, Jan. 1993.

[25] R. Oruganti, P. C. Heng, J. T. K. Guan, and L. A. Choy, “Soft-switchedDC/DC converter with PWM control,” IEEE Trans. Power Electron.,vol. 13, no. 1, pp. 102–114, Jan. 1998.

[26] P. Knaup, “International patent application,” WO 2007/048420 A1,Sep. 2014.

[27] M. Schweizer and J. Kolar, “Design and implementation of a highlyefficient three-level T-type converter for low-voltage applications,” IEEETrans. Power Electron., vol. 28, no. 2, pp. 899–907, Feb. 2013.

[28] V. Vlatkovic, M. Schutten, and R. Steigerwald, “Auxiliary series resonantconverter: A new converter for high-voltage, high-power applications,”in Proc. 11th Annu. IEEE Appl. Power Electron. Conf. Expo., vol. 1,Mar. 1996, pp. 493–499.

[29] I. Barbi and W. Aragao Filho, “A nonresonant zero-voltage switchingpulse-width modulated full-bridge DC-to-DC converter,” in Proc. 16thAnnu. Conf. IEEE Ind. Electron. Soc., Nov. 1990, vol. 2, pp. 1051–1056.

[30] D. Gautam, F. Musavi, W. Eberle, and W. Dunford, “A zero-voltageswitching full-bridge DCDC converter with capacitive output filter forplug-in hybrid electric vehicle battery charging,” IEEE Trans. PowerElectron., vol. 28, no. 12, pp. 5728–5735, Dec. 2013.

[31] A. Jose Bento Bottion and I. Barbi, “Input-series and output-series con-nected modular full-bridge PWM DC-DC converter with capacitive out-put filter and common duty cycle,” in Proc. 11th IEEE/IAS Ind. Appl.,Dec. 2014, pp. 1–8.

Delvanei Gomes Bandeira Jr. was born in Pelotas,Rio Grande do Sul, Brazil, in 1986. He received theB.S. degree from the Catholic University of Pelotas,Pelotas, Brazil, in 2010, and the M.S. degree from theFederal University of Santa Catarina, Florianopolis,Brazil, in 2014, both in electrical engineering. He iscurrently working toward the Ph.D. degree in elec-trical engineering in the Power Electronics Institute,Federal University of Santa Catarina.

His research interests include soft switching,switched capacitors, and high voltage power supplies.

Ivo Barbi (F’11) was born in Gaspar, Santa Catarina,Brazil, in 1949. He received the B.S. and M.S. degreesin electrical engineering from the Federal Universityof Santa Catarina, Florianopolis, Brazil, in 1973 and1976, respectively, and the Dr. Ing. degree in electri-cal engineering from the Institut National Polytech-nique de Toulouse, Toulouse, France, in 1979.

He is a Researcher in the Solar Energy ResearchCenter, and a Professor of Electrical Engineering atthe Federal University of Santa Catarina. He is theFounder of the Brazilian Power Electronics Society

and the Brazilian Power Electronics Conference in 1990, and the BrazilianPower Electronics and Renewable Energy Institute (IBEPE) in 2016. He is thePresident of the IBEPE

He is an Associate Editor of the IEEE TRANSACTIONS ON POWER ELECTRON-ICS and the IET Electronics Letters.

Documents

A T-Type Isolated Zero Voltage Switching DC–DC Converter With … em periódicos... · 4210 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 32, NO. 6, JUNE 2017 A T-Type Isolated