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A study on interface traps and near interfacial bulk
traps in the interfaces of dielectric/semiconductor and
semiconductor hetero-junction
Chunmeng Dou
Supervisor: Prof. Hiroshi Iwai
& Prof. Kuniyuki Kakushima
Electronics and Applied Physics
Interdisciplinary Science and Engineering Group
Tokyo Institute of Technology
1
Tokyo Institute of Technology final examination 2013-02-06
2
Content of this thesis
Ch.1. Introduction
Ch.2. Review of interfacial traps
characterization techniques
Ch.3. Profiling interface
traps distribution on Si
fins by charge-pumping
method
Ch.7. Conclusion
Ch.4. Evaluation of oxide traps
distribution by C-V measurement
Ch.5. Modified conductance method
Ch.6. Investigation on
Interface traps and near
interfacial bulk traps in
AlGaN/GaN by
conductance method
Interfacial traps
on Si finsOxide traps in high-k/III-V
Interfacial traps in
nitride hetero-junctions
3
Future trend of IC technology
2000 2010 2020 2030
CMOS More Moore
New Application
digital+analog+optical
Silion+III-V/III-Nitride
Electrical+Mechanical
New Technologies
Carbon Based
Spintronics
Magnetic Domains
Molecular Switches …….
New structures/materials
High-k/metal-gate
Multi-gate structure
High mobility channel
M. Bohr, Moore’s law in the innovation era,
Proc. of SPIE, vol. 7974, pp. 797402/1-8 (2011)
Future progress driven by CMOS scaling, semiconductor device
diversification, and revolutionary device concepts.
4
Emerging FETs with novel structure/material
New structure New material
Multi-gate for high ION/IOFF
ratio:
III-V/Ge for low power-consumption digital IC:
III-Nitride for high power/frequency application:
yx zdEdE dE
dx dy dz
Interface and near interface traps: device-killing factor
5
w/o traps
with traps
S D
Gate
Oxide or
barrier layer
Interface trap
bulk trap
w/o traps
with traps
Gate voltage
Log (
I d)
Relaxed sub-
threshold control
Cox
Cs
Degraded
ION
Evaluation and control of interfacial traps is crucial for introducing
novel structure and material
6
Interfacial issues of 3D nanostructures
Si
Cross-sectional view of Si fins D. Schroder, “Semiconductor material and device
characterization”, 3rd edition, Willey Interscience, 2006
(100)
(111)
Spatial distribution of density of interface states, Dit, at the 3D
surface, depending on crystalline orientation and fabrication process,
has to be investigated
varying crystalline
orientation
etch
ed s
urf
ace
SiO2
7
Interfacial issues of III-V based MOS systems
Non-stoichiometry in compound
semiconductor:
Lack of high-quality interfacial oxide
layer with large band-offset:
Large amounts of interface traps large amounts of oxide border traps
Separate evaluation of interface traps and oxide border traps is
necessary
Si:
GaAs:
disruption of periodic crystal
+ traps due to additional vacancies
SiO2/Si:
~ 2.5 eV
Al2O3/InGaAs
~ 2.0 eV
8
Al0.25Ga0.75N
GaN
Lattice constant
PPE
PSP
PSP
Metal GaNAlGaN
2DEG
Polarization
interface charge
SP: spontaneous polarization
PE: piezo-electric polarization
Interfacial issues of AlGaN/GaN hetero-interface
Due to the lattice mismatch
Interface traps exist at the hetero-interface.
Bulk traps may exist in the thin AlGaN layer under tensile strain
Metal
GaN
Sub.
Al0.25Ga0.75N
Tensile strain
Purpose of this study
9
Developing characterization techniques to analyze the interfacial issues of
representative devices with novel structure (3D) and materials (III-V/III-Nitride)
3D structure III-V MOS system Nitride hetero-junctions
(1) Provide general guideline for interface characterization when new
structure and material are introduced.
(2) Strengthen the understanding of trapping/de-trapping mechanisms
Spatial distribution of Dit Dit and Nbt evaluation Dit the hetero-interface
10
Content of this thesis
Ch.1. Introduction
Ch.2. Review of interfacial traps
characterization techniques
Ch.3. Profiling interface
traps distribution on Si
fins by charge-pumping
method
Ch.7. Conclusion
Ch.4. Evaluation of oxide traps
distribution by C-V measurement
Ch.5. Modified conductance method
Ch.6. Investigation on
Interface traps and near
interfacial bulk traps in
AlGaN/GaN by
conductance method
Interfacial traps
on Si finsOxide traps in high-k/III-V
Interfacial traps in
nitride hetero-junctions
Admittance analysis Charge-pumping
methodC-V based-method Conductance method
1. Common method for
evaluate MOS capacitor
1. Sensitive to low Dit,
and other information
is available
Direct evaluation of Dit by
measuring the electron-
hole recombination current
at the trap sites2. Convenient measurement for MOS capacitor
1. Required theoretically ideal C-V model or
equivalent circuit model
Requiring MOSFET or
diode configuration
2. Not applicable for MOS capacitors on SOI
3. Separate evaluation of interface traps and near
interface bulk traps is lack of discussion
11
Ad
van
tages
Pro
ble
ms
Preliminary evaluation when
new materials are introduced
Accurate profiling in
advanced structures
Comparison on different characterization techniques
12
Choosing proper characterization techniques
III-V MOS system
Dit and Nbt evaluation
Metal
GaN
Sub.
Al0.25Ga0.75N
Tensile strain
New materialNew structure
Charge-pumping method
to evaluate spatial
distribution of Dit at 3D
surface (Ch.3)
Admittance analysis
Capacitance (Ch.4) and conductance (Ch.5)
analysis in III-V MOS capacitance
conductance analysis (Ch.6) in hetero-interface
III. Profiling interface traps distribution on Si fins
by charge-pumping method
13
Experimental setup and sample preparation
Optimal forming gas annealing condition for lowering Dit
Evaluation of the spatial distribution of Dit on the 3D
surfaces of Si fins
Charge-pumping (CP) method for SOI structure
14
Gated-diode structure:
Vgamp
Vbase
tr tf
CP method can be applicable to SOI structure by Gated p-i-n diode
accumulation
Inversion
T. Ouisse, et al., IEEE Trans. Electron Devices,
vol.38, no. 6, pp.1432-1444 (1991)
N+ P+e- h+
Si sub.
BOX
W
Pulse Vg
VR
A
CP current
Gate pulse waveform:
Ef,acc
Ef,inv
EC
EV
Electron
trapping
hole
trapping
tr↓
tf↑
15
100
BOX
N+ P+
W
Devices fabrication
Si Sub.
BOX
W
Si Sub.
BOX
SiO2
Si Sub.
BOX
W
N+
Si Sub.
BOX
W
P+N+
Si Sub.
BOX
W
P+N+
Al
Fin Patterning
Starting wafer:p type 140ohm-cm
SOI wafer (100)-oriented
SOI layer (70nm) / BOX layer (50nm)
Gate oxide film formation by a dry oxidation
at 1000 oC for 10min.
W film deposition by RF sputtering
P implantation
(Phosphorus, 30keV, 3×1014 cm-2)
BF2 implantation
(Boron , 30keV, 3×1014 cm-2)
Activation annealing in N2 gas ambient
at 800 oC for 5min.
Al contacts deposition by thermal evaporation
(source and drain regions and back side )
Annealing in F.G. ambient
at 300 oC to 440 oC by 20 oC steps for 30 min.
For Fin:Wfin: 80 – 110 nmHfin : 70 nm
For planarW: 46 & 78 mm
16
Vamp= 2V
Vr= 0.05V
f = 500kHz
tr= 100nsec
Vbase (V)
I cp
(nA
)
0
10
20
30
-3 -2 -1 1
tf = 100nsectf = 200nsectf = 300nsectf = 400nsec
L = 4.0mm
W = 78mm
(a)
0
0
-1
1
-2-3
Vbase (V)
0
10
20
30
I cp
(nA
)
Fall time tf (ns)400300200
26
27
28
29
I cp
,ma
x(n
A)
100
Dit(Eem)
(b)
25
Vamp= 2V
Vr = 0.05V
f = 500kHz
tr = 100nm
L = 4.0 mm
W = 78 mm
100 200 300 40025
26
27
28
29
I cp
,ma
x(n
A)
(a) Fall time tf (ns) (b)
Dit (Eem,e)
Typical charge-pumping characteristics
Typical “hat” shape charge pumping current is confirmed
By changing tf and tr, Dit at the upper and lower halves of band-gap
can be extracted
17
0.28 0.30 0.32-0.32 -0.30 -0.281010
1012
1011
1013
1010
1012
1011
1013
E − Ei (eV)
Dit
(cm
-2eV
-1)
(a) (b)
(c) (d)
Wfin = 100 nm, Hfin = 100 nm,
Forming gas annealing for passivation of the Dit on Si fins
Passivation of Si dangling band:
From 300 oC to 420 oC:
Si-H bond formation
From 420 oC to 540 oC:
Si-H bond dissociation
Optimal F.G annealing temperature
~ 420 oC
For Si fins: optimal F.G. annealing temperature at 400 ~ 420oC;
similar to planar SiO2/Si(100) case
18
-0.32 -0.30 -0.28 0.28 0.30 0.321010
1012
1010
1011
(c) 3D (d)
1011
(a) planar (b) planar
E−Ei (eV)
Dit
(cm
-2eV
-1)
Channel widths dependence of the Dit
For planar devices:
Dit does not depend on W
Uniform Dit distribution
For Si fins:
Dit increases as W decreases
Non-uniform Dit distribution
(lower Dit at the top walls)
The average Dit on the surfaces of Si fins increases as channel
width decrease
3D
19
Dit @ E-Ei = 0.29 eV
Fitting with corners
0 50 100 150
Wfin (nm)
0
1
2
3
Dit
(cm
-2eV
-1)
Dit,2Δ
Dit of (100) planar SOI
×1011
Wfin from 80 to 110 nm
Hfin = 70 nm
Evaluation the local Dit distribution
, , ,2 2( 2
2
)fin it top fin it side it corner
it
fin fin
W D H D DD
W H
(100) (110)
with
corners
3.2 ×1010
cm-2eV-1
2.3 ×1011
cm-2eV-1
3.0 ×1011
cm-2eV-1
, it fin it topD W D
, ,2( 2 2
)
2
fin it side it corner
it fin
fin
H D DD W
H
Dit, corners > Dit, side > Dit, top
Chapter 3: Summary of achievements
Optimal forming gas annealing temperature for Si fins is
confirmed (400 ~ 420 oC)
At the surface of Si fins patterned from (100) SOI wafer,
Dit, corners > Dit, side > Dit, top
mainly due to surface crystalline orientation
20
Method for profiling the spatial distribution of
Dit on 3D nanostructure is established
IV. Evaluation of oxide traps distribution by C-V measurment
21
Origin of the frequency dispersion of C-V curves in
accumulation region
Distributed model considering the frequency and
temperature dependent response of oxide border traps
Evaluation of oxide border traps distribution in energy and
space by C-V technique
22
Origin of the frequency dispersion in accumulation
1.0 0.5 0.0 0.5 1.0
Cap
aci
tan
ce (
mF
/cm
2)
0.0
0.5
1.0
1.5
2.0
2.5
Voltage (V)
Vfb
100 Hz
1MHz
Pt/HfO2/Al2O3/n-In0.53Ga0.47As MOSCAP
Ch
ara
cteri
stic
Fre
qu
ency
Trap energy level
depletion
accumulation
In depletion, the frequency dispersion can be attributed to mid-gap Dit.
In accumulation, the time constant at interface can be given by:
t0 ≈ (NDOS s vth)-1 ≈ 10-9~10-10 s
which is too fast to cause frequency dispersion from 100 Hz to 1MHz
f=1/2pt0 & t0 = (nss vth)-1
23
Trapping/de-trapping of the near interfacial oxide traps, i.e., border traps
Origin for the frequency dispersion in accumulation
Tunneling front model:
F.P. Heiman et al., IEEE TED, 12(4) 167-178(1965)
( ) , 2 E xbt 0E x e kt t
Time constant of border trap
10 C n th(N v )t s
with
&*( ) ( ) /ox
CE 2m E Ek
oxC CE E 2 eV
Considering lack of thermal-dynamically stable interfacial layer with large
band-offset in III-V MOS system, there are a large amount of electrically
active border traps reside in the high-k layer.
Band-offset for Al2O3/In0.53Ga0.47As:
for SiO2/Si: oxC CE E 2.6 eV
24
Combined influence of frequency and temperature
Establish a method to readily evaluate the quality of the high-k oxide.
Multi-frequency C-V
at various temperatures
Oxide traps distribution in
energy and space
Investigate the frequency and temperature dependent response of Oxide traps
Although the direct tunneling model suggest ignorable temperature dependence
of the frequency dispersion in accumulation….
Vg (V)
Ca
pa
cita
nce
(m
F/c
m2)
0.0 0.5 1.0-0.5-1.0 0.0 0.5 1.0-0.5-1.0 0.0 0.5 1.0-0.5-1.0 0.0 0.5 1.0-0.5-1.00.0
1.0
2.0
2.5
1.5
0.5
300 K 210 K 150 K 77 K 100 Hz
1MHz
25
Distributed border traps model for MOS capacitor
substrategate
CS
∆Gbt∆Cbt
∆Cbt ∆Gbt∆Cbt ∆Gbt
x = 0
Cox
G Sub● ● ● ● ● ●
x = tox
𝜀𝑜𝑥/∆𝑥 𝜀𝑜𝑥/∆𝑥
𝑁
∆𝑥 = tox/𝑁
Border traps:
Charge storage
+ energy loss
Y. Yuan, et al., IEEE TED, vol.59, No.8 (2012)
By inputting: (1) Cox and tox ; (2) Cs ; (3) Nbt (x) ; (4) t0 and k
Admittance characteristics can be numerically calculated and fitted with
experimental results
26
Empirical evaluation for frequency and temperature dependence
Metal
n-III-V sub.
x0(f, T)
(a) Measuring Frequency (f) dependency
(b) Measuring Temperature (T) dependency~ thermal activated capture cross section ~
b0
E exp
kTs s
11.5 0.5
b0 C0 th0 0
0 0
ET T(T) N v exp
T T kTt s
0
0
1 1x (f,T) ln
2 2 f (T)k p t
D.K. Schroder et al., “Semiconductor Material and
Device Characterization” (Wiley, 2006)
wt=1 condition:
Border traps with tbt= t0 e2kx < 1/2pf can response
T dependence t0 = (Nc vth s)-1: f and T depend probing depth x0:
27
III: xmax<x< tox
II: xmin<x< xmax
I:0 < x < xmin
xmax @100Hz
xmin @1MHz
0 100 200 300 400
Temperature (K)
0.0
0.4
0.8
1.2
1.6
Dis
tan
ce f
rom
in
terf
ace
into
th
e o
xid
e(n
m)
2.0
Probing depth decreases with increasing frequency or decreasing temperature
For our measurement window (100 Hz to 1MHz):
Region I: too fast ; Region II: frequency dispersion; Region III: no influence
Empirical evaluation for frequency and temperature dependence
28
Method demonstration 1: Approaching the intrinsic capacitance
high freq.
low freq.
0 100 200 300 400
Temperature (K)
Acc
um
ula
tio
n C
ap
aci
tan
ce (
mF
/cm
2)
1.4
1.8
2.2
2.6
1.0 V
0.8 V
0.6 V
1.0 V
0.8 V
0.6 V
Vg=
The intrinsic capacitance of the InGaAs MOSCAP, without the influence of
border traps, can be sufficiently approached by 1MHz/77K C-V measurement.
29
Method demonstration 2: temperature dependence of t0
III: xmax<x< tox
II: xmin<x< xmax
I:0 < x < xmin
xmax @100Hz
0 100 200 300 400
Temperature (K)
0.0
0.4
0.8
1.2
1.6
Dis
tan
ce f
rom
in
terf
ace
into
th
e o
xid
e(n
m)
2.0
xmin @1MHz
Accumulation capacitance decided by:
CoxCbt(f,T)
Cs, acc
Cox: constant
CS,acc: weak dependence
on f and T
CBT: depends on probing
depth x0(f,T)
Therefore:
if ft0(T) = constant
↔Same Cbt
↔Same Ctot
0
0
1 1x (f,T) ln
2 2 f (T)k p t
Ctot
30
f = 109.65 kHz,
T = 300 K
f = 8.32 kHz,
T = 210K
f = 301.99 Hz,
T = 150K
f = 331.13 kHz,
T = 210 K
f = 25.12kHz,
T = 150K
f = 301.99 Hz,
T = 77 K
0.0 0.5 1.0-0.5-1.0
Vg (V)
(a)
0.0 0.5 1.0-1.0 -0.50.0
0.5
1.0
1.5
2.0
2.5
Cap
aci
tan
ce (
mF
/cm
2)
Fre
qu
ency
(H
z)t 0
(T)/
t 0(T
0)
0 100 200 300 400
Temperature (K)
100
102
104102
104
106
(b)
(c)
(d)
( )
( )
0
0 0
T
T 300K
t
t ( )
( )
0
0 0
T
T 210K
t
t
300 K
210 K
150 K
210 K
150 K
77 K
with Eb = 65 meV
Accumulation capacitance can be well reproduced by lower frequency at decreased
temperature
Inside the conduction band of InGaAs, t0 changes from 10-9~10-10 s to 10-6~ 10-5 s
(103) as temperature decreases from 300 K to 77 K.
Method demonstration 2: temperature dependence of t0 -cont’d
11.5 0.5
b0 C0 th0 0
0 0
ET T(T) N v exp
T T kTt s
31
Extraction of energy and spatial distribution of oxide traps
1). Extraction of energy-voltage relationship
from high-frequency/low-temperature C-V
2). Preliminary evaluation of the spatial
distribution assuming uniformly distributed
oxide traps concentration (Nbt)
Methodology:
3). Extraction of the non-uniform distributed
oxide traps concentration (Nbt)
32
Step 1: Extract energy distribution of border traps from
high-frequency/low-temperature C-V
To avoid the over-estimation of the Cox and surface potential, Vg- energy
relationship can be extracted from high-frequency/low-temperature C-V by
Terman technique.
At Room Temperature, C-V has
distortion in two directions
N. Taoka, et al., IEDM, pp. 610-613, 2011
77K
150K210K300K
Evaluated with
considering
oxide traps
33
Step 2.Preliminary evaluation the spatial distribution of oxide
traps concentration
101 101 103 105 107 109 1011
w (rad/s)
Cap
acit
ance
, C
tot(m
F/c
m2)
1.5
2.0
2.5
3.0
3.5
Nbt : 1.96×1020 cm-3 t0 : 1.8×10-9 s
Measurement window
Region I,II, III
Fitting of C(w) @
Vg = 1V, 300K
Fitting of C(w) @
Vg = 1V, 77K
101 101 103 105 107 109 1011
w (rad/s)
Cap
acit
ance
, C
tot(m
F/c
m2)
1.5
2.0
2.5
3.0
3.5
Measurement window
Region II
Nbt : 7.3×1019 cm-3 t0 : 6.0×10-7 s
Region I,II
Region II
Region II, III
Ctot(w) measured at different temperatures cannot be consistently fitted by
assuming border traps concentration (Nbt) with uniform spatial distribution
Increased Nbt profile toward the gate may exist.
34
Step 3. Extract the non-uniformed distributed oxide traps
distribution
(a) Nbt spatial profile (b) t0 as a function of temperature
(c) Fitted C(w) at different temperature (d) Fitted G(w) at different temperature
Spatial distribution of Nbt
from the interface into the
oxide can be gradually
formed from low-to-high
temperature C-V
35
Extracted border trap distribution in energy and space
High concentration of oxide border traps (1019-1020 cm-3) reside in the
oxide and increases as energy or depth increases.
The increased Nbt as depth increases may attributed to accumulated
defects during high-k growth or the dual layer structure used in this
study.
Charge pumping method
ALD- Al2O3/In0.53Ga0.47As
Chapter 4: Summary of achievements
An empirical way to evaluate the frequency- and temperature-dependent
response of oxide border traps is demonstrated.
Capturing process of oxide traps tends to be thermal activated.
Temperature dependent frequency dispersion of the accumulation
capacitance results from non-uniform distributed oxide border traps.
High concentration of oxide traps (1019-1020 cm-3) reside in the oxide,
which is consistent with the results attained by other techniques.
36
A convenient way to evaluate the oxide traps
distribution in energy and space from frequency- and
temperature-dependent C-V is established
V. Modified conductance method with considering the influence
of oxide border traps
37
Distortion of conductance
curve due to oxide border
traps
Evaluation of distribution of interface traps and oxide border
traps from conductance curves
Temperature dependency of
the conductance behaviors
38
Conductance method with considering oxide traps
The influence of oxide traps is negligible: Large amount of active oxide traps:
Cox
CS
Cit(w)
Gp(w)
2 5 p
it max
G.D ( )
q w
The Gp/w versus w plot does not have
obvious peak behaviors
The influence of oxide traps has to be
taken into consideration
ALD-Al2O3/InP MOSCAP:
Same surface treatment, different oxide deposition parameter
Dit = 3.0e12 cm-2eV-1
Dit = 9.8e11 cm-2eV-1
N. Taoka, et al., Microelectron. Eng., vol. 88 (2011)
39
Conductance behaviors with increasing temperature
Pt/HfO2/Al2O3/n-In0.53Ga0.47As
near flat-band
T increases
20, 40, 60, 80oC
102 103 104 105 106 1070
0.05
0.10
0.15
0.20
0.25
w (rad/s)
Gp/w
(m
F/c
m2)
low frequency response can be confirmed by high temperature measurement,
indicating of existence of the slow traps.
No obvious peak behaviors
∆E
tit = (nsNCsvth)-1exp(∆E/kT)
tbt = tit exp (2kx)
T↑, ns ↑, thus tit &tbt ↓
where ns = NC exp(-∆E/kT)
∆E
40
Determination of Dit, Nbt from conductance curves
Pt/HfO2/Al2O3/n-In0.53Ga0.47As
near flat-band
Oxide traps
response
102 103 104 105 106 1070
0.05
0.10
0.15
0.20
0.25
w (rad/s)
Gp/w
(m
F/c
m2)
Symbols: exp.
Lines: fitted
80oC
60oC
40oC20oC
Interface traps
response
For interface traps:
Standard conductance method
Dit= 1.58×1012 cm-2eV-1
ss = 60 meV
(surface potential fluctuation)
tit = 2.9×10-5 s (20oC), 7.5×10-6 s (40oC),
2.9×10-6 s (60oC), 9.6×10-7 s (60oC),
For oxide traps:
Distributed oxide traps model
0.0 0.2 0.4 0.6 0.8 2.0
4.0
6.0
8.0
Depth (nm)N
bt(c
m-3
eV-1
)
×1019
3.0×1019
6.21×1019
k = 5.5 nm-1
Gp/w characteristics can be well fitted considering
oxide traps
w/o Nbt, Dit may be overestimated
41
Determination of energy level from T dependence of tit
1/kT (eV-1)
30 32 34 36 38 40
80oC
60oC
40oC
20oC
10-7
10-6
10-5
10-7
t it
(s)
∆E ≈ 0.22eV
The energy level can be derived from T dependence of previously
extracted tit without requiring additional sample parameters
Chapter 5: Summary of achievements
42
Conductance method is modified to be applicable
when there is a large amount of electrically active
oxide border traps
High temperature conductance measurements are carried out to confirm the
oxide traps.
Incorporating the influence of oxide traps on conductance, distorted Gp/w
versus w curves can be well fitted.
Without considering oxide traps, Dit may be considerably overestimated,
which leads to misunderstanding the origin of defects.
Energy level can be easily extracted by various temperature measurement.
VI. Investigation on interface traps and near interfacial bulk
traps in AlGaN/GaN by conductance method
43
Device structure
Proposed model for the influence of electrodes on the interfacial
traps in AlGaN/GaN heterojunctions
Comparison on conductance
spectra in AlGaN/GaN
heterojunctions with Ni and
TiN electrodes
44
Devices structure
Metal
Buffer layer (1mm)
Al0.25Ga0.75N (25nm)
Si(111) Substrate
GaN(1mm)
TiN
/Al
/Ti
TiN
/Al
/Ti
2DEG
TEOS-SiO2
AlN
(1nm)
T. Kawanago, et al., ESSDERC2013, Bucharest, Romania
(1) Metal electrode: TiN, Ni
(2) 25 nm Al0.25Ga0.75N barrier layer
(3) 1 nm AlN layer for polarization enhancement
Comparison between AlGaN/GaN and High-k/InGaAs
45
0.0E+0
1.0E-8
2.0E-8
3.0E-8
4.0E-8
5.0E-8
6.0E-8
1.0E+2 1.0E+3 1.0E+4 1.0E+5 1.0E+6102 103 104 105 106
Frequency (Hz)
Gp/w
(S・s
ec/c
m2)
0.0
(x10-8)
Vg=-4.4V
-6.0V
Vg=-6.0V -4.4V
Conductance spectra (Gp/w) in depletion
0.2
0.4
0.6
relatively low Dit in the AlGaN/GaN hetero-interface
Large amounts of distributed border traps do not likely exist in
AlGaN layer
102 103 104 105 106
Frequency (Hz)
Gp/w
(S・s
ec/c
m2)
0.00
100
200
300
400
Vg= 0.7V
Vg= 0.5 V
(x10-8)AlGaN/GaN High-k/InGaAs
distributed border traps response Typical interface traps response
Ni TiN
AC analysis of interface traps in depletion region
46
1.0E+11
1.0E+12
-6 -5.5 -5 -4.5
1.0E-05
1.0E-04
1.0E-03
-6 -5.5 -5 -4.5
0.0E+0
1.0E-8
2.0E-8
3.0E-8
4.0E-8
5.0E-8
6.0E-8
1.0E+2 1.0E+3 1.0E+4 1.0E+5 1.0E+6102 103 104 105 106
Frequency (Hz)
Gp/w
(S・s
ec/c
m2)
0.0
(x10-8)
Vg=-4.4V
-6.0V
Vg=-6.0V -4.4V
Gate voltage (V)-6.0 -5.0 -4.5
1012
1011
10-5
10-4
10-3
TiN
Ni
TiN
Ni
Dit
(cm
-2/e
V)
t(s
ec)
Conductance spectra (Gp/w) Dit and time constant (t)
0.2
0.4
0.6
-5.5
Ni and TiN electrode:
(1) Almost same Dit profile in depletion region (5% higher in Ni case)
(2) Time constant (t ) is longer in case of Ni electrode
47
Conductance spectra (Gp/w) Dit and time constant (t)
0.0E+0
5.0E-9
1.0E-8
1.5E-8
1.0E+2 1.0E+3 1.0E+4 1.0E+5 1.0E+6102 103 104 105 106
Frequency (Hz)
Gp/w
(S・s
ec/c
m2)
(x10-8)
TiN gate Vg=-3.6V
-3.2V
0.0E+0
5.0E-9
1.0E-8
1.5E-8
1.0E+2 1.0E+3 1.0E+4 1.0E+5 1.0E+6
Ni gate Vg=-4.1V
-3.0V
0.5
1.0
1.5
0.0
0.5
1.0
1.5
0.0
1.0E+10
1.0E+11
1.0E+12
-4.1 -3.9 -3.7 -3.5 -3.3 -3.1
1.0E-05
1.0E-04
1.0E-03
-4.1 -3.9 -3.7 -3.5 -3.3 -3.1
Gate voltage (V)-4.1 -3.9 -3.3
1012
1010
10-5
10-4
10-3
TiN
Ni
TiN
Ni
Dit
(cm
-2/e
V)
t(s
ec)
1011
-3.1-3.5-3.7
AC analysis of interface traps in inversion region
Ni and TiN electrode:
(1) Almost same Dit profile in inversion region
(2) Similar time constant (t )
48
In depletion:
There are trapping sites whose energy level and position depend on metal electrode
Model for carriers trapping in depletion & inversion
In inversion:
There are trapping sites that are less dependent of metal electrode, which may
be caused by N vacancies.
Depletion Inversion
GaN
NiNi TiN
N vacancies
Trap sites with discrete energy level or position may exist
TiN
AlGaN
Chapter 6: Summary of achievements
49
Conductance method is applied to analyze the distribution
of interfacial traps in AlGaN/GaN heterojunction
Traps with discrete energy or position in the AlGaN layer are
found near hetero-interface
While the traps that influence the depletion region seems
sensitive to the electrode, those influence the inversion region
are less electrode-dependent
50
Conclusion
Ch.1. Introduction
Ch.2. Review of interfacial traps
characterization techniques
Ch.3. Profiling interface
traps distribution on Si
fins by charge-pumping
method
Ch.7. Conclusion
Ch.4. Evaluation of oxide traps
distribution by C-V measurement
Ch.5. Modified conductance method
Ch.6. Investigation on
Interface traps and near
interfacial bulk traps in
AlGaN/GaN by
conductance method
Interfacial traps
on Si finsOxide traps in high-k/III-V
Interfacial traps in
nitride hetero-junctions
51
Conclusion of this thesis
By adopting proper techniques and proposing models, proper method is chosen and
improved to evaluate the interfacial issues of 3D nanostructures, high-k/III-V MOS
systems, and nitrides heterojunctions.
Method to evaluate the spatial distribution of Dit on Si fins is developed. The
results reveal high Dit at corners. (Chapter III)
Method to profile the distribution of Nbt in MOS devices from frequency- and
temperature-dependent C-V is developed. The results show a large amount of
oxide border traps in high-k/III-V MOS systems. (Chapter IV)
Conductance method for Dit characterization is modified to be applicable for the
case that there are considerable amounts of oxide border traps. The influences of
Dit and Nbt on the conductance curves are divided. (Chapter V)
Conductance method is adopted to evaluate the interfacial traps in III-nitride
hetero-junction. . (Chapter VI)
52
Future works: guidelines for structure/material optimization
Optimizing capture cross-section of the 3D
channel, or the curvature of the corners, is
important to lower Dit.
Further physical analysis need to be carried out
to clarify the species of the electrical active oxide
traps in high-k/III-V MOS systems.
Further work need to be done to identify the
species of the traps and corresponding strategy
should be proposed
53
Publication list
1. C. Dou, D. Lin, A. Vais, T. Ivanov, H. -P. Chen, K. Martens, K. Kakushima, H. Iwai, Y. Taur,
A. Thean, and G. Groeseneken, “Determination of energy and spatial distribution of oxide border
traps in InGaAs MOS capacitors from capacitance-voltage characteristics measured at various
temperature”, accepted by Microelectronics Reliability
2. C. Dou, T. Shoji, K. Nakajima, K. Kakushima, P. Ahmet, Y. Kataoka, A. Nishiyama, N. Sugii,
H. Wakabayashi, K. Tsutsui, K. Natori, and H. Iwai, “Characterization of Interface State Density of
Three-Dimensional Si Nanostructure by Charge Pumping Measurement”, accepted by
Microelectronics Reliability
3. C. Dou, K. Kakushima, P. Ahmet, K. Tsutsui, A. Nishiyama, N. Sugii, K. Natori, T. Hattori, and H.
Iwai, “Resistive switching behavior of a CeO2 based ReRAM cell incorporated with Si buffer layer”,
Microelectronics Reliability, vol. 62, no. 4, pp. 688-691 (2012)
(a)論文 : 3編 (フルペーパー)論文リスト
54
Publication list
(b) 国際会議 : 2編1. C. Dou, S. Sato, K. Kakushima, P. Ahmet, K. Tsutsui, A. Nishiyama, N. Sugii, K. Natori, T.
Hattori, H. Iwai, “Si nanowire with asymmetric channel”, G-COE PICE International
Symposium and IEEE EDS mini-colloquium on Advanced Hybrid Nano Devices, Tokyo Institute
of Technology, Japan (Nov., 2011)
2. C. Dou, K. Mukai, K. Kakushima, P. Ahmet, K. Tsutsui, A. Nishiyama, N. Sugii, K. Natori, T.
Hattori, H. Iwai, “Resistive switching behaviors of ReRAM having W/CeO2/Si/TiN structure”,
ECS Trans., vol. 35, no. 4, pp. 597-603 (2011)
(c) 国内会議 : 2編
1. C. Dou, M. Mamatrishat, D. Zade, S. Sato, K. Kakushima, P. Ahmet, K. Tsutsui, A.
Nishiyama, N. Sugii, K. Natori, T. Hattori, H. Iwai, “Resistance switching behaviors in rare
earth(Ce, Eu) oxide based MIM structures”, the 69th meeting of Japan Society of Applied
Physics (JSAP), Japan (Spring, 2010)
2. C. Dou, K. Mukai, K. Kakushima, P. Ahmet, K. Tsutsui, A. Nishiyama, N. Sugii, K. Natori, T.
Hattori, H. Iwai, “Investigation of the effect of Si buffer layer in CeO2 based RRAM Devices”,
the 70th meeting of Japan Society of Applied Physics (JSAP), Japan (March, 2011)
Thank you very much !
55