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A Study of Carbon Nanotubes and Their Applications in Transistors
prepared for
Penny Beebe Engineering Communications Program
Amit Lal
School of Electrical and Computer Engineering
by
Alan Yu School of Electrical and Computer Engineering
May 17, 2004
CONTENTS
LIST OF FIGURES
iii
I. GLOSSARY 1II. LIST OF SYMBOLS AND ABBREVIATIONS 5
III. INTRODUCTION 6IV. SOURCES 6V. DISCUSSION 7
A. Nanoscale 7 B. Imaging at the Nanoscale 7 1. Transmission Electron Microscopy (TEM) 7 2. Scanning Tunneling Microscopy (STM) 8 C. Carbonic substances ⎯ Diamond, Graphite, and Fullerene 8 D. Carbon Nanotube properties 9 1. Hexagonal Network 9 2. Chirality 10 a. Identifying Chirality 10 b. Chiral Vector 10 3. CNT Electrical Properties 13 a. Metallic and Semiconducting Conduction 13 b. Single and Multi-walled Nanotubes 14 4. CNT Non-Electrical Properties 15 D. Transistors 16 1. Concepts and Uses 16 a. Basic Transistor Operation 16 b. Digital Technology 17 c. Amplifier 18 d. Sensor 18 2. Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) 18 a. N-Type and P-Type Wafers 18 b. Basic MOSFET operation 20 3. Nanotube Transistor 20 a. CNT FET 20 b. CNT SET 21 c. A Successful Carbon Nanotube Field-Effect-Transistor (CNFET) 22
i
d. Sorting CNTs 25 e. Nanotube Placement and Manipulation 26 f. Challenges 27
VI. CONCLUSION 27VII. WORKS CITED 29
VIII. APPENDIX: 3D model for CNFET created by the IBM WRL 32
ii
LIST OF FIGURES Figure 1 Types of carbon 8
Figure 2 CNT, an extended bucky ball 9
Figure 3 Nanotube, yet another form of carbon molecule 10
Figure 4 Chiral angles 11
Figure 5 Chiral vector for CNT characterization 12
Figure 6 Chirality of CNTs and their corresponding electrical conductivities 13
Figure 7 MWNTs 15
Figure 8 SWNT 16
Figure 9 Simple nanotube transistor setup 20
Figure 10 Conductance characteristic of a simple nanotube transistor 21
Figure 11 Conductance versus temperature and Coulomb oscillations 22
Figure 12 Cross sectional diagram of IBM CNFET 24
iii
I. GLOSSARY
amplifier: a device that intensifies an electric signal.
angstrom (Å): 10-10 meter
armchair CNT: a CNT with a chiral angle of 30° and that is metallic
bucky ball: a hollow, spherical molecule made of car-bon
carbon nanotube (CNT): a nanotube made from carbon atoms
channel: the semiconducting part of a transistor through which current flows when the tran-sistor is on
charged particle: an electron or a hole
chiral angle: a measure of the angle at which a graphene sheet is wrapped to form a nanotube
chirality: see chiral angle
CNFET: a field-effect transistor that uses a CNT as the channel
conductance: a measurement of how much current a ma-terial can conduct
Coulomb blockade: the phenomenon where an electron is blocked from passing between the nano-tube and the contact electrodes unless a higher energy is provided
Coulomb oscillation: the characteristic conduction in an SET that alternates between conduction and no con-duction as the gate voltage is changed
current: the flow of charged particles; a higher cur-rent means more charged particles pass through a location in one second
1
diamond: a material made from carbon atoms that is clear, extremely hard, and highly conduc-tive thermally
digital: of or relating to circuits that use discrete numbers to perform all computations and calculations
doping: an engineered or sometimes naturally oc-curring process of replacing atoms of a semiconducting material of 4 valence elec-trons, such as silicon, with elements of ei-ther 3 or 5 valence electrons
double-walled nanotube: an MWNT consisting of exactly two tubes
drain: one of the two electrodes placed at the ends of a transistor channel that receives the charged particles that pass through the channel during conduction
electrode: an electrical contact pad that is used to make an electrical connection between two materials; in a transistor, the source and the drain are electrodes
field-effect transistor: the most widely used type of transistor, with a channel whose current can be regu-lated by the voltages applied at the gate, source, and drain
fullerene: a hollow, cage-like, molecule supported by an atomic network of hexagons and penta-gons
gate: the part of a transistor that has ultimate control over the intensity of the current flowing through the channel
graphene sheet: a single sheet of graphite composed of hex-agonally arranged carbon atoms
graphite: a substance made from multiple layers of graphene sheets stack one on top of another
hole: a positive charged particle (an electron is a negative charged particle)
2
insulating: not conducting, or of such low conduction that any electrical conduction is considered insignificant
impurity: the element used to dope a semiconductor
metallic: highly conducting; providing little or no electrical resistance to the conduction of charged particles
metal-oxide-semiconductor FET (MOS-FET):
an FET where the gate is placed on top of a semiconducting material with an insulator, the oxide, in-between
micro: 10-6
multi-walled nanotube: a nanotube consisting of multiple SWNT of varying diameters placed concentrically so that the spacing between each consecutive SWNT is 3.4 Å
nano: 10-9
nanotube: a hollow tube of nano-scale that can be an SWNT or an MWNT
n-type: doped with elements with 5 valence elec-trons; an n-type MOSFET is turned on by positive voltage at the gate, and off by a negative voltage.
photolithography: a technology in transistor manufacturing that shines light on a wafer to pattern struc-tures to be made
p-type: doped with elements with 3 valence elec-trons; a p-type MOSFET is turned on by negative voltage at the gate, and off by a positive voltage.
scanning tunneling microscopy: a microscopy technique that can image nanoscale surface structures
semiconducting: having electrical conductance that is be-tween an insulator and a metal and that can be adjusted by an outside force, often an applied voltage
3
silicon: an element of 4 valence electrons that is the most widely used semiconducting material in electronics
single-electron transistor (SET): a transistor that conducts current, one elec-tron at a time
single-walled nanotube: a nanotube consisting of a single graphene sheet rolled into a tube, with each end of the tube closed by half of a bucky ball
source: one of the two electrodes placed at the ends of a transistor channel that provides the charged particles necessary for electrical conduction in the channel
transistor: an electronic device formed on semicon-ducting material that can regulate current and also amplify electrical signals
transmission electron microscopy: A technique for imaging nanoscale object
voltage: potential in electricity
wafer: a circular disc of varying thickness and di-ameter composed of an element with 4 va-lence electrons on which are built micro-electronic devices.
zigzag CNT: a CNT with a chiral angle of 0° that can be semiconducting depending on the CNT di-ameter
4
II. LIST OF SYMBOLS AND ABBREVIATIONS SYMBOLS
Å angstrom
Cg capacitance between the gate and the chan-nel (with insulator in-between)
e charge of a single electron
∆Vg gate voltage period for Coulomb oscilla-tions
ABBREVIATIONS
CNFET carbon nanotube field-effect transistor
CNT carbon nanotube
DWNT double-walled nanotube
FET field-effect transistor
IBM WRL CNFET CNFET designed by the IBM Watson Re-search Laboratory
MOSFET metal-oxide-semiconductor field-effect transistor
MWNT multi-walled nanotube
nm nanometer
SET single-electron transistor
SWNT single-walled nanotube
TEM transmission electron microscopy
µm micrometer
5
III. INTRODUCTION
The carbon nanotube (CNT) is a hollow tube composed of carbon atoms. Its diameter
averages tens of nanometers (10-9 meters) and its length can vary from nanometers to
centimeters (10-2 meters). Since their discovery in 1991, carbon nanotubes have been
widely experimented with, and analyzed, for their potential as important new material for
future of micro- and nanoelectronics. In particular, there has been extensive research
done on the suitability of using CNTs in transistor technology. Although many transistor
types exist, the most heavily researched CNT transistors are the field-effect transistor
(FET) and the single-electron transistor (SET). The purpose of my library research has
been to study how the CNT can be used as a material for the FET and the SET. The in-
tended audience of this paper is new graduates of engineering who are unfamiliar with
CNT applications in transistors.
IV. SOUCES
The majority of my sources come from journal articles, such as Applied Physics Letters,
Nature, and others. As a comprehensive resource for the properties of the CNT, I have
used the book Carbon nanotubes : synthesis, structure, properties, and applications, by
M.S. Dresselhaus, G. Dresselhaus, and P. Avouris. I used reviews by McEuen, confer-
ence papers, and various internet resources such as the IBM Watson Research Laboratory
research news. I have also spoken to Cornell University Professor Edwin Kan about the
feasibility of using CNTs in transistors.
6
7
V. DISCUSSION
A. Nanoscale
“Nano” in mathematical terms means 10-9. A nanometer refers to a scale of measurement
that is a billion times smaller than a meter. The height of an average person falls just
short of two billion nanometers (10-9 m). Biological cells, the building blocks of living
organisms, are thousands of nanometers across in diameter. A DNA molecule is about
2.5 nanometers wide. Individual atoms can be up to a few tenths of a nanometer in di-
ameter.
Modern electronics is termed microelectronics because, decades ago, manipulations on
the micrometer (10-6 m) scale was the technological limit. The nanotechnology of today
refers to engineering on a scale that is 1000 times smaller.
B. Imaging at the Nanoscale
Traditional microscopy using light is limited to a resolution of roughly 500nm. For im-
aging structures smaller than a few hundred nanometers, electron beams, instead of light,
are utilized. (Young and Freedman, 2000, pp. 1281-2) Explosive advancements in nano-
tube characterization have been made possible by nanoscale imaging technology which
makes possible the structural study of nanotubes. For example, a nanotube can be tested
for its electrical properties and then imaged to find the corresponding structure
1. Transmission Electron Microscopy (TEM)
TEM uses electron rays analogously to the use of light rays in a microscope. However,
instead of using optical lenses, TEM employs magnetic fields to perform the task of re-
fracting the electron beams. An electron ray is directed perpendicularly to the surface on
which are the nanoscale specimens under study. The rays pass through the specimens
and once again are refocused by magnetic “lenses” and projected onto a photographic
film. Since electron speed can be reduced by dense structural elements, the resulting
TEM images will show variations in color or brightness according to variations in the
specimens’ structural density. The microscope is maintained in vacuum so that electron
beams do not scatter off of air molecules. (Young and Freedman, 2000, pp. 1282-3)
8
2. Scanning Tunneling Microscopy (STM)
STM is a technique used for the 3-dimensional imaging of an atomic surface. It takes
advantage of electron tunneling, the quantum physics phenomenon where, the electron (a
particle) can pass through a potential-energy barrier even if it does not have enough ki-
netic energy to do so according to Newtonian physics. The procedure begins with apply-
ing a voltage between the surface to be scanned and the tip of an extremely sharp probe
(the tip of the probe often terminates in a sin-
gle atom). The probe is brought to within 1
nm from the surface. At this distance, and
with the voltage applied, electrons from the
surface can actually “tunnel” through the sur-
face-potential barrier and unto the probe, creat-
ing a tunneling current that is measured. The
probe will move across the surface under
study, one line at a time, constantly adjusting
its height with respect to the surface so that a
constant tunneling current is maintained. The
result will be that the probe movement perpen-
dicular to the surface will correspond to varia-
tions in the surface terrain. Therefore, the probe movement, both across the surface and
in the direction perpendicular to it, is recorded, and later on taken by a computer program
to generate the 3-dimensional image of the scanned surface area. (Young and Freedman,
2000, pp. 1305-7)
C. Carbonic substances ⎯ Diamond, Graphite, and Fullerene
CNTs fall under the category of fullerenes, which in turn falls under the category of all
carbonic substances. Three forms of carbon are known to exist, diamond, graphite, and
fullerene. Diamond, extremely hard and highly thermally conductive, obtains its proper-
ties from its rigid atomic structure of tetrahedrally arranged carbon molecules. Figure 1a
shows the atomic structure of diamond. Each dot in Figure 1 represents a carbon atom,
and each line between two dots represents the electrical bond between two carbon atoms.
a) diamond c) bucky ball
b) graphite
Figure 1 ⎯ Types of carbon (adapted from Smalley, 2003)
9
Graphite is the second known form of carbon, and is composed of stacked sheets of car-
bon, called graphene sheets. Each graphene sheet is composed of hexagonally arranged
carbon atoms, in a honeycomb pattern. Figure 1b shows two graphene sheets stacked one
on top of the other. Macroscopic chunks of graphite can consist of millions of layers of
stacked graphene sheets.
A third form of carbon, called a fullerene, encompasses all hollow, cage-like structures of
carbon. The bucky ball (Figure 1c) is one example. It is a soccer ball-like sphere of hex-
agonally or pentagonally arranged carbon atoms, and can range in diameter.
D. Carbon Nanotube Properties
1. Hexagonal Carbon Network
The CNT, a fullerene, is like an extended bucky ball (see Figure 2). (Smalley, 2003, in-
terview) It can be thought of as a graphene sheet rolled up to create a seamless cylinder
of variable length, with each end capped by half a bucky ball of corresponding diameter.
The smallest CNT diameter theoretically possible is 0.4nm (Qin et al. 2000, p. 50), or 4 Å
(angstrom), and was successfully fabricated by Wang et al. (2000, pp. 50-1). The diame-
ter can also reach up to 50 nm (Saito, 1999, p. 43). The CNT length to width ratio can be
extremely high, up to 1000 or more.
Figure 3 shows a close-up of the tip of a CNT, once again modeling the hexagonal, hon-
eycomb-like carbon arrangement. Figures 2 and 3 both depict what are called armchair
CNTs. The word armchair refers to the angle in which the hexagonal network of the
nanotube is formed with respect to the tube axis. Therefore, not only the length and di-
ameter of the CNT can be varied, but also helicity of the hexagonal network⎯a property
called chirality.
Figure 2. CNT, an extended bucky ball (adapted from Smalley, 2003)
10
2. Chirality
a. Identifying Chirality
Figure 4 shows the concept of chirality. A series of five CNTs with different chirality
were imaged by STM. The dotted line in each picture, vector T, is drawn along the tube
axis. Another vector, H, is drawn from the same starting point as T, but parallel to the
rows of consecutive hexagons in the carbon network. The angle between vectors T and
H is labeled as Φ. The chiral angle, θ, or chirality, is defined as:
θ = 30° - Φ
Since rows of consecutive hexagons in the carbon network can be found in several direc-
tions, H is chosen such that Φ is the smallest. In other words the vector H is chose to be
parallel to what are called nearest-neighbor
(with respect to the tube axis) hexagon rows.
Figure 4e shows a CNT with the same carbon
structure as those depicted in Figures 2 and 3.
A honeycomb network drawing is superim-
posed on the STM image to show that the near-
est-neighbor hexagon row is actually along the
same direction as the tube axis, thus making a
chiral angle of 30˚ (Φ = 0˚). A CNT with a 30˚
chiral angle has a special name, called the arm-
chair CNT. At 0˚ of chirality (Φ = 30˚), the
CNT is called a zigzag CNT (see Figure 4d). All angles between 0˚ and 30˚ result in
tubes that are termed chiral CNTs. Figures 4a, 4b, and 4c show chiral CNTs with chiral
angles of 23˚, 16˚, and 5˚ respectively.
b. Chiral Vector
CNT structural characterization is most often indicated by what is called the chiral vector,
which indicates both the chiral angle and diameter of the CNT at the same time. In es-
sence the chiral vector is a line that traces the CNT along its circumference from one car-
bon atom (we will call it the reference atom) back to itself. If we cut open the nanotube
along the tube axis and through the reference atom, we can imagine spreading out the
Figure 3. Nanotube, yet another form of carbon molecule
(adapted from Smalley, 2003)
(1)
11
nanotube into a graphene sheet that could exactly match a portion of an infinitely large
graphene sheet. Figure 5 shows the hexagonal carbon network that can be thought of as
the infinitely large graphene sheet. The doted lines at the left and right represent the cut
made along the CNT. Location (0,0) represents the reference atom and is the location
that the chiral vector C starts from. Although the chiral vector begins and ends on the
same reference atom, end is represented by location (11,7) in the graphene sheet, shown
in Figure 5. When the graphene sheet is wrapped into a cylinder, locations (0,0) and
(11,7) will both converge on the same reference atom.
The row of large dots in Figure 5 indicates the nearest-neighbor row of hexagons. Again,
vector H is drawn parallel to the nearest-neighbor row, and also begins from the refer-
ence atom. Whereas the chiral vector is perpendicular to the tube axis, the armchair
doted line is perpendicular to the H vector. If the chiral vector lines up with the armchair
line, the resulting rolled-up nanotube would be the armchair CNT discussed earlier. The
armchair line bisects every hexagon it passes through.
The unit vectors a1 and a2 both begin at one corner of a single hexagon and end two cor-
ners away in the same hexagon. Recall that each hexagon corner in the honeycomb net-
work represents one carbon atom in the physical graphene sheet. a1 and a2 point in the
zigzag directions, or directions that make 30° angles with the armchair direction.
a)
b)
d)
Figure 4. Chiral angles (adapted from Wildoer, 1998, p. 59)
c)
e)
12
The chiral vector is therefore represented mathematically by the vector equation:
C = na1 + ma2
or (n,m) for short, where n and m are positive integers. Since a1 and a2 each traverse one
whole hexagon, the coordinates (n,m) represent atoms that are n and m hexagons away
from the reference atom in the a1 and a2 directions respectively. a1 points in the indicated
zigzag direction, 30° away from the armchair direction. If C lines up with the doted zig-
zag line in Figure 5, the resulting nanotube would be a zigzag CNT. The terms zigzag
and armchair come from the patterns traced along the hexagons along those directions, as
shown by the zigzag and arm-chair-like lines drawn in Figure 5. The angles θ and Φ al-
ways combine to form 30°. (Dresselhaus and Avouris, 2001, pp. 3-8)
A CNT can therefore be characterized by the notation (n,m) which refers to the chiral
vector. A (n,n) configuration will result in an armchair CNT. (n,0) and (0,m) configura-
tions will result in zigzag CNTs. The diameter dt of the CNT is defined by the equation:
ππhcc
tCnmnma
d =++
=)(3 22
Figure 5. Chiral vector for CNT characterization (adapted from Wildoer, 1998, p. 59)
(2)
(3)
13
where Ch is the length of the chiral vector C. acc is the carbon-to-carbon (C-C) bond-
length, or the length between consecutive carbon atoms (1.42Å). The chiral angle is de-
fined by:
( )⎥⎦⎤
⎢⎣
⎡
+= −
nmn
23tan 1θ
2. CNT Electrical Properties
a. Metallic and Semiconducting Conduction
Figure 6 shows the armchair, zigzag, and chiral tubes and their corresponding electrical
properties. The red lines for the armchair and zigzag tubes (Figures 6a and 6b respec-
tively) are drawn once again the corre-
spondence between tube naming and
atomic structure.
The chirality and diameter of a CNT is
extremely important, because they de-
termine the properties of the tube. In
electrical terms, chirality and diameter
determine whether the CNT will be-
have as a metal or a semiconductor. A
semiconductor is a material that has
electrical conductivity at room tem-
perature (68 to 77°F) that is higher
than an electric insulator, such as dia-
mond or glass, but lower than that of a
metal, such as aluminum, copper, and
silver. Semiconductors include sele-
nium, germanium, and others, but the
most widely used and well-known is silicon. Metals are often malleable, where as semi-
conductors are not. Yet the semiconducting CNT is malleable. According to McEuen et
al. (2002, p. 83), “metallic tubes have conductivities and current densities that meet or
Figure 6. Chirality of CNTs and their corresponding electrical conductivities (adapted from Weisman, 2004, p. 24)
c) Chiral (semiconducting, 0°< θ <30°)
a) Armchair (metallic θ = 30°)
b) Zigzag (semiconducting, θ = 0°)
(4)
14
exceed the best metals, and semiconducting tubes have mobilities and transconductances
that meet or exceed the best semiconductors.”
For metallic behavior, CNTs can have conductivity up to eight times higher than that of
copper, and can carry a current density achievable by any known conventional metallic
wire, making them potential candidates nanoscale wires (Appenzeller et al., 2002, p.
392). Armchair CNTs, with chiral angle of 30°, have been demonstrated experimentally
and theoretically to be metallic in conduction (see Figure 6a). Similarly, zigzag and
chiral tubes have been shown to be semiconducting given the right diameter (see Figures
6b and 6c).
b. Single and Multi-walled Nanotubes
The CNTs discussed so far are called a single-walled nanotubes (SWNT). They are sin-
gle tubes each made from a single graphene sheet. CNTs, however, can consist of multi-
ple tubes, resulting in what are called multi-walled nanotubes (MWNT).
The MWNT consists of more than one tube of differing diameters placed concentrically
like a set of nested Russian dolls (Collins and Avouris, 2000, p. 63), with spacing be-
tween consecutive tubes of 3.4 Angstroms (10^-10 m) (Dai, 2001, p. 218). Figure 7
shows three MWNTs also imaged by TEM (“N” indicates the number of tubes). In es-
sence what is shown is the cross-section of the MWNTs. Figure 7a shows a MWNT with
five tubes, Figure 7b shows one with two tubes (also called a double-walled nanotube, or
DWNT), and Figure 7c shows one with seven tubes. Since the SWNT can vary in con-
ductivity, so can each tube in a MWNT. It is therefore possible for a MWNT to consist
of alternating layers of metallic and semiconducting tubes.
The outermost tube of a MWNT has a typical diameter ranging from 10-20nm (Dai,
2001, pp. 218). The MWNT is more convenient for experimentation. The concentric
tubes of the MWNT are in general found to have poor electrical contact with each other.
(Ahlskog et al., 2001, pp. 337-8) Theoretical predictions as well as experimental studies
have shown that only the outermost nanotube in a MNWT contributes to conduction
(Wei, 2001, p. 1172).
15
Discovery of the carbon nanotubes (CNT) is regularly attributed to Sumio Iijima of the
NEC Fundamental Research Laboratory in Tsukuba, Japan, in 1991. What he first de-
scribed was actually a multi-walled nanotube (MWNT), as shown in Figure 7. Two years
later, he discovered the single-walled nanotube (SWNT).
The SWNT consists of a single CNT, typically on the order of 1.4nm in diameter. Figure
8 shows an image of an SWNT captured by TEM, once again showing the cross section
of the tube. Seen in the image are two dark lines corresponding to two sides of the nano-
tube wall. Both MWNT and SWNT have been experimented with in FETs and SETs.
4) CNT Non-Electrical Properties
SWNTs possess particular mechanical and thermal properties that result from “the hex-
agonal array of graphene, which is the densest possible packing of atoms in two dimen-
sions[. . .], together with the extraordinary strength of C-C sp2 bonds” (Colbert and
Smalley, 2002, pp. 6-7). The SWNT is about 100 times stronger than steel, yet one-sixth
the weight. Its hollow center and chicken-wire-like structure makes it very light, being
Figure 7. MWNTs (adapted from Dresselhaus, 2001, p. 2)
a) N = 5 b) N = 2 c) N = 7
16
1/6th the weight of copper, and about half the weight of aluminum. (Smalley, 2003) As
for thermal conduction, the CNT surpasses even that of diamond, reaching almost twice
as much (Hoelein, 2003, p. 664).
E. Transistors
1. Concepts and Uses
a) Basic Transistor Operation
A transistor is basically a regulator of electrical current. The region through which that
current flows is termed the channel of the transistor. The material used in the channel is a
semiconductor, usually silicon,. In electricity, potential energy is called the voltage. If
the voltage difference between the two ends of the channel were increased, more current
would flow through the channel. In the same way, current would decrease with a de-
crease in the voltage difference. Such a voltage difference can be applied by using two
metal contact pads placed in contact with each end of the channel. In transistor terminol-
ogy, the pads are called the source and the drain, where the source supplies the charged
carriers for current through the channel, and the drain receives the charged carriers. The
transistor comprises another component, called a gate, made of a metal, which has ulti-
mate control over the current flowing through the channel. Whatever channel current that
may otherwise be induced by the source-drain voltage difference is ultimately moderated
by the voltage induced at the gate. If no voltage at all is induced, all current is restricted
from flowing. Then, as more voltage is induced, the restriction on current is lessened.
The gate lies on top of the channel, with a piece of insulator (usually silicon dioxide) in-
Figure 8. SWNT (adapted from Zettl, 2003)
17
between the two. Three typical uses for the transistor are as a switching mechanism in
digital technology, an amplifier, and a sensor.
b) Digital Technology
The word digital refers to the fact that particular components of a device use distinct
states to perform computations and/or storage. For example, if a device consists of six
switches that can be switched on or off, the device can be used to store representations of
128 (26) numbers. These numbers can represent 128 degrees Fahrenheit of a thermome-
ter. Where as a mercury thermometer uses the continuous volumetric expansion and con-
traction of mercury to indicate temperature readings, a digital thermometer can use the
switching technique to store and display temperature readings. Similarly, for other appli-
cations, the number of switches used can be increased to increase the amount of available
representations.
Digital technology is therefore possible, if we can make devices with a mechanism for
switching between distinct states, and that would remain in one particular state until af-
fected by a signal at the input. It must also be possible to read the state of the device at
its output. Practically, it suffices to create a device that can store just two distinct states,
because the combination of several such devices can be used represent a greater number
of states. The transistor is in fact one such device. For example, the input may be the
current at the gate, and the state tracked by the transistor may be the presence of a current
in the channel. The presence and absence of a current in the channel can be easily de-
tected.
Thus far, no other switching devices have been invented that can compete with the tran-
sistor’s manufacturing economy and its suitability for large-scale integration. In other
words, if transistors had to be made one by one, and then connected to one another to
form digital devices, the cost and sizes of those devices would rise considerably, thus un-
dermining the transistor’s suitability. As it is, billions of transistors can be formed on a
single chip in a single cost-effective process called photolithography. The technology
behind photolithography will not be described here in detail, but the reader should note
that improvements in the photolithography technology have been responsible for the
18
steady decrease in the sizes of transistors over the past three decades. Nevertheless,
many industrial analysts are perceiving an end to transistor miniaturization through
photolithographic process improvements. As a result, active investigations into alterna-
tive technologies and materials have been on going for the purpose of prolonging the
trend of miniaturization.
c) Amplifier
In addition to serving as a switching mechanism, another direct application of the transis-
tor is as an amplifier. One significant example is the amplification of signals along
lengths of a telephone line. However, numerous other electrical devices require amplifi-
cation, such as components inside a radio, television, or cellular phone. The transistor
can amplify if a large voltage difference is maintained at the two ends of the channel.
Then, variations of a weak voltage at the gate can translate to variations of a large current
in the channel.
d) Sensor
Lastly, if the sensitivity of the transistor to changes in gate voltage is greatly enhanced, it
can also be useful in sensing applications. A single-electron transistor (SET) can be used
in such a way. Since a SET conducts electrons one at a time, its sensitivity to electrical
variations in the environment is extremely high.
2. Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs)
a. N-Type and P-Type Wafers
The MOSFET is the most widely used type of transistor, and comes in two types, n-type,
and p-type. All MOSFETs are formed on what is called a wafer, or a circular disc of
semiconducting material (most often silicon, as we will assume for our discussion) that
has variable thickness and diameter. Before any transistors are formed, the wafer first
goes through a process called doping, where a certain amount of silicon atoms are re-
placed by atoms of another element, called impurities. Various techniques for doping are
possible, but it often consists of the introduction of impurities to the wafer in the form of
a vapor at high temperature. If the temperature is kept sufficiently high, and for suffi-
ciently long, the impurities will spread rather evenly throughout the wafer.
19
Prior to doping, the wafer consists of a network of silicon atoms electrically bonded to
four neighboring atoms. Bonding between two atoms occurs when each atom shares one
valence electron (recall that electrons orbit the nucleus of an atom, and electrons in the
outermost orbit are call valence electrons) with the other so that, in effect, each atom can
be considered as having an additional valence electron. Silicon has four valence elec-
trons. If a silicon atom bonds with four neighboring atoms, it will in effect have a total of
eight valence electrons, four of its own, and four from the neighboring atoms. Since an
atom is most stable when it has exactly eight valence electrons, silicon atoms attempt to
bond with exactly four neighboring atoms.
If a silicon wafer is doped with impurities that have 5 valence electrons, the impurities
will introduce extra electrons to conduct electricity throughout the wafer, creating what is
called an n-type wafer. When an impurity atom of 5 valence electrons replaces a silicon
atom during doping, the impurity atom will bond with the four neighboring atoms of the
replaced silicon atom, but it will have one electron left over that is free to move about
throughout the wafer to conduct electricity. If a wafer is doped with a large amount of
impurities, it will also have a large of amount of electrons that are available for electrical
conduction. Therefore the conductivity of a wafer can be adjusted by the amount of im-
purities it is doped with.
In contrast, doping a silicon wafer with an element of 3 valence electrons creates what is
called a p-type wafer. In a p-type wafer, when the impurity atom replaces a silicon atom,
it will only be able to bond with three of the neighboring atoms, while the fourth
neighboring atom will have one dangling valence electron. If an external force is applied
to the wafer, it is possible for the missing electron to be replaced by an electron from a
nearby bond. In other words, if atoms A and B are missing a bond, a voltage applied to
the wafer may cause the bond between nearby atoms C and D to break so that C and D
will contribute one electron to A and B. Atoms A and B are then bonded, where as the
missing bond has moved to atoms C and D. In like manner the missing bond can actually
move across the entire wafer. The missing electron for a bond is called a hole, and is
considered a positive charged particle because it is attracted by a negative voltage,
whereas the negative charged particle, the electron, is attracted by a positive voltage. The
20
hole, therefore, like the electron, can move about the wafer and conduct electricity. N-
type and p-type wafers make it possible for MOSFETs to be turned on by opposite volt-
ages
b. Basic MOSFET operation
MOSFETs are referred to by the type of wafer used. An n-type MOSFET conducts cur-
rent through the channel if a higher voltage is applied at the gate, and cuts off current at
lower voltage. A p-type MOSFET has the inverse operation where a lower voltage at the
gate conducts current through the channel, but a higher voltage cuts it off. The exact lev-
els of the high and low voltages for turning a MOSFET on and off depend on the specific
dimensions and component properties of the MOSFET.
3. Nanotube Transistor
a. CNT FET
A semiconducting nanotube can be used to create a transistor on top of a silicon wafer.
Figure 9 shows a simple nanotube transistor setup. If metal contact pads, or electrodes
(the yellow pads in the figure), are placed on each end of the nanotube (the red tube), one
can serve as the source, and the
other the drain of the transistor,
while the nanotube itself acts
as the channel. If voltage is
applied at the silicon wafer
(light blue bottommost region)
the intensity of that voltage can
control the electrical conduc-
tance of the nanotube by
changing the electron density
in the tube (McEuen, 2000, p.
32). The dark blue oxide serves as an electrical insulation between the gate and the nano-
tube to prevent current from flowing between the wafer and the source, drain, or nano-
tube. Nanotubes set up as in Figure 9 normally behave like p-type MOSFETs, possibly
because the metal electrodes and other chemicals in the environment generate holes dur-
Figure 9. Simple nanotube transistor setup (adapted from Hoenlein, 2003, p. 666)
nanotube molecule
source electrode
drain electrode
oxide
silicon wafer
21
ing the process of making the transistor. (McEuen, 2000, p. 31) Experiments by the Dai
group at Stanford University, however, have shown that changing the chemical environ-
ment of the nanotube can significantly affect the nanotube’s behavior and can make it
either n-type or p-type.
Figure 10 shows a sample electrical conductance graph of a p-type nanotube transistor set
up according to the aforementioned technique. At high voltages, beyond 5 volts, conduc-
tion is seen to be near zero: the device is off. Conduction begins to rise with decreasing
gate voltage until at about 2 volts, conduction nearly saturates: the device is on.
b. CNT SET
If the temperature of the nanotube is below average room temperature (68 to 77°F), the
average electrical conductance of the nanotube would decrease, as shown in the inset of
Figure 11. If the temperature decreases to a point where the thermal energy in the junc-
tions (points of contact) between the nanotube and the electrodes is less than the energy
needed for an electron to cross the junctions, an interesting phenomenon called Coulomb
oscillations begins. In Figure 11, the coulomb oscillations are the spiky blue graph near
zero conductance. The spikes correspond to the transport of one electron at a time
through the nanotube (Dai, 2002, p. 231). At temperatures that are a few degrees Kelvin
or sub-Kelvin (Roschier et al., 1999, p. 729), thermal energy is insufficient to help trans-
fer electrons from the source to the nanotube and from the nanotube to the drain, so that
electrons are blocked, a phenomenon called Coulomb blockade (Park et al., 2001). The
Figure 10. Conductance characteristic of a simple nanotube transistor
(adapted from McEuen, 2000, p. 31)
22
electrons entering or leaving the nanotube will then depend predominantly on the voltage
applied at the gate for a given bias (or for a fixed voltage difference between source and
drain). Coulomb oscillation is a condition in which a certain amount of voltage increase
is necessary before another electron can be conducted through the channel. The spikes
repeat at regular intervals. In fact, the voltage increase necessary for transporting another
electron is governed by equation (5):
gg C
eV =∆
where e is the charge of an electron, Cg refers the capacitance between the gate and the
nanotube (with insulator in-between), and ∆Vg is the gate voltage period for Coulomb
oscillations. Oscillatory behavior of nanotubes at sub-Kelvin temperatures is in fact the
most basic characteristic of an SET. According to Dai (2002, p. 231), “nanotubes are po-
tential candidates for high performance SETs.”
c. A Successful Carbon Nanotube Field-Effect-Transistor (CNFET)
For years FET operations using CNTs as channels have been demonstrated. Various re-
search groups have gradually improved techniques for enhancing CNFET operation as
well as to create designs that are physically more analogous to present-day MOSFET
(5)
Figure 11. Conductance versus temperature and Coulomb oscillations
(adapted from McEuen, 2000, p. 34)
23
technology in hopes that CNTs may eventually be used as a replacement material. A
plethora of nanotube FET experimental setups have been documented. They will not all
be presented. Rather, a successful implementation in 2002 by Wind et al. at the IBM
Watson Research Laboratory (WRL) is discussed here and is taken to be representative of
how closely a CNFET can be designed structurally compared to a MOSFET. The group
at WRL subsequently compared their device characteristics with state-of-the-art MOS-
FETs and found that their device still outperformed silicon counterparts. They further
indicate that their implementation left much room for optimization, therefore advocating
strongly for the potential of replacing silicon FETs by CNFETs.
The Appendix shows a computer model for the actual IBM transistor structure, magnified
one-hundred thousand times. The metallic gate is seen as the orange slab on top of the
dark blue layer of gate oxide. The gate oxide prevents current from flowing between the
gate and the rest of the transistor components. A voltage applied at the gate induces
charge density changes in the nanotube underneath. The nanotube, seen as the wired
black tube, lies directly underneath the gate oxide, and makes electrical contact with the
source and the drain, seen as the two yellow slabs. Another oxide, the light blue silicon
dioxide, rests underneath the nanotube, source, and drain. It is used to electrically isolate
the transistor from the conductive silicon wafer underneath. Notice that the silicon wafer
and silicon dioxide pair can function very similarly to the gate and gate oxide pair. If a
voltage is applied to the whole wafer, it could also act as a gate. However, if many tran-
sistors similar to that seen in the Appendix were deposited on top of the silicon wafer, a
voltage applied to the silicon wafer will control all transistors simultaneously. Using the
wafer as gate is therefore not useful for device comparisons since present-day transistors
use individually controlled top gates.
Fabrication of the IBM CNFET began with a p-type silicon wafer (the specific width and
diameter of the wafer used are not mentioned by Wind et al., although wafer thickness is
normally much greater than the thickness of the devices fabricated on the wafers). Figure
12 shows a cross-sectional schematic of the transistor split along the length of the nano-
tube. The fact that the wafer used was p-type is indicated in Figure 12 “p++ Si.” Over
the wafer was deposited a layer of silicon dioxide (SiO2) that, once again, served as both
24
electrical and thermal insulation for the transistor against the wafer. A solution of CNTs
was poured over the SiO2. The solution density was adjusted so that approximately one
CNT per 25 µm2 (10-6 meters squared) area would be deposited over the SiO2. The solu-
tion was then removed. (Such a nanotube deposition process was used because, due to
the extreme minuteness of nanotubes, we have no technology as of now to individually
position them in large quantities over a wafer) A technique called atomic force micros-
copy was then employed to detect the positions of nanotubes on the SiO2.
Subsequently, two electrically conducting titanium pads (electrodes), serving as the
source and the drain, were formed over the nanotube, separated from each other by ap-
proximately 200 to 300 nm. On top of
the nanotube, the source, and the drain
was laid another layer of electrical insula-
tion consisting of a mixture of SiH4 and
O2 referred to earlier as the gate oxide.
Finally, in the groove over the insulator
and between the source and the drain is
laid a layer of conductive material made
either from aluminum (Al) or titanium
(Ti) that is approximately 15 nm thick. The Appendix as well as Figure 12 both show
one individual transistor, whereas several similar transistors can be made on top of a sin-
gle silicon wafer. (Wind et al., 2002, pp. 3818-9)
The process used by Wind el al. was novel. All other implementations reported prior to
their approach either used the substrate as the gate, which meant that all transistors had to
be turned on and off at the same time, or created individual gates for each transistor but
left the nanotubes exposed to air, which led to deteriorated performance. Another disad-
vantage to prior implementations was the need to use high voltages to turn on the transis-
tors. Yet another was the inability to produce both n-type and p-type transistors. The
implementation by Wind et al. overcame these disadvantages and resulted in the best per-
forming CNFET up to that time.
Figure 12. Cross sectional diagram of IBM CNFET
(adapted from Wind et al., 2002, p. 3817)
25
More so than outperforming previous CNFETs, however, IBM wanted performance
comparisons with silicon FET. Since the IBM CNFET was very similar to the MOSFET
in structure and operation, the MOSFET was therefore the most relevant silicon FET type
for comparisons. In general, for the MOSFET, the source and drain are actually a part of
the silicon wafer, but more heavily doped to be highly conductive. The wafer itself is
doped just enough to exhibit n-type or p-type behavior, and act as the channel of the
MOSFET. A layer of oxide is laid over the transistor and insulates the top gate from the
channel, source, and drain. Wind et al. made comparisons of their device with leading
MOSFETs of comparable size and found that their device outperformed same scale state-
of-the-art MOSFETS in certain key performance aspects. “Thus,” say Wind et al.,
“[their] experimental results advocate strongly for CNTs as candidates for future
nanoelectronics technologies.”
In addition to Wind et al., other groups, such as Henlein et al. (2003, p. 3) have also
shown that “every single electrical attribute of the most advanced CNT devices is supe-
rior to the equivalent MOSFET.” The only exception is that the gate length needs to be
much larger for the CNFET. In other words, although CNFET have better performance,
they are as of now no smaller than what MOSFET technology is capable of producing.
Scaling will be a challenging topic for further research.
d. Sorting CNTs
Currently, in CNT synthesis, both metallic and semiconducting CNTs are produced si-
multaneously. For commercial applications of CNTs in electronics it is important to be
able to sort between metallic and semiconducting tubes. Some groups have attempted
with success. For example, in November of 2003, a team of scientist from DuPont Co.,
the University of Illinois at Urbana-Champaign, and the Massachusetts Institute of Tech-
nology explored a technique for sorting SWNTs by their diameters and electronic proper-
ties. They found in essence that a certain sequence of single-stranded DNA formed a
helical structure around individual SWNTs, and that the electrical properties of the DNA-
CNT hybrid depended on the SWNT diameter and chirality. They used a technique
called anion exchange, which will not be discussed here (the reader is referred to Zheng
et al., 2003), to filter out the hybrids. They confirmed that the earlier fractions contained
26
smaller diameter tubes that were metallic, and that later fractions contained larger diame-
ter tubes that were semiconducting. More sorting techniques such as these will likely be
explored in the future.
e. Nanotube Placement and Manipulation
For CNTs to be used in electronics, a method must exist for efficiently controlling the
placement and manipulation of massive amounts of CNTs. Although IBM’s WRL has
successfully demonstrated the repositioning of a single CNT as well as the shaping of it
like a string on a surface, their technique is still limited to the manipulation of one CNT
at a time. Regular micro or nanoelectronics, on the other hand, often consists of millions
of sub-devices. If an IC chip, for example, uses nanotubes as replacement material, bil-
lions of nanotubes would require accurate placement over the chip. The physical ma-
nipulation of nanotubes one at a time is inefficient, and not cost-effective enough over
current IC technology.
Attempts have been made to circumvent individual manipulation. Up until recently, elec-
trical measurements of CNTs and transistor experimentations have often been conducted
in one of two ways. One way is to first create the electrical contacts throughout the wa-
fer, and then disperse CNTs on the wafer in hopes that there is a finite probability for
CNTs to bridge some of the electrodes. When they do, electrical measurements can be
made and STM can be used to characterize the CNT structure. Sometimes bridging can
be assisted by the flow of a fluid or the application of a voltage between the contact elec-
trodes, yet the yield is still nevertheless low (Hoenlein, 2003, p. 3). The second tech-
nique, which was used for the IBM CNFET discussed earlier, consists of first spreading
large quantities of CNTs on a wafer. Imaging techniques such as TEM and STM can
then be used to find the location of CNTs with desired chirality and dimensions. Elec-
trodes and other nanoscale features can then be deposited on top of the CNT with the de-
sired properties. The yield for such a technique, however, is similarly low. (Avouris et
al. 1999, pp. 205-6)
27
f. Challenges
Major challenges still lie ahead for the CNT before it can become a replacement material
for nanoelectronic applications. Although CNTs exhibit good conduction characteristics,
that conduction is often times limited by the resistance between the CNT and electrodes.
One challenge is therefore to create a reproducible fabrication technique for very low re-
sistance electrical contacts. (Tsukagoshi et al., 2002, p. 107) Another challenge is the
control over the chirality of the CNTs grown. For example, we are still unable to grow
only tubes of a single chirality. We are now able to control the diameter of the tubes
grown by adjusting growth temperature and size of catalyst, yet in a batch of grown nano-
tubes we would still have both metallic and semiconducting tubes (Saito and Kataura,
2002, p. 213). Although sorting techniques continue to be explored, sorting implies that
tubes must be placed on wafers after growth, but patterning and positioning of tubes over
electronic device structures are still problematical. Perhaps the greatest challenge is the
current inability to reliably, rapidly, and reproducibly create complex nanotube arrays.
Before such hurdles are overcome, CNTs cannot be integrated into commercial fabrica-
tion processes as replacement material. (McEuen et al. 2002, p83)
VI. Conclusion
CNTs have been shown to behave as high-quality metals or semiconductors depending on
the chirality and diameter making it possible to use CNTs in transistors as well as for in-
terconnects. They have been demonstrated to be appropriate material for FET and SET
applications. CNTs have even been shown to be capable of doping, demonstrating n-type
and p-type behavior. Research for enhancing the CNT FET and SET properties and prac-
ticality are still on-going, and has made significant progress. A myriad hurdles lie in the
way of seeing CNTs used in commercial applications, yet they are being dealt with indi-
vidually and there appears to be no theoretical limit to the successful implementation of
CNTs in electronics.
Due to imaging capabilities on the nanoscale, as well as progress made in the growth of
CNTs, explosive advancements in the understanding of the CNT have occurred in the
short time since its first discovery. Currently, it is still difficult to control the chirality,
and therefore the conductivity, of the nanotube, thus preventing it from wide-spread de-
28
ployment in micro- or nanoelectronics. The CNT possesses extraordinary and unique
electrical, mechanical, chemical, thermal, and optical properties, holding great promise
for wide and varied applications. However, we need to improve the growth process so
that CNTs can be produced in large quantities reliably, rapidly, and reproducibly.
29
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