MIT Lincoln LaboratoryHPEC_2010-1PJG 9/15/2010 APPROVED FOR PUBLIC RELEASE – DISTRIBUTION IS UNLIMITED

A Prototype FPGA Tile for Subthreshold-Optimized CMOS

• Low power systems benefit from FPGAs– Improved energy efficiency/performance vs. microcontroller– Improved design via reconfigurability– Lower cost vs. ASIC

• State of the art low power FPGAs: 10s to 100s of mW

• Ultra-low power applications require 10s to 100s of µW– Wireless sensor networks– RFID– Digital hearing aids

• Ultra-low power budgets motivate extreme voltage scaling– Subthreshold supply voltages yield peak energy efficiency

Peter Grossmann, Miriam Leeser

This work is funded by the Lincoln Scholars Program, MIT Lincoln Laboratory. The Lincoln Laboratory portion of this work was sponsored by the United States Government under Air Force contract number FA8721-05-C-0002.  The opinions, interpretations, conclusions and recommendations are those of the authors and are not necessarily endorsed by the United States Government.

MIT Lincoln LaboratoryHPEC_2010-2PJG 9/15/2010 APPROVED FOR PUBLIC RELEASE – DISTRIBUTION IS UNLIMITED

Subthreshold vs. Superthreshold Circuits

T

DS

T

THGS

V

V

nV

VV

D eeL

WII 10 20 THGSD VV

L

WII

Hypothetical MOS I-V Curve

1E-12

1E-11

1E-10

1E-09

1E-08

1E-07

1E-06

1E-05

0.0001

0.001

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6

Gate-Source Voltage (V)

Dra

in C

urr

en

t (A

)

Subthreshold Superthreshold

Key Tradeoffs in Subthreshold Operation:

· High energy efficiency

· Large circuit delays

· High sensitivity to process variation

· Low sensitivity to transistor size

· High sensitivity to supply voltage

VTH

MIT Lincoln LaboratoryHPEC_2010-3PJG 9/15/2010 APPROVED FOR PUBLIC RELEASE – DISTRIBUTION IS UNLIMITED

Prototype Tile Architecture

• 2-input CLB

• 4 routing channels

• 32 programming bits

• Flexible I/O

ASEL[0]

AS

EL

[1]

ASEL[0]

BSEL[1]

BSEL[0]

BSEL[0]

CLB

B

A

Y

YSEL[0]

YSEL[1]

YSEL[2]

YSEL[3]

SRAM,Programming

Circuitry

24

Tile Boundary

MIT Lincoln LaboratoryHPEC_2010-4PJG 9/15/2010 APPROVED FOR PUBLIC RELEASE – DISTRIBUTION IS UNLIMITED

Prototype Tile Demonstration

• Functional verification of all tile components through implementation of serial adder

• Tile average power ≈ tens of nanowatts

• Enables useful circuits on sub-mW power budgets

• Implementation of 6x6 tile array on test chip currently in fabrication at Lincoln Laboratory

AB

0110

0 00 11 01 1

0110

0 00 11 01 1

0001

0 00 11 01 1

0111

0 00 11 01 1

0001

0 00 11 01 1

QD

QD

CIN

COUT

SUM

Serial Adder