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A Promising Semantics forRelaxed-Memory Concurrency
Jeehoon KangChung-Kil Hur
Seoul National University(Korea)
Ori LahavViktor VafeiadisDerek Dreyer
MPI-SWS(Germany)
May 2017Shonan Meeting
/28
A Message Passing Example:
No Data Race
D = 42
LOCK(L)
F = 1
UNLOCK(L)
while (1) {
LOCK(L)
f = F
UNLOCK(L)
if (f) break
}
d = D
Initially: D = F = 0
Finally: d = 42
2
/28
Sequentially Consistent Concurrency
D = 42
F = 1
while (1) {
f = F
if (f) break
}
d = D
Initially: D = F = 0
Finally: d = 42
3
/28
Relaxed-Memory Concurrency
D = 42
F = 1
while (1) {
f = F
if (f) break
}
d = D
Initially: D = F = 0
Finally: d = 42 or 0
F = 1
D = 42
HW out of order exec
4
/28
Release & Acquire
D = 42
F = 1
while (1) {
f = F
if (f) break
}
d = D
Initially: D = F = 0
Finally: d = 42
[rel]
[acq]
5
/28
Release & Acquire
D = 42
F = 1
while (1) {
f = F
if (f) break
}
d = D
Initially: D = F = 0
Finally: d = 42
[rel]
[acq]
Run as if in a single thread
5
/28
Release & Acquire with Tweak
D = 42
F = 1
f = F
if (f) {
d = D // d = 42?
}
D = 10
Initially: D = F = 0
[rel]
[acq]
6
/28
Concurrency Models
• Semantics of multi-threaded programs?
- Sequential consistency (SC): simple but expensive
• Relaxed memory model (C/C++, Java)
- Many consistency modes (cost vs. consistency tradeoff)
- Open problem: what is the “right” semantics?
7
/28
“Right” Concurrency Semantics?
Conflicting goals of compilers, hardware &programmers
• Compiler/hardware: validating optimizations(e.g. reordering, merging)
• Programmer: supporting reasoning principles(e.g. DRF theorem, program logic)
8
/28
“Right” Concurrency Semantics?
Conflicting goals of compilers, hardware &programmers
• Compiler/hardware: validating optimizations(e.g. reordering, merging)
• Programmer: supporting reasoning principles(e.g. DRF theorem, program logic)
Java memory model
8
/28
“Right” Concurrency Semantics?
Conflicting goals of compilers, hardware &programmers
• Compiler/hardware: validating optimizations(e.g. reordering, merging)
• Programmer: supporting reasoning principles(e.g. DRF theorem, program logic)
Java memory model
C/C++ memory model
8
/28
“Right” Concurrency Semantics?
Conflicting goals of compilers, hardware &programmers
• Compiler/hardware: validating optimizations(e.g. reordering, merging)
• Programmer: supporting reasoning principles(e.g. DRF theorem, program logic)
Java memory model
C/C++ memory model
8
/28
“Out-of-thin-air” problem (1/3)
Load-Buffering (LB)
a = XY = a
b = YX = 42
Thread 1 Thread 2
(allowed: a=b=42)
9
/28
“Out-of-thin-air” problem (1/3)
Load-Buffering (LB)
a = XY = a
b = YX = 42
Thread 1 Thread 2
(allowed: a=b=42)
Registers
9
/28
“Out-of-thin-air” problem (1/3)
Load-Buffering (LB)
a = XY = a
b = YX = 42
Thread 1 Thread 2
(allowed: a=b=42)
RegistersShared
Locations
9
/28
“Out-of-thin-air” problem (1/3)
Load-Buffering (LB)
a = XY = a
b = YX = 42
Thread 1 Thread 2
(allowed: a=b=42)
RegistersShared
Locations
C11Relaxed
9
/28
“Out-of-thin-air” problem (1/3)
Load-Buffering (LB)
a = XY = a
b = YX = 42
Thread 1 Thread 2
(allowed: a=b=42)
9
/28
“Out-of-thin-air” problem (1/3)
Load-Buffering (LB)
a = XY = a
b = YX = 42
Thread 1 Thread 2
(allowed: a=b=42)
X = 42b = Y
9
/28
“Out-of-thin-air” problem (1/3)
Load-Buffering (LB)
a = XY = a
b = YX = 42
Thread 1 Thread 2
(allowed: a=b=42)
X = 42b = Y
Read X,42
Write Y,42
Read Y,42
Write X,42
(X=Y=0)
(read-from)
(sequenced-before)
9
/28
“Out-of-thin-air” problem (1/3)
Load-Buffering (LB)
a = XY = a
b = YX = 42
Thread 1 Thread 2
(allowed: a=b=42)
X = 42b = Y
Read X,42
Write Y,42
Read Y,42
Write X,42
(X=Y=0)
(read-from)
(sequenced-before)
Justification is too loose!
9
/28
“Out-of-thin-air” problem (2/3)
Classical Out-of-thin-air (OOTA)
a = XY = a
b = YX = b
Thread 1 Thread 2
(forbidden: a=b=42)
10
/28
“Out-of-thin-air” problem (2/3)
Classical Out-of-thin-air (OOTA)
a = XY = a
b = YX = b
Thread 1 Thread 2
(forbidden: a=b=42)
Reasoning principles(e.g. invariant a=b=X=Y=0)
10
/28
“Out-of-thin-air” problem (2/3)
Classical Out-of-thin-air (OOTA)
a = XY = a
b = YX = b
Thread 1 Thread 2
(forbidden: a=b=42)
Reasoning principles(e.g. invariant a=b=X=Y=0)
Read X,42
Write Y,42
Read Y,42
Write X,42
(X=Y=0)
(read-from)
(sequenced-before)
10
/28
“Out-of-thin-air” problem (2/3)
Classical Out-of-thin-air (OOTA)
a = XY = a
b = YX = b
Thread 1 Thread 2
(forbidden: a=b=42)
Reasoning principles(e.g. invariant a=b=X=Y=0)
Read X,42
Write Y,42
Read Y,42
Write X,42
(X=Y=0)
(read-from)
(sequenced-before)
What does hardware do?
10
/28
“Out-of-thin-air” problem (3/3)
Tracking Syntactic Dependency?
11
a = XY = a
b = YX = 42
Thread 1 Thread 2
(a=b=42?)
a = XY = a
b = YX = b
Thread 1 Thread 2
(a=b=42?)
/28
“Out-of-thin-air” problem (3/3)
Tracking Syntactic Dependency?
11
a = XY = a
b = YX = 42
Thread 1 Thread 2
(a=b=42?)
a = XY = a
b = YX = b
Thread 1 Thread 2
(a=b=42?)
(dep)
/28
“Out-of-thin-air” problem (3/3)
Tracking Syntactic Dependency?
11
a = XY = a
b = YX = 42
Thread 1 Thread 2
(a=b=42?)
a = XY = a
b = YX = b
Thread 1 Thread 2
(a=b=42?)
(dep)
/28
“Out-of-thin-air” problem (3/3)
Tracking Syntactic Dependency?
12
a = XY = a
b = YX = b+42-b
Thread 1 Thread 2
(a=b=42?)
a = XY = a
b = YX = b
Thread 1 Thread 2
(a=b=42?)
(dep)
/28
“Out-of-thin-air” problem (3/3)
Tracking Syntactic Dependency?
12
a = XY = a
b = YX = b+42-b
Thread 1 Thread 2
(a=b=42?)
a = XY = a
b = YX = b
Thread 1 Thread 2
(a=b=42?)
(dep)
/28
“Out-of-thin-air” problem (3/3)
Tracking Syntactic Dependency?
12
a = XY = a
b = YX = b+42-b
Thread 1 Thread 2
(a=b=42?)
a = XY = a
b = YX = b
Thread 1 Thread 2
(a=b=42?)
(dep)
/28
“Out-of-thin-air” problem (3/3)
Tracking Syntactic Dependency?
12
a = XY = a
b = YX = b+42-b
Thread 1 Thread 2
(a=b=42?)
a = XY = a
b = YX = b
Thread 1 Thread 2
(a=b=42?)
(dep)
/28
“Out-of-thin-air” problem (3/3)
Tracking Syntactic Dependency?
12
a = XY = a
b = YX = b+42-b
Thread 1 Thread 2
(a=b=42?)
a = XY = a
b = YX = b
Thread 1 Thread 2
(a=b=42?)
(dep)
/28
Promising Semantics
• Solving the out-of-thin-air problem
• Supporting optimizations & reasoning principles
• Covering most C/C++ concurrency features
• Operational semantics w/o undefined behavior
• Most results are verified in Coq
http://sf.snu.ac.kr/promise-concurrency
13
/28
Key Idea 1: Messages & Views
• Memory: pool of messages (loc, val, timestamp)
• Per-thread view on the memory
14
Timestamp
Loc.
X
Y
0
0 37
85
42
42
/28
Thread 1
Key Idea 1: Messages & Views
• Memory: pool of messages (loc, val, timestamp)
• Per-thread view on the memory
14
Timestamp
Loc.
X
Y
0
0 37
85
42
42
/28
readable/writable
Thread 1
Key Idea 1: Messages & Views
• Memory: pool of messages (loc, val, timestamp)
• Per-thread view on the memory
14
Timestamp
Loc.
X
Y
0
0 37
85
42
42
/28
readable/writable
Thread 1 Thread 2
Key Idea 1: Messages & Views
• Memory: pool of messages (loc, val, timestamp)
• Per-thread view on the memory
14
Timestamp
Loc.
X
Y
0
0 37
85
42
42
/28
Example
Store Buffering
Y = 42 a = X
X = 42b = Y
Timestamp
Loc.
X
Y
0
0
(allowed: a=b=0)Thread 1 Thread 2
15
/28
Example
Store Buffering
Y = 42 a = X
X = 42b = Y
Timestamp
Loc.
X
Y
0
0
(allowed: a=b=0)Thread 1 Thread 2
b = Y X = 42reorderable
(x86/Power/ARM)
15
/28
Example
Store Buffering
Y = 42 a = X
X = 42b = Y
Timestamp
Loc.
X
Y
0
0 42
(allowed: a=b=0)Thread 1 Thread 2
b = Y X = 42reorderable
(x86/Power/ARM)
15
/28
Example
Store Buffering
Y = 42 a = X
X = 42b = Y
Timestamp
Loc.
X
Y
0
0
42
42
(allowed: a=b=0)Thread 1 Thread 2
b = Y X = 42reorderable
(x86/Power/ARM)
15
/28
Example
Store Buffering
Y = 42 a = X
X = 42b = Y
Timestamp
Loc.
X
Y
0
0
42
42
(allowed: a=b=0)Thread 1 Thread 2
b = Y X = 42reorderable
(x86/Power/ARM)
15
/28
Example
Store Buffering
Y = 42 a = X
X = 42b = Y
Timestamp
Loc.
X
Y
0
0
42
42
(allowed: a=b=0)Thread 1 Thread 2
b = Y X = 42reorderable
(x86/Power/ARM)
15
/28
Example
Load Buffering (LB)
a = XY = a
b = YX = 42
Timestamp
Loc.
X
Y
0
0
Thread 1 Thread 2 (allowed: a=b=42)
16
/28
Key Idea 2: Promises
• A thread can promise to write X=V in the future,after which other threads can read X=V.
• To avoid OOTA, the promising thread mustcertify that it can write X=V in isolation.
• Until all its promises are fulfilled, the thread can take certifiable steps only.
17
/28
Example
Load Buffering (LB)
a = XY = a
b = YX = 42
Timestamp
Loc.
X
Y
0
0
Thread 1 Thread 2 (allowed: a=b=42)
18
/28
Example
Load Buffering (LB)
42
a = XY = a
b = YX = 42
Timestamp
Loc.
X
Y
0
0
Thread 1 Thread 2 (allowed: a=b=42)
Thread 2’spromise
18
/28
Example
Load Buffering (LB)
42
a = XY = a
b = YX = 42
Timestamp
Loc.
X
Y
0
0
Thread 1 Thread 2 (allowed: a=b=42)
Thread 2’spromise
18
/28
Example
Certification
42
b = YX = 42
Timestamp
Loc.
X
Y
0
0
Thread 2
Thread 2’spromise
19
/28
Example
Certification
42
b = YX = 42
Timestamp
Loc.
X
Y
0
0
Thread 2
Thread 2’spromise
19
/28
Example
Certification
42
b = YX = 42
Timestamp
Loc.
X
Y
0
0
Thread 2
42
Thread 2’spromise
19
/28
Example
Certification
42
b = YX = 42
Timestamp
Loc.
X
Y
0
0
Thread 2
42
Thread 2’spromise
19
/28
Example
Load Buffering (LB)
42
a = XY = a
b = YX = 42
Timestamp
Loc.
X
Y
0
0
Thread 1 Thread 2
Thread 2’spromise
(allowed: a=b=42)
20
/28
Example
Load Buffering (LB)
42
a = XY = a
b = YX = 42
Timestamp
Loc.
X
Y
0
0
Thread 1 Thread 2
Thread 2’spromise
(allowed: a=b=42)
20
/28
Example
Load Buffering (LB)
42
a = XY = a
b = YX = 42
Timestamp
Loc.
X
Y
0
0 42
Thread 1 Thread 2
Thread 2’spromise
(allowed: a=b=42)
20
/28
Example
Load Buffering (LB)
42
a = XY = a
b = YX = 42
Timestamp
Loc.
X
Y
0
0 42
Thread 1 Thread 2
Thread 2’spromise
(allowed: a=b=42)
20
/28
Example
Load Buffering (LB)
42
a = XY = a
b = YX = 42
Timestamp
Loc.
X
Y
0
0
42
42
Thread 1 Thread 2
Thread 2’spromise
(allowed: a=b=42)
20
/28
Example
Load Buffering (LB)
42
a = XY = a
b = YX = 42
Timestamp
Loc.
X
Y
0
0
42
42
Thread 1 Thread 2
Thread 2’spromise
b = YX = b+42-b
(allowed: a=b=42)
20
/28
Example
Classical Out-of-thin-air (OOTA)
a = X Y = a
b = YX = b
Timestamp
Loc.
X
Y
0
0
Thread 1 Thread 2(forbidden: a=b=42)
21
/28
Example
Classical Out-of-thin-air (OOTA)
42
a = X Y = a
b = YX = b
Timestamp
Loc.
X
Y
0
0
Thread 1 Thread 2(forbidden: a=b=42)
Thread 2’spromise?
21
/28
Example
Classical Out-of-thin-air (OOTA)
42
a = X Y = a
b = YX = b
Timestamp
Loc.
X
Y
0
0
Thread 1 Thread 2(forbidden: a=b=42)
Thread 2’spromise?
21
/28
Example
Classical Out-of-thin-air (OOTA)
42
a = X Y = a
b = YX = b
Timestamp
Loc.
X
Y
0
0
Thread 1 Thread 2(forbidden: a=b=42)
Thread 2’spromise?
21
/28
The Message Passing Example
22
Timestamp
Loc.
D
F
Thread 1 Thread 2
D = 42
F = 1
while (1) {
f = F
if (f) break
}
d = D
0
0
/28
The Message Passing Example
22
Timestamp
Loc.
D
F
Thread 1 Thread 2
D = 42
F = 1
while (1) {
f = F
if (f) break
}
d = D
0
0
42
/28
The Message Passing Example
22
Timestamp
Loc.
D
F
Thread 1 Thread 2
D = 42
F = 1
while (1) {
f = F
if (f) break
}
d = D
0
0
42
1
/28
The Message Passing Example
22
Timestamp
Loc.
D
F
Thread 1 Thread 2
D = 42
F = 1
while (1) {
f = F
if (f) break
}
d = D
0
0
42
1
/28
The Message Passing Example
22
Timestamp
Loc.
D
F
Thread 1 Thread 2
D = 42
F = 1
while (1) {
f = F
if (f) break
}
d = D
0
0
42
1
d = 0
/28
Timestamp
Loc.
D
F
Release & Acquire
Thread 1 Thread 2
D = 42
F = 1
while (1) {
f = F
if (f) break
}
d = D
0
0
[rel] [acq]
23
/28
Timestamp
Loc.
D
F
Release & Acquire
Thread 1 Thread 2
D = 42
F = 1
while (1) {
f = F
if (f) break
}
d = D
0
0
42
[rel] [acq]
23
/28
Timestamp
Loc.
D
F
Release & Acquire
Thread 1 Thread 2
D = 42
F = 1
while (1) {
f = F
if (f) break
}
d = D
0
0 1
42
[rel] [acq]
23
/28
Timestamp
Loc.
D
F
Release & Acquire
Thread 1 Thread 2
D = 42
F = 1
while (1) {
f = F
if (f) break
}
d = D
0
0 released at1
42
[rel] [acq]
23
/28
Timestamp
Loc.
D
F
Release & Acquire
Thread 1 Thread 2
D = 42
F = 1
while (1) {
f = F
if (f) break
}
d = D
0
0 released at1
42
[rel] [acq]
23
/28
Timestamp
Loc.
D
F
Release & Acquire
Thread 1 Thread 2
D = 42
F = 1
while (1) {
f = F
if (f) break
}
d = D
0
0 released at1
42
[rel] [acq]
d = 42
23
/28
Release & Acquire with Tweak
D = 42
F = 1
f = F
if (f) {
d = D // d = 42?
}
D = 10
Initially: D = F = 0
[rel]
[acq]
24
/28
[acq]
[acq][acq]
[rel] [rel][rel]
Re-Certification is Necessary
• A thread must re-certify during the executionthat it can write all its promises in isolation.
W=1 if (W) Y=1else Z=1
if (X) Z=1
Thread 1 Thread 2
(forbidden: X=1)
if (Y && Z) X=1
Thread 3
25
/28
[acq]
[acq][acq]
[rel] [rel][rel]
Re-Certification is Necessary
• A thread must re-certify during the executionthat it can write all its promises in isolation.
W=1 if (W) Y=1else Z=1
if (X) Z=1
Thread 1 Thread 2
(forbidden: X=1)
if (Y && Z) X=1
Thread 3
Z=1 promised
25
/28
[acq]
[acq][acq]
[rel] [rel][rel]
Re-Certification is Necessary
• A thread must re-certify during the executionthat it can write all its promises in isolation.
W=1 if (W) Y=1else Z=1
if (X) Z=1
Thread 1 Thread 2
(forbidden: X=1)
if (Y && Z) X=1
Thread 3
Z=1 promised
Certified:T2 in isolation
25
/28
[acq]
[acq][acq]
[rel] [rel][rel]
Re-Certification is Necessary
• A thread must re-certify during the executionthat it can write all its promises in isolation.
W=1 if (W) Y=1else Z=1
if (X) Z=1
Thread 1 Thread 2
(forbidden: X=1)
if (Y && Z) X=1
Thread 3
Z=1 promised
Certified:T2 in isolation
25
/28
[acq]
[acq][acq]
[rel] [rel][rel]
Re-Certification is Necessary
• A thread must re-certify during the executionthat it can write all its promises in isolation.
W=1 if (W) Y=1else Z=1
if (X) Z=1
Thread 1 Thread 2
(forbidden: X=1)
if (Y && Z) X=1
Thread 3
Z=1 promised
Certified:T2 in isolation
25
/28
[acq]
[acq][acq]
[rel] [rel][rel]
Re-Certification is Necessary
• A thread must re-certify during the executionthat it can write all its promises in isolation.
W=1 if (W) Y=1else Z=1
if (X) Z=1
Thread 1 Thread 2
(forbidden: X=1)
if (Y && Z) X=1
Thread 3
Z=1 promised
Certified:T2 in isolation
25
/28
[acq]
[acq][acq]
[rel] [rel][rel]
Re-Certification is Necessary
• A thread must re-certify during the executionthat it can write all its promises in isolation.
W=1 if (W) Y=1else Z=1
if (X) Z=1
Thread 1 Thread 2
(forbidden: X=1)
if (Y && Z) X=1
Thread 3
Z=1 promised
Certified:T2 in isolation
25
/28
[acq]
[acq][acq]
[rel] [rel][rel]
Re-Certification is Necessary
• A thread must re-certify during the executionthat it can write all its promises in isolation.
W=1 if (W) Y=1else Z=1
if (X) Z=1
Thread 1 Thread 2
(forbidden: X=1)
if (Y && Z) X=1
Thread 3
Z=1 promised
Certified:T2 in isolation
Z=1 fulfilled
25
/28
[acq]
[acq][acq]
[rel] [rel][rel]
Re-Certification is Necessary
• A thread must re-certify during the executionthat it can write all its promises in isolation.
W=1 if (W) Y=1else Z=1
if (X) Z=1
Thread 1 Thread 2
(forbidden: X=1)
if (Y && Z) X=1
Thread 3
Z=1 promised
Certified:T2 in isolation
25
/28
[acq]
[acq][acq]
[rel] [rel][rel]
Re-Certification is Necessary
• A thread must re-certify during the executionthat it can write all its promises in isolation.
W=1 if (W) Y=1else Z=1
if (X) Z=1
Thread 1 Thread 2
(forbidden: X=1)
if (Y && Z) X=1
Thread 3
Z=1 promised
Certified:T2 in isolation
25
/28
[acq]
[acq][acq]
[rel] [rel][rel]
Re-Certification is Necessary
• A thread must re-certify during the executionthat it can write all its promises in isolation.
W=1 if (W) Y=1else Z=1
if (X) Z=1
Thread 1 Thread 2
(forbidden: X=1)
if (Y && Z) X=1
Thread 3
Z=1 promised
Certified:T2 in isolation
Re-certification:Failed!
Because X = 0
25
Example
Counter
26
Core 1 Core 2
r1 = fetch-add X
(forbidden: r1=1,r2=1)
r2 = fetch-add X
Timestamp
Loc.
X 0
Example
Counter
26
Core 1 Core 2
r1 = fetch-add X
(forbidden: r1=1,r2=1)
r2 = fetch-add X
Timestamp
Loc.
X 0 1
Example
Counter
26
Core 1 Core 2
r1 = fetch-add X
(forbidden: r1=1,r2=1)
r2 = fetch-add X
Timestamp
Loc.
X 0 1 2
/28
Example
Write-Read Coherence
X = 1a = X
X = 2b = X
(forbidden: a=2,b=1)Thread 1 Thread 2
27
/28
Example
Write-Read Coherence
X = 1a = X
X = 2b = X
(forbidden: a=2,b=1)Thread 1 Thread 2
27
/28
Example
Write-Read Coherence
X = 1a = X
X = 2b = X
(forbidden: a=2,b=1)Thread 1 Thread 2
27
/28
Example
Write-Read Coherence
X = 1a = X
X = 2b = X
(forbidden: a=2,b=1)Thread 1 Thread 2
27
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Example
Write-Read Coherence
X = 1a = X
X = 2b = X
(forbidden: a=2,b=1)Thread 1 Thread 2
27
/28
Example
Read-Write Coherence
X = 1X = 2
a = Xb = X
Thread 1 Thread 2 (forbidden: a=2,b=1)
28
/28
Example
Read-Write Coherence
X = 1X = 2
a = Xb = X
Thread 1 Thread 2 (forbidden: a=2,b=1)
28
/28
Example
Read-Write Coherence
X = 1X = 2
a = Xb = X
Thread 1 Thread 2 (forbidden: a=2,b=1)
28
/28
Example
Read-Write Coherence
X = 1X = 2
a = Xb = X
Thread 1 Thread 2 (forbidden: a=2,b=1)
28
/28
Example
Read-Write Coherence
X = 1X = 2
a = Xb = X
Thread 1 Thread 2 (forbidden: a=2,b=1)
28
/28
Results (1/2)
Compiler/HW Optimizations
• Operational semantics for C/C++ concurrency:plain/relaxed/release/acquire r/w/u/fence, SC fence
• Compiler optimizations(reordering, merge, dead load elim., …)
• Compilation to x86 & Power
29
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Results (2/2)
Reasoning Principles
• DRF-SC: Data Race Freedom ⇒ SC
- DRF-PromiseFree: DRF ⇒ semantics w/o promises
• Invariant-based logic:soundness of global invariant (e.g. a=b=X=Y=0)
• http://sf.snu.ac.kr/promise-concurrency
30
/28
Results (2/2)
Reasoning Principles
• DRF-SC: Data Race Freedom ⇒ SC
- DRF-PromiseFree: DRF ⇒ semantics w/o promises
• Invariant-based logic:soundness of global invariant (e.g. a=b=X=Y=0)
• http://sf.snu.ac.kr/promise-concurrency
30
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Future Work
• Supporting SC reads & writes(We found a flaw in C/C++11 on SC)
• Supporting consume reads
• Developing a rich program logic &Verifying fine-grained concurrent programs
31
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