A PRACTICAL IMPLEMENTATION OF THE ... - Stanford Universitypv974cq4358/... · Approved for the Stanford University Committee on Graduate Studies. Patricia J. Gumport, Vice Provost

A PRACTICAL IMPLEMENTATION OF THE

MODULATED WIDEBAND CONVERTER

COMPRESSIVE SENSING RECEIVER ARCHITECTURE

A DISSERTATION

SUBMITTED TO THE DEPARTMENT OF ELECTRICAL

ENGINEERING

AND THE COMMITTEE ON GRADUATE STUDIES

OF STANFORD UNIVERSITY

IN PARTIAL FULFILLMENT OF THE REQUIREMENTS

FOR THE DEGREE OF

DOCTOR OF PHILOSOPHY

Douglas Jay Kozak Adams

March 2016

http://creativecommons.org/licenses/by-nc/3.0/us/

This dissertation is online at: http://purl.stanford.edu/pv974cq4358

© 2016 by Douglas Jay Kozak Adams. All Rights Reserved.

Re-distributed by Stanford University under license with the author.

This work is licensed under a Creative Commons Attribution-Noncommercial 3.0 United States License.

ii



http://purl.stanford.edu/pv974cq4358

I certify that I have read this dissertation and that, in my opinion, it is fully adequatein scope and quality as a dissertation for the degree of Doctor of Philosophy.

Boris Murmann, Primary Adviser


Amin Arbabian


Thomas Lee

Approved for the Stanford University Committee on Graduate Studies.

Patricia J. Gumport, Vice Provost for Graduate Education

This signature page was generated electronically upon submission of this dissertation in electronic format. An original signed hard copy of the signature page is on file inUniversity Archives.

iii

© Copyright by Douglas Jay Kozak Adams 2016

All Rights Reserved

ii

I certify that I have read this dissertation and that, in my opinion, it

is fully adequate in scope and quality as a dissertation for the degree

of Doctor of Philosophy.

(Boris Murmann) Principal Adviser




(Thomas Lee)




(Amin Arbabian)

Approved for the Stanford University Committee on Graduate Studies

iii

Abstract

Cognitive radio systems promise to alleviate the shortage of wireless bandwidth by

sensing the entire spectrum and operating in the underutilized whitespace. Pro-

totypes based on the Modulated Wideband Converter (MWC) compressive sensing

architecture have demonstrated both fast spectrum sensing and receiver flexibility.

In this thesis, we demonstrate a MWC receiver capable of sensing four 1.4 MHz

channels between 0 and 900 MHz that is robust to interference and meets the LTE

specifications for both sensitivity and maximum allowable input power.

The MWC quickly determines the spectral content of the entire input band by

multiplying it with a spectrally diverse mixing signal which guarantees that every in-

put channel is represented in measurements taken at baseband. While these spectrally

diverse mixing signals are necessary for detection, they provide no blocker rejection,

provide a very large effective noise bandwidth, and thus represent the worst-case

mixing signal once the input spectrum is characterized. Therefore, in this thesis we

introduce a separation between the detection and reception modes of the MWC. Once

the detection mode establishes the signal and blocker band locations, we reconfigure

the receiver to directly target the desired signals while actively nulling a single strong

blocker.

In order to null a blocker band, we introduce two independent techniques. In the

first sequence-based technique, we develop an algorithm to modify targeted digital

mixing sequences so that they additionally null an undesired harmonic. In the second

iv

delay-based technique we generalize a technique for harmonic cancellation commonly

applied in power inverters. By finely controlling the relative delay between two par-

allel mixing paths, we are able cancel any single mixer harmonic in their sum, thus

preventing a strong blocker in the corresponding band from interfering with the base-

band measurements.

We design, build, and test an integrated mixer prototype that demonstrates these

two rejection techniques and allows us to compare the MWC receiver architecture

against recently published alternatives. Our prototype achieves 50.2 dB of sequence-

based rejection, 59.3 dB of delay-based rejection, and 62.8 dB of rejection when both

techniques are applied to the same blocker. Likewise, the mixer demonstrates a 64.8

dBm IIP2, a 14.3 dBm IIP3, and a 31.5 dB noise figure while consuming 26.6

mW of signal-path power per branch. These performance parameters are in line

with recently published harmonic rejection mixers. Additionally, when coupled to a

hypothetical LNA that provides 25 dB of gain, 2.5 dB of noise figure, and a -10 dBm

IIP3, we calculate a receiver sensitivity of -96.1 dBm and 10 dB of SNDR for up to

-25 dBm of input power for the MWC receiver.

We thus demonstrate that the MWC is competitive with traditional wideband

receivers, while its additional flexibility makes it particularly attractive for cognitive

radio systems.

v

Acknowledgments

There are so many people to thank and so many institutions to praise that it is

impossible to even enumerate them here. This thesis would not have been possible

without their combined support, guidance, and love.

I would like to thank Ericsson and Stanford’s initiative for Rethinking Analog

Design for the funding that they provided, and I would like to thank the TSMC

University Shuttle Program for the silicon area they provided.

I would like to thank the Montgomery County Magnet Programs, the Massachusetts

Institute of Technology, and Stanford University for providing environments in which

I flourished. These places are dear to me in the instruction they provided, but more-

so for the peers they introduced me to and the personal standards that they instilled

in me.

I would like to thank my advisor, professor Boris Murmann, for being absolutely

everything I have ever wanted in an academic advisor. You found a way to be helpful

without being overbearing, supportive without being demanding, and a consummate

professional in everything you do. The effort you put into your advising is incredibly

obvious and incredibly valued.

I would like to thank my friends for leading by example: Randy, for your enthusi-

asm and curiosity. Mike, for your perfectionism and attention to detail. Ilya for your

loyalty and support, and Jon for your perspective and inclusivity. I am absolutely a

better person for having known each of you and am honored to be considered your

vi

friend in return.

To Susan, whose unwavering love, kindness, and support makes me strive to be

the person you see in me. Thank you for looking so far beyond yourself, and thank

you for being there for everyone around you.

To my sister Catherine. Having someone I can talk to about anything, and whose

perspective is substantially different from my own is precious to me. Despite how far

apart we live I am glad we are as close as we are. In that I am truly lucky.

Finally, I would like to dedicate this thesis to my parents.

To my mom. You knew exactly how to motivate and challenge a precocious young

engineer. You provided a role model for what I could be and showed me exactly how

to get there.

To my dad. You gave me absolutely unconditional love, support, and approval.

You deeply touched everyone around you and we were absolutely the better for it.

You are far and away the best person I have ever known, and I hope someday to

follow in your footsteps.

vii

Contents

Abstract iv

Acknowledgments vi

1 Introduction 1

1.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.2 Cellular Telephony . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

1.3 Cognitive Radio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.4 Chapter Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2 Background 7

2.1 Compressive Sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.2 The Random Demodulator . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.3 The Modulated Wideband Converter . . . . . . . . . . . . . . . . . . . . 12

2.4 Compressive Sensing Radio Tradeoffs . . . . . . . . . . . . . . . . . . . . 17

3 System Design 19

3.1 System Assumptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.2 Detection vs. Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3.3 Detection in the MWC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

3.4 Orthogonal Matching Pursuit-Based Support Recovery . . . . . . . . . 30

viii

3.5 Design Targets for a Practical MWC . . . . . . . . . . . . . . . . . . . . 34

3.6 SHR Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

3.6.1 Sequence-Based Harmonic Rejection . . . . . . . . . . . . . . . . 38

3.6.2 Delay-Based Harmonic Rejection . . . . . . . . . . . . . . . . . . 49

3.6.3 Limits to SHR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

3.7 Sensitivity of the MWC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

3.7.1 Single-Branch Noise . . . . . . . . . . . . . . . . . . . . . . . . . . 58

3.7.2 Multi-Branch Noise . . . . . . . . . . . . . . . . . . . . . . . . . . 62

3.8 Maximum Input Power of the MWC . . . . . . . . . . . . . . . . . . . . 66

3.9 Link Budget Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

3.10 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

4 Circuit Design 72

4.1 Shift Register Data Storage . . . . . . . . . . . . . . . . . . . . . . . . . 72

4.2 Digital-to-Delay Converter . . . . . . . . . . . . . . . . . . . . . . . . . . 76

4.3 Mixer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

4.4 Active-RC Anti-Aliasing Filter . . . . . . . . . . . . . . . . . . . . . . . . 85

4.5 Clock and Control Considerations . . . . . . . . . . . . . . . . . . . . . . 92

4.6 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

5 Test Setup and Measurement Results 96

5.1 Test Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

5.2 Integrated Circuit Prototype . . . . . . . . . . . . . . . . . . . . . . . . . 99

5.3 Mixer Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

5.3.1 Single Harmonic Rejection Measurement . . . . . . . . . . . . . 100

5.3.2 Noise Figure Measurement . . . . . . . . . . . . . . . . . . . . . . 104

5.3.3 Nonlinearity Measurement . . . . . . . . . . . . . . . . . . . . . . 110

5.3.4 Comparison to the State of the Art . . . . . . . . . . . . . . . . 110

ix

5.4 The MWC as an LTE Receiver . . . . . . . . . . . . . . . . . . . . . . . 114

5.5 Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

5.6 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

6 Conclusions and Future Work 118

6.1 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

6.2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

Bibliography 122

x

List of Tables

3.1 Optimal values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

3.2 State of the art LNAs. *Entire receiver chain. . . . . . . . . . . . . . . 69

3.3 Assumed system parameters, and abbreviated justifications. Elabora-

tion to follow in Chapter 4. . . . . . . . . . . . . . . . . . . . . . . . . . . 70

4.1 Sizing for each delay cell. . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

4.2 Combined mixer and switch resistance nonlinearity coefficients. . . . . 83

4.3 Op-amp active device operating points. . . . . . . . . . . . . . . . . . . 87

4.4 Anti-aliasing filter component values. . . . . . . . . . . . . . . . . . . . . 91

4.5 Anti-aliasing filter nonlinearity coefficients. . . . . . . . . . . . . . . . . 92

5.1 Per-branch area, decoupling capacitance, and power draw. . . . . . . . 100

5.2 Per-branch area, decoupling capacitance, and power draw. . . . . . . . 102

5.3 Calculated mixer noise figure. . . . . . . . . . . . . . . . . . . . . . . . . 109

5.4 Average noise power summed across integration windows. . . . . . . . 109

5.5 Comparison of our mixer to recently published harmonic rejection mixers.112

xi

List of Figures

1.1 US radio frequency spectrum allocations from 300 MHz to 3 GHz.

Adapted from [1]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.2 The map is divided so as to have one tower in each cell. Non-adjacent

cells can re-use the same band. . . . . . . . . . . . . . . . . . . . . . . . 3

2.1 A general Random Demodulator architecture. . . . . . . . . . . . . . . 10

2.2 When implemented with an integrating low-pass filter Figure 2.1 can

be rearranged to this equivalent system above. . . . . . . . . . . . . . . 12

2.3 Multiple frequency bands are mixed to baseband according to the har-

monics of p(t). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.4 Frequency-domain behavior of a multi-band mixer. . . . . . . . . . . . 13

2.5 Schematic of the MWC architecture. . . . . . . . . . . . . . . . . . . . . 14

2.6 Frequency-domain behavior of the MWC. . . . . . . . . . . . . . . . . . 15

2.7 By removing the unsupported columns of C and rows of X we simplify

the recovery problem. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.1 Input signal structure. (a) depicts a single occupied band. (b) depicts

the entire spectrum with four occupied bands (blue) and one sinusoidal

blocker (red). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.2 Column amplitudes of a randomly generated C matrix. Every column

has appreciable amplitude. . . . . . . . . . . . . . . . . . . . . . . . . . . 24

xii

3.3 Spread-spectrum mixing signals yield high baseband noise. . . . . . . . 25

3.4 Spread-spectrum mixing signals mix both signal and blockers to base-

band. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

3.5 Targetted mixing signals reduce the baseband noise. . . . . . . . . . . . 26

3.6 Targetted mixing signals can drastically attenuate blocking signals. . 26

3.7 The number of times that the support is successfully determined in

5000 runs, and repeated for each SNR. . . . . . . . . . . . . . . . . . . . 29

3.8 The probability of recovering 3 out of 133 possible signal locations.

Measurements swept across various SNR levels and repetition counts. 33

3.9 The probability of recovering 4 out of 133 possible signal locations.

Measurements swept across various SNR levels and repetition counts. 34

3.10 The probability of recovering 4 out of 133 possible signal locations in

the presence of a single sinusoidal blocker 10 dB stronger than the signal. 35

3.11 The probability of recovering 4 out of 133 possible signal locations in

the presence of a single sinusoidal blocker, 40 dB stronger than the

signal, after modifying the mixing sequence to reject a known blocker.

Figure 3.10 does not modify the mixing matrix, and the support re-

covery probability suffers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

3.12 Allowable in-band blocker power for LTE receivers [2]. . . . . . . . . . 37

3.13 A row of F plotted in the complex plane. Each sy associated with a

blue vectors is set to 1, while each sy associated with a red vectors is

set to -1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

3.14 The ideal single-target mixing sequence is a sinusoid. The ideal single-

target, two-level digital mixing sequence is a quantized sinusoid . . . . 42

3.15 In the frequency domain both the ideal sinusoid and the quantized

sinusoid effectively target the desired harmonic. Quantization however

adds additional spurious harmonics. . . . . . . . . . . . . . . . . . . . . 43

xiii

3.16 The composite vector G plotted in the complex plane. . . . . . . . . . 44

3.17 The ideal multitarget mixing sequence is the sum of sinusoids. The

ideal multitarget, two-level digital mixing sequence is a quantized sum

of sinusoids . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

3.18 In the frequency domain both the ideal multitarget signal and two-level

digital signal effectively target the desired harmonics. Quantization

however adds additional spurious harmonic response. . . . . . . . . . . 45

3.19 Normalizing the relevant rows of F before combining them into G as

in Equation 3.27 drastically reduces the variation in desired harmonic

gain and improves overall SHR. . . . . . . . . . . . . . . . . . . . . . . . 46

3.20 Adjusting a small fraction of the zero-value sequence elements allows

us to null a specific harmonic without sacrificing gain for the desired

harmonics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

3.21 On a logarithmic scale it is clear that most background harmonics only

slightly attenuated, and that by toggling zero-value sequence elements

we achieve a much stronger null for an undesired harmonic. . . . . . . 48

3.22 Sorted Monte Carlo sequence parameters for four randomly selected

desired signal bands and one randomly selected blocker band. . . . . . 49

3.23 Harmonic attenuation according to Equation 3.35 for (a) k = 19 and

(b) k = 57. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

3.24 Sorted Monte Carlo parameters demonstrating attenuation of four de-

sired harmonics as a result of delay-based harmonic cancellation. . . . 52

3.25 Notch attenuation plotted against delay accuracy for cancellation fre-

quencies across the input band. . . . . . . . . . . . . . . . . . . . . . . . 54

3.26 Our implementation of the MWC adds a fifth branch and interposer

switches to enable online calibration. . . . . . . . . . . . . . . . . . . . . 55

xiv

3.27 Simulated SHR achieved through sequence-based harmonic rejection

plotted against RMS jitter. . . . . . . . . . . . . . . . . . . . . . . . . . . 57

3.28 Schematic of the MWC architecture. . . . . . . . . . . . . . . . . . . . . 59

3.29 Noise sources in the MWC. . . . . . . . . . . . . . . . . . . . . . . . . . . 59

3.30 Noise folding vs. ZVT Monte Carlo simulations. . . . . . . . . . . . . . 62

3.31 The multiband subsystem within a single MWC branch. . . . . . . . . 67

4.1 Our implementation of the MWC receiver. . . . . . . . . . . . . . . . . 73

4.2 D flip-flops. (a) depicts a standard-cell flip-flop. (b) depicts a true

single-phase clock flip-flop. . . . . . . . . . . . . . . . . . . . . . . . . . . 74

4.3 Shift register cell layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

4.4 A 16 register cell of the shift register. . . . . . . . . . . . . . . . . . . . . 75

4.5 Coarse-fine implementation of the DDC within each branch of the MWC. 77

4.6 Implementation of the fine DDC with 21 digitally controlled delay cells. 78

4.7 Extracted sweep of delay plotted against DDC code. . . . . . . . . . . 79

4.8 During a digital transition uncertainty in voltage translates to uncer-

tainty in time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

4.9 Simplified mixer structure displaying current-setting resistors, calibra-

tion switches, and mixer switches. . . . . . . . . . . . . . . . . . . . . . . 82

4.10 Simulated current plotted against input voltage. . . . . . . . . . . . . . 83

4.11 Simulated current plotted against input voltage. . . . . . . . . . . . . . 84

4.12 Anti-aliasing filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

4.13 Schematic of the op-amp within the anti-aliasing filter. . . . . . . . . . 87

4.14 Op-amp feedback loop transfer function: (a) gain (b) phase . . . . . . 89

4.15 Noise schematic for the anti-aliasing filter. . . . . . . . . . . . . . . . . . 90

4.16 DC sweep of the anti-aliasing filter. . . . . . . . . . . . . . . . . . . . . . 91

4.17 Clock multiplexer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

xv

4.18 Clock multiplexer output, fast enable, and slow enable. . . . . . . . . . 94

4.19 Clock-disable circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

4.20 Skipped clock pulse as a result of a clock-disable rising edge. . . . . . 94

5.1 Experimental test setup. . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

5.2 On-board common-mode bias generation. . . . . . . . . . . . . . . . . . 98

5.3 Annotated die photo. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

5.4 Sequence-based (a), delay-based (b), and combined (c) single-harmonic

rejection measurements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

5.5 SHR plotted against jitter for sequence-based, delay-based, and com-

bined SHR rejection techniques. We simulated 1.2 ps RMS jitter and

assume 2.2 ps based on the measurements. . . . . . . . . . . . . . . . . 103

5.6 Measured calibration tone power during a calibration sweep. . . . . . . 104

5.7 Setup to calibrate the noise factor of the spectrum analyzer. . . . . . . 105

5.8 Setup to measure noise factor of the combined DUT–spectrum analyzer

system. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

5.9 Three-block system from which we generalize Frii’s formula. . . . . . . 108

5.10 Test setups used for mixer noise factor measurement. . . . . . . . . . . 108

5.11 Noise averaging reduces the noise floor of the recovered bands relative

to the baseband samples. . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

5.12 IIP2 (a) and IIP3 (b) nonlinearity measurements. . . . . . . . . . . . 111

5.13 MWC reception demonstration. . . . . . . . . . . . . . . . . . . . . . . . 116

xvi

Chapter 1

Introduction

1.1 Motivation

With the advent of smartphones, the demand for ubiquitous high data-rate wire-

less communications has skyrocketed. Unfortunately, the bandwidth available for

traditional cellular telephony is limited by interference from other users. The FCC

maintains a licensing system to allocate individual bands to specific users and ser-

vices, but with the advent of smartphones the licensing program has been unable

to keep pace with demand. One possible solution is the introduction of cognitive

radios–whereby a user is able to opportunistically use available spectrum without

disturbing the incumbent license owner. In order for such a scheme to be practical, a

cognitive radio receiver must quickly identify incumbent signals, adjust its bandwidth

to operate within the available spectral vacancies, and aggregate multiple channels to

provide the total desired bandwidth. New radio architectures based on compressive

sensing show promise as potential cognitive radio receivers, but proof-of-concept im-

plementations have only recently been published. In this thesis, we seek to establish

the modulated wideband converter compressive sensing architecture as a practical re-

ceiver topology. We do so by demonstrating an integrated circuit prototype capable

1

CHAPTER 1. INTRODUCTION 2

of rejecting a single strong blocker while simultaneously receiving four signal bands

at sensitivities defined by the LTE specifications.

1.2 Cellular Telephony

For any communications channel, the Shannon-Hartley theorem states that the achiev-

able data rate trades off against both bandwidth and signal-to-noise ratio. Likewise,

receiver noise trades against power draw such that the power budget ultimately limits

the achievable signal-to-noise ratio. For battery operated mobile devices the power

budget is particularly limiting, and for practical purposes the data rate can be consid-

ered to trade directly against bandwidth. Unfortunately, wireless systems all share

the same channel, so the bandwidth occupied by one user reduces the bandwidth

available to everyone else.

For cell phones, each device shares the radio spectrum with a whole host of radio

applications in addition to every other nearby cell phone. The radio spectrum is

used for everything from weather forecasting and astronomy to satellite navigation

and HAM radio, which is why the FCC maintains a licensing system that covers

all frequencies between 6 kHz and 300 GHz. An overview of spectrum allocations

between 300 MHz and 3 GHz (which covers most cellular bands) is provided in

Figure 1.1. Cellular telephones are allowed to operate on only a fraction of these

bands and unless the FCC reallocates spectrum through license auctions, the total

available bandwidth available is fixed.

The cellular telephony system manages the limitation imposed by bandwidth shar-

ing by breaking the map into cells, as depicted in Figure 1.2. The transmitting towers

and mobile devices within each cell are only powerful enough to interfere with the

adjacent cells. Therefore, non-adjacent cells are able to re-use the same bandwidth.

In order to accommodate higher per-device data rates, cellphone providers have


Figure 1.1: US radio frequency spectrum allocations from 300 MHz to 3 GHz.Adapted from [1].

0.9

1

1.1

1.2

1.3

1.4

1.5

1.6

1.7

1.8

Figure 1.2: The map is divided so as to have one tower in each cell. Non-adjacentcells can re-use the same band.


continually reduced the size of the cells. As the cell size decreases the number of users

per cell also decreases and the bandwidth available to each user increases as a result

[3]. Unfortunately, as the per-user demand approaches the total available bandwidth,

decreasing cell size no longer provides additional per-user bandwidth, and the cost of

installing additional base stations is no longer economically viable. A new paradigm

that transcends the license restrictions and increases the total available bandwidth is

required.

1.3 Cognitive Radio

Although the spectrum blocks allocated to cell phones are efficiently allocated, the

spectrum in other blocks is generally underutilized. A recent spectrum survey in

Europe demonstrated that although the average spectrum utilization of the GSM 900

band in Paris is above 45%, the overall spectrum utilization from 400 MHz to 3 GHz

is only 10.7% [4]. Likewise, another study demonstrated that in the fifty largest cities

in the United States an average of twenty channels are vacant in the highly desirable

VHF and UHF broadcast television bands [5]. Smartphones are particularly prone

to oversubscribing the wireless channel; at a sporting event where many fans wish to

upload the same highlight video, or in a meeting where everyone needs to download

the same presentation it can be impossible to meet the demand for data with the

available spectrum.

Cognitive radio offers a promising solution to the problem of spectrum scarcity

[6]. Cognitive radios are designed to be aware of the conditions they operate within—

the availability of both licensed spectrum and spectrum licensed to other operators.

By opportunistically operating on unlicensed vacant spectrum, cognitive radios can

greatly increase the spectrum allocation efficiency—thus solving the perceived spec-

trum shortage without interfering with incumbent licenses.


In a cognitive radio architecture flexibility is the paramount design goal. The

primary focus to-date has been the increase in digitally-controlled tuning range so

that a single receiver can cover multiple bands. As wideband receivers must account

for interference across their entire input range and large out-of-band blockers can

overwhelm the backend receive electronics, recent research has sought to increase the

viability and tuning range of digitally controlled filters. One method, demonstrated

in [7], achieves flexible pre-filtering with a bank of parallel analog filters that can be

adaptively combined cover many blocker scenarios. N-Path filtering, another method

demonstrated in [8], uses switches and capacitors to effectively up-modulate low-pass

filters making them behave like bandpass filters. By adjusting the switching frequency

the filter location can be swept over a wide range. Another method, demonstrated

in [9], does away with the pre-filter and achieves blocker rejection in a mixer-first

implementation by digitally controlling the matching parameter s11. Indeed, N-Path

filtering and mixer-first architectures can be combined, as in [10], to great effect.

A radio can be flexible in more than its frequency range. By aggregating band-

width from different channels a receiver can increase its throughput beyond that which

can be achieved in a single channel. Likewise, variable bandwidth allows a receiver

to more optimally utilize spectral vacancies of different sizes.

The Modulated Wideband Converter (MWC) compressive sensing receiver ar-

chitecture, as first described in [11], can operate over a wide bandwidth, provides

arbitrary carrier aggregation, and can dynamically adjust its per-channel bandwidth.

It therefore represents an incredibly promising cognitive radio receiver architecture,

however no known previous work has addressed the blocker problem.


1.4 Chapter Organization

This thesis is organized as follows: Chapter 2 provides background on a selection

of compressive sensing architectures, and a discussion of the architecture tradeoffs

and prior work. Chapter 3 follows the system-level design of the MWC, developing

practical architecture improvements, performance metrics, and design targets. Chap-

ter 4 describes our integrated prototype and details the design of key circuit blocks.

Chapter 5 provides measurement results, and Chapter 6 concludes this thesis with a

short summary and a discussion of future research.

Chapter 2

Background

In this chapter, we provide a brief introduction to compressive sensing and describe

its application in high-frequency circuitry through two topologies—the random de-

modulator (RD) and the modulated wideband converter (MWC). We explain the

operating principles and provide examples of prior work for both. We conclude with

a short discussion of the relative merits of the two topologies within the wireless

communication application space.

2.1 Compressive Sensing

There are infinitely many input signals that can describe any discrete set of samples.

Sampling theory is the application of assumptions that limit that infinite set to a single

unique solution. Traditionally, sampling is based on the Shannon-Nyquist theorem,

which provides a unique solution to describe the samples if the input signal contains

no frequency component above half the sampling rate.

Shannon-Nyquist is far and away the most common assumption used guarantee a

unique solution interpolated between a set of samples, but other assumptions exist.

Compressive sensing is the study of further assumptions that reduce the sampling

7

CHAPTER 2. BACKGROUND 8

requirements while still guaranteeing a unique solution. These assumptions are ex-

pressed as a sparsity requirement, where some large subset of the parameters that

describe the system are assumed to be zero.

Compressive sensing is a general technique that has been used across a wide range

of applications. By assuming sparsity in the dynamic range of an image it is possible

to reconstruct an image from far fewer measurements than there are pixels present

in the image [12]. By assuming sparsity in the parameters that describe the shape of

a measured signal it is possible to reconstruct MRI [13], radar [14], ultrasound [15],

or EEG [16] signals from samples taken below the Nyquist rate. And by assuming

sparsity in the nonlinear coefficients present in a system, it is possible to characterize

that system without necessitating measurements of the output at the Nyquist rate

[17].

In order to apply compressive sensing to cognitive radio applications, we assume

sparsity in the frequency domain. We more explicitly detail the assumptions specific

to this work in Section 3.1. There are two common compressive sensing architectures

that are well adapted to leverage frequency-domain sparsity to achieve general pur-

pose RF reception—the Random Demodulator and the Modulated Wideband Con-

verter. However, small differences in the structural assumptions and implementation

details make the MWC more suited to general purpose reception. In order to demon-

strate this, we overview the mathematics and implementation of both architectures.

2.2 The Random Demodulator

The Random Demodulator (RD), first presented in [18], provides a framework for

recovering signals with a known structure from low-rate samples taken at the infor-

mation rate. In this section we provide an overview of its operation following the

presentation in [19].


The RD is designed to recover signals x(t), that can be described by

x(t) =N

∑n=1

cnψn(t) (2.1)

for a set of known dictionary functions ψn and unknown weights cn.

As the dictionary functions are known a-priori, the coefficients cn contain the

entire information needed to recover the input. If we assume sparsity in cn, such

that most coefficients are expected to be zero, then the information rate is merely

the number of to-be-extracted coefficients divided by the period with which they

may occur. Traditional implementations of the RD use a single dictionary function

indexed with a time or frequency shift [14, 17, 18, 20].

The standard RD architecture is depicted in Figure 2.1. Here the mixing se-

quence p(t) is taken as a randomized Bernoulli sequence that updates at the Nyquist

frequency. The sampled output y[m] is thus given as

y[m] = ∫

∞

−∞x(τ)p(τ)h(t − τ)dt∣

t=mTs

(2.2)

= ∫

∞

−∞

N

∑n=1

cnψn(τ)p(τ)h(t − τ)dt∣t=mTs

(2.3)

=N

∑n=1

cn ∫∞

−∞ψn(τ)p(τ)h(t − τ)dt∣

t=mTs´¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¸¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¶

θm,n

.(2.4)


x(t)

p(t)

LPF:h(t)

t =mTS

y[m]

Figure 2.1: A general Random Demodulator architecture.

Rearranging Equation 2.4 yields the standard CS matrix form

⎡⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎣

y[1]

y[2]

⋮

y[M]

⎤⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎦

=

⎡⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎣

θ1,1 θ1,2 ⋯ θ1,N

θ2,1 θ2,2 ⋯ θ2,N

⋮ ⋮ ⋱ ⋮

θM,1 θM,2 ⋯ θM,N

⎤⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎦

⋅

⎡⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎣

c1

c2

c3

⋮

cN

⎤⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎦ ,

(2.5)

where unsupported coefficients in the vector c correspond to irrelevant columns in

the matrix Θ, and the number of measurements M is much fewer than the length of

the dictionary N .

The supported coefficients can be identified with l1 optimization [21], orthogonal

matching pursuit [22], convex relaxation [23], or other methods.

Unfortunately, the computational cost of populating Θ is prohibitively large due to

the convolution integral required for each element. In order to reduce computational

complexity we implement the low-pass filter with an integrator. Integration can be

subdivided in the time domain allowing us to rearrange the system depicted in Figure

2.1 to the mathematically equivalent system of Figure 2.2. The integration is split into

short periods that coincide with the period of the piecewise constant mixing signal

Tp. These short integrations are then accumulated digitally to produce an identical


result, shown below.

x[n] = xI(t)∣t=nTp = ∫t+Tp

tx(τ)dτ ∣

t=nTp

(2.6)

= ∫

t+Tp

t

N

∑n=1

cnψn(τ)dτ ∣t=nTp

(2.7)

=N

∑n=1

cn ∫t+Tp

tψn(τ)dτ ∣

t=nTp

(2.8)

= Ψ ⋅ c (2.9)

We note that Ψ in 2.9 can be pre-computed. Thus, the entire convolution operation

can be folded into the single matrix multiplication.

y = HPΨ²

Θ

⋅c, (2.10)

with

Θ =

⎡⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎣

1⋯1

1⋯1

1⋯1±

Ts/Tp ones

⎤⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎦

´¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¸¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¶Digital Accumulation

⎡⎢⎢⎢⎢⎢⎢⎢⎢⎣

p[1]

⋱

p[N]

⎤⎥⎥⎥⎥⎥⎥⎥⎥⎦

´¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¸¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¶Bernouli Sequence

⎡⎢⎢⎢⎢⎢⎢⎢⎢⎣

Ψ1(1) ⋯ ΨN(1)

⋮ ⋱ ⋮

Ψ1(N) ⋯ ΨN(N)

⎤⎥⎥⎥⎥⎥⎥⎥⎥⎦

´¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¸¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¶Pre-computed Integrals

.

(2.11)

Here Θ is composed of a digital accumulation matrix H, a piecewise mixing matrix

P, and sparsity inducing matrix Ψ, all of which are known a-priori and can be pre-

computed. The resulting system can be solved with standard CS approaches.

The RD has been applied to many real-world applications. A variation of the

RD is used to implement an ADC frontend in [20]. By limiting the input signals

to a multi-tone frequency-sparse model the device is able to greatly reduce both the

power consumption and sampling frequency beyond the state of the art. Similarly, [14]


x(t) ∫TN

xI(t)

t = nTN

x[n]

p(t)

∑TS/TN

y[m]

Figure 2.2: When implemented with an integrating low-pass filter Figure 2.1 can berearranged to this equivalent system above.

describes a variation of the RD implemented as a wideband radar pulse detector. By

leveraging the known signal structure of the reflected radar pulses, full reconstruction

is performed from samples taken 12.5 times below the Nyquist rate.

Even given the computation reduction provided by [24] and described above, there

remains a strong tradeoff in the RD between accuracy and computational complex-

ity. The dictionary functions ψn must be defined to fully describe every possible

input across a very large range, which demands a very large dictionary. In the ADC

frontend, the dictionary must contain a separate element for every possible input

frequency with fine resolution over a wide bandwidth. Likewise, in the radar pulse

detector the dictionary must contain a separate element for every possible pulse ar-

rival time with fine resolution over a long interval. For both of these applications

the required accuracy and range resulted in large matrices that precluded real-time

recovery.

2.3 The Modulated Wideband Converter

In this work we elaborate on the Modulated Wideband Converter, which was first

described in [25]. The MWC can be seen as a generalization of the RD in which the

CS matrix is directly implemented in hardware. Instead of assuming a dictionary-

based functional form the MWC assumes block sparsity in the frequency domain,


x(t)

p(t)

y[n]

Figure 2.3: Multiple frequency bands are mixed to baseband according to the har-monics of p(t).

X(jω):

P(jω):

Baseband

Y(ejΩ):

Σ

Figure 2.4: Frequency-domain behavior of a multi-band mixer.

which makes it well-suited to general purpose reception. Here we give an overview of

the topology and explain the mathematical underpinnings of its operation.

We build up the MWC architecture from a single multi-band mixer as depicted

in Figure 2.3. Every physically realizable periodic function can be described by its

Fourier series, which decomposes the periodic function into sinusoidal components.

Furthermore, the Fourier transform for a periodic function consists of an infinite series

of delta functions with amplitudes described by these same Fourier series coefficients

and separated by the repetition frequency of the periodic function. For an arbitrary

mixing signal p(t) with non-negligible Fourier coefficients the mixer effectively divides

the entire spectrum into equal-sized bands and produces a weighted superposition of

those bands at baseband, as shown in Figure 2.4.

For a single occupied band in a known location the multi-band mixing hardware


x(t)

p(1)(t)m = 1⋰m =M

y(1)[n]⋰y(M)[n]

Figure 2.5: Schematic of the MWC architecture.

can perfectly reconstruct the input from samples taken at a low rate. However, if

multiple signal bands are present in the input they will be superimposed at baseband,

and the samples taken at baseband will describe an underdetermined system. By

adding an additional hardware channel for each input band it is possible to make

multiple independent baseband measurements and recover the input. This is the

MWC architecture as depicted in Figure 2.5.

The frequency domain behavior of the MWC is depicted graphically in Figure 2.6

and given by

⎡⎢⎢⎢⎢⎢⎢⎢⎢⎣

Y (1) (ej−BW

2 )←→ Y (1) (ejBW2 )

⋮

Y (M) (ej−BW

2 )←→ Y (M) (ejBW2 )

⎤⎥⎥⎥⎥⎥⎥⎥⎥⎦

´¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¸¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¶Y

=

⎡⎢⎢⎢⎢⎢⎢⎢⎢⎣

c(1)1 ⋯ c

(1)N

⋮ ⋱ ⋮

c(M)1 ⋯ c

(M)N

⎤⎥⎥⎥⎥⎥⎥⎥⎥⎦

´¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¸¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¶C

⋅

⎡⎢⎢⎢⎢⎢⎢⎢⎢⎣

X (j (ω1 −BW

2))←→X (j (ω1 +

BW2

))

⋮

X (j (ωN −BW

2))←→X (j (ωN +

BW2

))

⎤⎥⎥⎥⎥⎥⎥⎥⎥⎦

´¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¸¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¶X

.

(2.12)

In Equation 2.12, the frequency of the nth row in X is offset by ωn so as to center the

spectrum on the nth mixing harmonic. Likewise, Y (m)(ejΩ) represents the baseband

measurements of branch m, and c(m)n is the Fourier coefficient corresponding to band

n within branch m.

For a block-sparse input spectrum with known support, numerous rows of X are


X(jω):

P(1)(jω):

P(2)(jω):

P(M)(jω):

Y(1)(ejΩ):

Y(2)(ejΩ):

Y(M)(ejΩ):

Baseband:ω1

c(1)1

c(2)1

c(M)1

ω2

c(1)2

c(2)2

c(M)2

ω3

c(1)3

c(2)3

c(M)3

ω4

c(1)4

c(2)4

c(M)4

ω5

c(1)5

c(2)5

c(M)5

ω6

c(1)6

c(2)6

c(M)6

ω7

c(1)7

c(2)7

c(M)7

ω8

c(1)8

c(2)8

c(M)8

Figure 2.6: Frequency-domain behavior of the MWC.

known to be identically zero. Thus Equation 2.12 can be simplified by trimming the

non-contributing rows of X and the associated columns of C as depicted in Figure

2.7. So long as the number of hardware branches is greater than the number of

contributing bands, the simplified system

Y = C′ ⋅X′ (2.13)

can be solved directly via matrix inversion.

In practice, it is possible to greatly simplify the hardware by implementing a single

mixing sequence and distinguishing each p(m)(t) with unique phase. For properly

selected phases it is possible to guarantee that after trimming C′ is invertible [11].

The above reconstruction presupposes knowledge of the occupied band locations,

which are determined through CS. Equation 2.12 is a direct example of the standard

CS matrix form, so standard techniques can be used to determine the band locations.

We have also assumed some character to the block sparsity of the input, [25] details

the minimum set of assumptions necessary for the MWC, and we elaborate on the

assumptions made in this work in Section 3.1.


0 0.5 11

2

3

4

5

2 4 6 81

2

3

4

5

1

2

3

4

5

6

7

8

9

0 0.5 11

2

3

4

5

2 41

2

3

4

5

0 0.5 11

2

3

4

Y =

=

X •

•

C ⇔

⇔

Y =

=

C′ •

•

X′

Figure 2.7: By removing the unsupported columns of C and rows of X we simplifythe recovery problem.

The MWC is a recent topology innovation and we are only aware of two prior

hardware implementations. In [26] the authors built a discrete implementation of the

MWC as an explicit proof-of-concept. The hardware validates the MWC architec-

ture by demonstrating AM, FM, and PAM reception. While [26] demonstrates the

utility of the MWC as a general purpose receiver it does so without making a proper

comparison to existing technology within the intended application space.

In [27], the authors demonstrate an integrated adaptation of the MWC architec-

ture. Their work effectively decouples the digital clock frequency of the MWC from

the Nyquist frequency of the input by adding an IF mixing stage, and very effectively

demonstrates the MWCs ability to detect the occupancy and sparsity of the input

spectrum in a very short time period. However, their work limits itself to a rapid

interferer detector and does not address the problems of general purpose reception;

in a cognitive radio both are required. In this work, we complete the picture and

demonstrate the ability of the MWC to function as a general-purpose receiver in a

practical use-case.


2.4 Compressive Sensing Radio Tradeoffs

Both the RD and MWC have promise in cognitive radio applications. The compressive

sensing core of both topologies enables simultaneous reception of multiple, widely-

separated input bands from samples taken well below the Nyquist frequency. However,

the MWC is much better adapted as a cognitive radio receiver because its sparsity

assumption directly matches the intended use case and because recovering the signal

has a much lower computational cost.

The MWCs assumption of block sparsity in the frequency domain directly applies

to underutilized radio frequency spectrum. As depicted in Figure 1.1, the FCC allo-

cates licenses that consist of spectrum blocks, and within those blocks license holders

traditionally divide the spectrum into sub-blocks temporarily allocated to each user.

Therefore, when a license is not acted upon, or when user demand falls, blocks of

spectrum are left void. The sparsity assumption in the MWC thus perfectly matches

the sparsity pattern seen by a practical cognitive radio.

The RD can also be adapted to receive block-sparse signals, but it requires a

separate dictionary element to describe every degree of freedom in the input signal.

For information-dense wireless signals transmitted over a wide possible bandwidth

the dictionary must be immense. Dictionary size determines the sizes of both c and

Θ in Equation 2.10, which in turn dictate the computational load necessary to decode

the input. As a result, no published RD architecture has been able to demonstrate

real-time reconstruction. Alternatively, reconstruction in the MWC requires only the

inversion and multiplication of a small matrix whose size is dictated by the support

of the input and can be easily computed in real time.

The MWC is well-suited to both fast spectrum sensing (as demonstrated in [27]),

and efficient general purpose reception (as demonstrated in [26]) over a wide input

bandwidth, and furthermore demonstrates additional degrees of flexibility desirous


to cognitive radio receivers. It is therefore an attractive topology. For these reasons,

we seek to improve the practicality of the MWC by providing resilience to a strong

blocker, as might be expected in a real-world use case.

Chapter 3

System Design

In this chapter, we define and design our MWC system. Our goal is to extend the

MWC from the mathematical framework presented in Section 2.3 to an explicit block-

level system description with specifications that we can use to motivate the circuit

designs presented in Chapter 4.

We begin by making a set of assumptions on the input signal to define the problem

and design space. Then we introduce a dichotomy in our MWC between detection and

reception modes, which enables improved noise performance and blocker rejection.

From there we discuss the mathematical underpinnings of compressive sensing as

they apply to the detection mode and explain why our system does not meet many

of the common assumptions. We therefore extend the orthogonal matching pursuit

algorithm to compensate, and demonstrate the efficacy of our detection algorithm

through simulation.

For the reception mode we motivate specifications for blocker rejection, sensitivity,

and allowable power analogous to those of LTE systems. We introduce two techniques,

sequence-based and delay-based, in order to achieve the desired blocker rejection, and

we develop equations that describe the noise and distortion in the MWC.

We conclude by back-calculating minimum specifications for the individual circuit

19

CHAPTER 3. SYSTEM DESIGN 20

blocks that, if met, enable a system that achieves the overall design targets.

3.1 System Assumptions

In this section, we establish the assumptions necessary for our MWC-based system.

We begin by asserting a set of constraints on the incident signal that reduce the

hardware requirements, the required back-end computation, or both. Then we specify

the signal sparsity and blocker characteristics for the MWC receiver.

A great deal of prior work has developed the MWC architecture for use as a flexible

radio receiver that is fully blind to the structure of the input signal [11, 25, 28]. Even

so, the most general implementation of the MWC still constrains the input spectrum

to a maximum number of continuous spectrum blocks, each of which is no wider than

the receiver-specific bandwidth. Under these constraints an arbitrarily located input

spectrum block may lie across the boundary between two adjacent reception bands,

requiring each band be treated independently and doubling the necessary receive

hardware. For our system, in order to simplify the demonstration hardware, we

require that the input spectrum blocks be centered within one of the reception bands.

This simplifying assumption comes at the cost of complete system and specification

agnosticism, but does not affect the frequency or bandwidth flexibility of the MWC,

which are its main strengths.

Within each signal band, we also limit input signals to lie within the upper side-

band (as depicted in Figure 3.1(a)). Upper and lower sidebands may be differenti-

ated by making an independent measurement for each, thus doubling the number of

branches in the MWC. This doubling closely parallels standard I/Q architectures that

also require twice the hardware to differentiate single sideband transmissions. Single-

sideband receivers are required for production systems that operate in dense spectral

environments, but are unnecessary for demonstrating our proof-of-concept prototype.


By foregoing the lower sideband, we double the number of signal bands that the

demonstration hardware can handle while reducing the usable spectrum per band by

a factor of two. Furthermore, by zeroing the lower sideband rather than providing a

mirrored conjugate signal we greatly simplify the necessary back-end computation.

Within the band, we dictate a signal modality for the received signal so that

the back-end DSP can work within an established framework. In this work, we

assume the transmitted signal to be a set of sinusoids at evenly-spaced frequencies.

As depicted in Figure 3.1(a), we assume four equally-spaced sinusoids within each

upper sideband. As detailed later, this imposed signal structure drastically simplifies

detection algorithm by condensing an infinite measurement vector (IMV) problem

to a finite, multiple measurement vector (MMV) problem. System blocks such as

the continuous-to-finite block [28] allow the MWC to operate without an assumed

signal structure, but are omitted here for simplicity. The chosen band structure is

appropriate in that it resembles that of orthogonal frequency domain multiplexing

(OFDM), which is heavily utilized in modern radio applications.

While the MWC is designed as a flexible receiver, it is not intended to support a

continually changing set of band locations. In a typical use-case a user might turn on

their receiver, run the detection algorithm to scan the available bands, and then begin

receiving data on the available bands. Therefore, we assume that the spectral support

is constant over the time window of interest and does not change mid-transmission.

Assuming constant spectral support allows the same hardware to make independent

subsequent measurements of the spectral support to improve detection accuracy [29].

Serializing the measurements used for spectral support detection greatly reduces the

total hardware requirements.

In this work, we note that the MWC receiver architecture is highly adept in

environments where the spectrum is blank except for the desired signal, but fares

poorly when a blocker is added. For this work we assume a single sinusoidal blocker


Band Center−BW/2 BW/2

(a) The signal structure of a single band with four equally spaced sinusoids withinthe upper sideband.

Frequency (MHz)700 900

(b) Representative input spectrum with desired signal in blue and a single blocker inred.

Figure 3.1: Input signal structure. (a) depicts a single occupied band. (b) depicts theentire spectrum with four occupied bands (blue) and one sinusoidal blocker (red).


as a practical use-case for the MWC receiver. As shown in [30], this is a practical

assumption for many receiver situations. For scenarios with numerous blockers spread

across the receive spectrum a different receiver topology is more appropriate.

As mentioned previously, the MWC requires an independent low-rate measure-

ment of the input signal for each occupied reception band. For this work we assume

no more than four occupied bands and one sinusoidal blocker, as depicted in Figure

3.1(b). More bands can be easily received with additional parallel hardware.

Finally, we require each branch of the MWC to implement an identical mixing

sequence subject to a branch-dependent delay τm. For identical mixing sequences the

hardware required to generate and store those mixing sequences can be reused across

branches drastically reducing the power requirements for many-branch implementa-

tions. Furthermore, it is demonstrated in [19] that since the delays affect each mixer

harmonic differently, the mixing matrix is Vandermonde and for non-degenerate cases

can be guaranteed invertible.

3.2 Detection vs. Reception

The MWC compressive sensing architecture is able to fully recover a sparse input X

from the underdetermined system Y = CX where Y is measured, X is K sparse, C

is known, and C obeys the restricted isometry property (RIP) of order 2K [21]. As

detailed previously, the recovery proceeds in two steps. First, the support of the input

X is determined. Then the unsupported columns of C and rows of X are removed,

reducing the system to a directly solvable matrix equation.

To date, all known literature has used the same matrix C for both the detection

step (where the spectral support is determined), and for the reception step (where the

signal content is extracted). However, these two steps do not share the same optimal

C, and by using a different C for each, the sensitivity and blocker tolerance of the


0 20 40 60 80 100 1200

0.01

0.02

0.03

0.04

Column Index of C

Co

lum

n M

agn

itu

de

Figure 3.2: Column amplitudes of a randomly generated C matrix. Every columnhas appreciable amplitude.

MWC can be drastically improved.

During detection, we choose C to maximize the probability that the true support

is recovered. This requires each column of C to have roughly equivalent magnitude.

To see this we consider the alternate scenario where one of the columns of C has

significantly below-average magnitude. In this case the baseband contribution of the

associated row of X is attenuated relative to every other row. If that attenuated

row is in the support of X then the signal-to-noise ratio of the measurements Y

falls, which has been shown to decrease the detection accuracy [22]. Therefore we

take the opposite approach. If we generate the elements of C randomly, the resulting

columns have appreciable amplitude with high probability [21], and no column will be

severely attenuated. An example set of randomly generated column magnitudes are

given in Figure 3.2. Unfortunately, the optimal mixing matrix during the detection

step represents the worst-case mixing matrix during the reception step as measured

in both a noise and blocker-rejection sense.

In order to understand why a spectrally diverse mixing matrix produces a receiver

with poor noise performance we refer to basic RF noise theory. A matched antenna

has a white input noise spectrum, so for a noiseless mixer, input noise from each band


No

ise

Po

wer

700 750 800 850 900

Har

mo

nic

Gai

n

Frequency (MHz)0 BW/2

No

ise

Mix

ed t

o B

aseb

and

Figure 3.3: Spread-spectrum mixing signals yield high baseband noise.

Sig

nal

+ B

lock

er

700 750 800 850 900

Har

mo

nic

Gai

n


Bas

eban

d S

ign

al M

easu

rem

ent

Figure 3.4: Spread-spectrum mixing signals mix both signal and blockers to baseband.

is mixed down to baseband where it adds constructively. Since each band is translated

to baseband with roughly equal gain, the noise power at baseband is very high (as

shown in Figure 3.3). Similarly, a spectrally diverse mixing matrix will faithfully

reproduce any blocking signal at baseband where it can overwhelm the desired signal

(as shown in Figure 3.4).

By separating the detection and reception steps it is possible to design a mixing

matrix where only the supported columns have appreciable magnitude. In this case

the bands that contribute signal are faithfully reproduced at baseband, while in-band


No

ise

Po

wer

700 750 800 850 900

Har

mo

nic

Gai

n


No

ise

Mix

ed t

o B

aseb

and

Figure 3.5: Targetted mixing signals reduce the baseband noise.

Sig

nal

+ B

lock

er

700 750 800 850 900

Har

mo

nic

Gai

n


Bas

eban

d S

ign

al M

easu

rem

ent

Figure 3.6: Targetted mixing signals can drastically attenuate blocking signals.

noise and blockers are attenuated (as shown in Figures 3.5 and 3.6 respectively). We

note that this distinction is only possible under the assumption that the spectral

support is constant over the time interval of interest. We leave the construction

details for a targeted mixing matrix to a later section.


3.3 Detection in the MWC

The MWC presented here is designed to recover the information in up to four signal

bands, with unknown band locations, from a small set of low-rate samples. To do

so we must first determine the location of those bands. This is the detection step of

the MWCs recovery algorithm. Using the assumptions given previously we cast the

problem as follows.

For the MWC we sample the down-mixed base-band signal in the time domain.

The samples y(m)[n], are indexed with m between 1 and M (in our implementation

we include the fifth calibration branch for detection so M = 5). The time-domain

measurements are transformed to frequency-domain measurements Y (m)(ejΩ) via the

fast Fourier transform. As stated previously, we assume that the frequency domain

representation of the input signal, X(jω), has the structure depicted in Fiugre 3.1.

Specifically, we assume that four of the N possible reception bands are populated

with sinusoids offset from the center of the band by respective frequencies iωof , with

i ∈ 1,2,3,4. For detection purposes we can therefore reshape the vectors X(jω)

and Y (m)(ejΩ) into two dimensional matrices Y ∈ CM×4 and X ∈ CN×4, and express

the entire system via the compact expression

Y = CX (3.1)

with C ∈ CM×N . Here we define Y mi to be the frequency-domain measurement

Y (m)(ejΩ)∣Ω=iωof , Xn,i to be the frequency domain input X(jω)∣ω=nBW+iωof , and C

to be a mixing matrix that is known a-priori. We note that the elements of each row

of X are all extracted from the same reception band, so that the columns of X have

identical support. By organizing the problem in this form we immediately see that

our system follows the form of a multiple-measurement vector (MMV) CS problem

[22].


While Equation 3.1 follows the form of an MMV CS problem, and numerous

solution algorithms have been demonstrated that can solve this system with high

probability [22], these solutions cannot be directly applied here because one of the

necessary assumptions is not met. Traditional solutions prove that the support can be

determined with high probability by leveraging the restricted isometry property (RIP)

of the mixing matrix. Here we present the traditional CS treatment, (as presented in

[19]) and discuss why it does not apply to my implementation of the MWC.

We begin by defining the isometry constant δK of matrix Φ as the smallest number

for which

(1 − δK)∥x∥22 ≤ ∥Φ ⋅ x∥2

2 ≤ (1 + δK)∥x∥22 (3.2)

holds for all K-sparse vectors x. If δK < 1 then Φ is said to possess the RIP of order

K. The measurements Y determine a provably unique solution to Y = ΦX for a K-

sparse input X, that furthermore can be solved in polynomial time, if Φ has the RIP

of order 2K. It is computationally infeasible to demonstrate the RIP for even small

matrices, but if the elements of Φ are generated randomly from a uniform, normal,

Bernoulli, or Rademacher distribution, and the condition

M ≥ cKlog(N/K) (3.3)

is met for some small distribution-dependent constant c, then Φ is RIP of order K

with p ≈ 1−e−M . It is simple to implement Φ with a Rademacher-based, time-domain

mixing sequence in hardware. We note that although there is a mismatch between

Φ, which has the RIP in the time domain, and X, which is sparse in the frequency

domain, generating the mixing matrix as the product C = ΦF, with F representing a

Fourier transform matrix, generally preserves the RIP.

For the MWC with M = 5, N = 133, and 4 signals, Equation 3.3 does not hold.

Notably, this does not prove that a matrix so constructed does not possess the RIP,


10 15 20 25 30 35 400

2

4

6

8

10

12

14

Signal to Noise Ratio (dB)

Su

cces

sfu

l Su

pp

ort

Det

ecti

on

/500

0 R

un

s

Figure 3.7: The number of times that the support is successfully determined in 5000runs, and repeated for each SNR.

and does not prove that reconstruction will fail, but rather removes the guarantee

that reconstruction will succeed with high probability. Experimentally, algorithms

designed to recover the support fail spectacularly for these system parameters, as

shown in Figure 3.7.

Reference [11] has solved this RIP problem by making multiple independent mea-

surements within a single hardware branch of the MWC. If multiple low-frequency

bands are digitized, the number of measurements (and associated rows in the mixing

matrix C) increases accordingly and it is possible to satisfy Equation 3.3 with min-

imal hardware [11]. However, the MWC as described in this work achieves blocker

rejection by measuring the downconverted input signal at baseband, thus limiting

each branch to a single band of measurements. The specifics of our blocker rejection

are detailed in section 5.3.1. It is therefore necessary to develop an algorithm that

is able to determine the correct spectral support for extremely non-square matrices

with high probability, even when those matrices do not have the RIP.


3.4 Orthogonal Matching Pursuit-Based Support

Recovery

One of the most successful algorithms for determining the support in a CS system

is Orthogonal Matching Pursuit (OMP), which was originally applied to single mea-

surement vectors [31], and extended to multiple measurement vectors [22]. Active

research has produced many algorithms that yield greater support recovery probabil-

ities (examples include ORMP [32], FOCUSS [33], CoSAMP [34] and AST [35]), but

OMP is the most commonly implemented due to its simplicity. In this section, we will

explain the OMP algorithm following its treatment in [22], and present improvements

that drastically improve the probability that it finds the correct spectrum support in

our implementation of the MWC.

OMP is a greedy, iterative, two-step process designed to solve the underdetermined

equation Y = AX under the assumption that X is sparse. At its simplest, the

algorithm begins by selecting the column ak1 of A that best explains the measurements

Y = Y0 and assumes that column to be in the support of X. Using a modified

Gram-Schmidt process, the component of Y0 best explained by ak1X is then removed

from Y0 to produce the residual measurements Y1. The column ak2 of A that best

explains Y1 is selected and the algorithm iterates. This process continues until the

remaining ∥Yp∥ is suitably small or a pre-specified number of columns have been

chosen. The explicit OMP algorithm follows, so that my proposed improvements

may be understood in context.

For the pth iteration of the OMP algorithm we find the column akp of A that

best explains the current residual Yp−1 by projecting Yp−1 onto each column vector

ak, k = 1,⋯, n in A, subtracting each projection from Yp−1 to generate an error

measurement vector Ep,k, and selecting the column akp that minimizes the Frobenius


norm of the error measurement. We have

Ep,k = (I −Pak)Yp−1 (3.4)

and

Pak=akaHk∥ak∥

, (3.5)

and the Frobenius norm of the error measurement can be simplified to

∥Ep,k∥2F = Tr(Ep,k

HEp,k) = Tr(Yp−1H(I −Pak

)Yp−1) = ∥Yp−1∥2F−Tr(Yp−1

HPakYp−1).

(3.6)

Here we note that ∥Yp−1∥2F is independent of the selected column, so minimizing the

norm of the error is identical to maximizing Tr(Yp−1HPak

Yp−1). The Frobenius

norm is used to simplify computation and calculation.

Once the column akp is selected, we compute

a(l)kp

= a(l−1)kp− qHl−1a

(l−1)kp

ql−1, l = 1, , p (3.7)

with

qp =a(p)kp

∥a(p)kp

∥, (3.8)

and the residual is calculated as

Yp = Yp−1 − qpqHp Yp−1 (3.9)

with the initializations a(0)kp

= akp and q0 = 0. In the above algorithm akp represents

the contribution to Yp that is not explained by the 1,⋯, p − 1 previously selected

columns.

As displayed in Figure 3.7, the OMP algorithm almost never successfully recovers


the support for the MWC system proposed in Section 3.3. In any underdetermined

system it is possible for a single column to be constructed from a linear superposition

of other columns. Thus, when running the OMP algorithm it is always possible that

an unsupported column better describes the measurements than the true support,

causing the detection algorithm to fail. As the dimension of the measurement vector

increases the probability of such an occurrence decreases exponentially, but conversely,

for a large number of low-dimension column vectors the probability can be very high.

Consider the simplified two-dimensional example where Y = [1 1]T

, A =

⎡⎢⎢⎢⎢⎢⎣

1 0 1

0 1 1

⎤⎥⎥⎥⎥⎥⎦

,

and X = [1 1 0]T

. In this case, the OMP algorithm will incorrectly estimate the

input as [0 0 1]T

because the third column of A perfectly explains the result Y

with higher sparsity than the true solution.

Previous work has used the assumption that the support is time-invariant to

repeat the measurement process and reduce the errors introduced by measurement

noise [29]. Here we introduce the idea of using repeated measurements to reduce the

errors caused by low-dimensionality measurements. To do so we use a new random

mixing matrix A for each repeated measurement. The OMP algorithm presented

above is extended so that for Q repeated measurements we select the column akp that

minimizes the total error given by

Q

∑q=1

∥Eq,p,k∥2F , (3.10)

where ∥Eq,p,k∥2F is the error for the kth column of the qth measurement of the pth

iteration. Yq,p is updated for each q as well. Simulation results for our repeated

measurement OMP algorithm are presented in Figures 3.8 and 3.9, where both figures

use five sets of concurrent measurements and attempt to recover the support of either

three or four bands respectively. The repeated measurement OMP algorithm reduces


10 15 20 25 30 35 400

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9


Pro

bab

ility

of

Co

rrec

t S

up

po

rt R

eco

very

1 Measurement3 Measurements5 Measurements7 Measurements9 Measurements11 Measurements13 Measurements15 Measurements17 Measurements

Figure 3.8: The probability of recovering 3 out of 133 possible signal locations. Mea-surements swept across various SNR levels and repetition counts.

to the standard MMV OMP algorithm for a single measurement set, which is displayed

in the bottom trace of both Figure 3.8 and Figure 3.9 for comparison.

Referring back to the previous example we intuit why repeating the measurements

improves performance. In the first set of measurements, the vectors X = [1 1 0]T

,

and X = [0 0 1]T

are both solutions to Y = AX, but for a new random A, only

X = [1 1 0]T

is guaranteed to remain a solution, while X = [0 0 1]T

is not likely

to do so. Thus, for the supported columns ∥Eq,p,k∥2F will always be low, whereas for

an unsuported column ∥Eq,p,k∥2F will only be low with some small probability.

Generating repeated measurement sets is preferable to measuring multiple bands

in each MWC branch because the detection algorithm can be made robust to block-

ers. Later in this thesis we introduce an algorithm whereby mixing sequences can

be modified to null the baseband contribution of a single band. Once a blocker is

identified, each mixing matrix in the detection mode can be modified to null that

blocker. Consider Figure 3.10 wherein a single sinusoidal blocker 10 dB stronger than

the signal is added, and the recovery probability drops precipitously. Alternatively,


10 15 20 25 30 35 400

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9


Pro

bab

ility

of

Co

rrec

t S

up

po

rt R

eco

very


Figure 3.9: The probability of recovering 4 out of 133 possible signal locations. Mea-surements swept across various SNR levels and repetition counts.

in Figure 3.11 a blocker 40 dB stronger than the signal is present, but it is identified

and nulled allowing detection to proceed normally. We see that the recovery prob-

abilities in Figure 3.11 (in the presence of a blocker), and Figure 3.9 (without), are

indistinguishable.

It is infeasible to null more than a single harmonic in our implementation, so a

nulled blocker will still be present at other low-frequency bands, and those architec-

tures that measure additional low-frequency bands cannot be made blocker insensitive

with this technique.

3.5 Design Targets for a Practical MWC

The MWC is a mathematically interesting receiver topology, but it must compete

against standard receiver topologies that have been refined over the past hundred

years. Unless it can perform on par with traditional topologies the flexibility advan-

tages of the MWC will not outweigh the performance costs.

The input specifications assumed for this work are therefore based on the LTE


10 15 20 25 30 35 400

1

2

3

4

5

6

7

8

9x 10

−3


Pro

babi

lity

of C

orre

ct S

uppo

rt R

ecov

ery


Figure 3.10: The probability of recovering 4 out of 133 possible signal locations inthe presence of a single sinusoidal blocker 10 dB stronger than the signal.

10 15 20 25 30 35 400

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9


Pro

bab

ility

of

Co

rrec

t S

up

po

rt R

eco

very


Figure 3.11: The probability of recovering 4 out of 133 possible signal locations in thepresence of a single sinusoidal blocker, 40 dB stronger than the signal, after modifyingthe mixing sequence to reject a known blocker. Figure 3.10 does not modify the mixingmatrix, and the support recovery probability suffers.


specifications [2]. We set the minimum reception bandwidth to 1.4 MHz, which

is the same as the minimum LTE bandwidth. Likewise, our receiver targets input

frequencies from 0 to 900 MHz, which include a dense set of LTE bands. In this

work we focus on three main performance metrics: sensitivity, distortion, and blocker

rejection.

The sensitivity measures the minimum detectable input signal power and is set by

the noise figure of the receive chain. For a 5 MHz bandwidth configuration they give

a reference sensitivity target of -100 dBm in the bands of interest [2]. We designed

our double-sideband system to receive four 1.4 MHz bands and give an aggregate

bandwidth of 5.6 MHz, so will use a similar -96.5 dBm sensitivity design target

(pro-rated to account for the noise penalty and bandwidth discrepancy).

At the other end of the power range, signal distortion limits the maximum input

power. The maximum input power for an LTE receiver is specified to be below -25

dBm, which we target as well. This input power is taken to include both desired

signals and in-band blockers. As an example, a -24 dBm blocker and -30 dBm signal

together constitute -25 dBm of total input power, and would fall within specification.

For LTE, the in-band blocking specification is given as a region of allowable blocker

power defined in relation to the single receive band. We depict one such region in Fig-

ure 3.12 [2] for a 1.4 MHz signal bandwidth. The blocker rejection specification does

not specify how many blockers may be present; in a crowded spectral environment

a specific band should be receivable so long as all blockers fall within specification.

However, this same specification should not be applied to the MWC. The cognitive

radio applications for which the MWC is intended inherently assume that the spec-

trum is underutilized and sparse. Instead of designing the MWC to concurrently

reject every possible blocker we introduce the single harmonic rejection (SHR) as a

more appropriate figure of merit to measure blocker attenuation.

We intend the SHR to measure the minimum baseband attenuation of a blocking


−11.7

−4.2−2.8

−0.7

0.7

2.8

4.2

11.7

Minimum SignalAllowable Blocker

−56 dBm

−44 dBm

−38 dBm

−97 dBm

Frequency Offset (MHz)

Figure 3.12: Allowable in-band blocker power for LTE receivers [2].

signal relative to the desired signal and so define it as the minimum ratio of signal-

band mixer gain to blocker-band mixer gain, and is given explicitly by

SHR =min(∣cd∣)

∣cb∣. (3.11)

Here we define c as the set of all mixer harmonics, index the set of desired signal

bands as cd, and index the mixing coefficient of a known blocker as cb. The SHR is

an extension of the harmonic rejection FOM used in mixers, which is the ratio of the

fundamental mixing tone to one of its harmonics.

3.6 SHR Systems

By distinguishing between detection and reception modes of the MWC the signal

and blocker locations determined in the detection mode can be used to optimize

performance in the reception mode. In this section we introduce two architecture

improvements to the mixer system that directly improve the SHR of the MWC. First,

we introduce a sequence design algorithm that effectively nulls an undesired harmonic


while maximizing the gain for desired frequency bands. Second, we introduce a delay-

based harmonic cancellation scheme that selectively nulls any undesired blocker band,

and finally we discuss the limits of harmonic rejection imposed by jitter and mismatch

in the system.

3.6.1 Sequence-Based Harmonic Rejection

In this subsection, we develop an algorithm that designs a targeted mixing sequence

to optimize SHR for use in the reception mode. Specifically, we design the sequence to

maximize the Fourier coefficients that correspond to known signal bands with respect

to the non-signal bands, and to actively null a single known blocker band.

We describe the mixing signal p(t) with a digitally sourced mixing sequence s, so

as to leverage the performance of modern CMOS processes. Thus, our mixing signal

is piecewise constant and updates to the next sequence value on the digital clock

transition.

The frequency fp of the digitally-described mixing sequence is given by

fp =fclkL, (3.12)

where L specifies the sequence length and fclk specifies the digital clock frequency.

The relation between the mixing sequence s = [s1, s2, . . . , sL]T and the Fourier series

coefficients c = [c1, c2, . . . , cN]T is set by a Fourier transform matrix F, such that

c = Fs. (3.13)

Here we see that the matrix element Fx,y represents the contribution of sequence

element sy to Fourier coefficient cx. The definition of the Fourier series transformation


is

cx =1

T ∫Ts(t)e−

2πTjxtdt (3.14)

and within a single clock period the mixing signal is constant with

s(t) = sy ∶y − 1

fclk< t ≤

y

fclk. (3.15)

Combining Equations 3.14 and 3.15 yields

cx = fpL

∑y=1∫

yfclk

y−1fclk

sye−2πjfpxtdt (3.16)

= s1 (fp∫

1fclk

0e−2πjfpxtdt) + s2 (fp∫

2fclk

1fclk

e−2πjfpxtdt) + ⋅ ⋅ ⋅ + sL (fp∫

Lfclk

L−1fclk

e−2πjfpxtdt)

(3.17)

= s1 (j

2πx[e

−2πjfpx1

fclk − 1])

´¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¸¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¶Fx,1

+s2 (j

2πx[e

−2πjfpx2

fclk − e−2πjfpx

1fclk ])

´¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¸¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¶Fx,2

+ sL (j

2πx[e

−2πjfpxLfclk − e

−2πjfpxL−1fclk ])

´¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¸¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¹¶Fx,L

(3.18)

= s1Fx,1 + s2Fx,2 + ⋅ ⋅ ⋅ + sLFx,L, (3.19)

and we see that cx is described by the dot product of the mixing sequence s and a set

of integrals that can be precomputed. We note that by combining multiple instances

of Equation 3.19 corresponding to the set of relevant Fourier coefficients we construct

Equation 3.13.

We choose the length of the mixing signal and the digital clock frequency to specify

the channel bandwidth and maximum input frequency of the receiver. We require

that the digital clock frequency be at least twice that of the highest input frequency


in order to ensure the frequency selectivity of the mixing sequence. To demonstrate

this necessity we consider both Fa,y and Fb,y where b = L − a. Fa,y and Fb,y are thus

described as

Fa,y =j

2πa(e−2πja y

L − e−2πja y−1L ) (3.20)

and

Fb,y =j

2π(L − a)(e−2πj(L−a) y

L − e−2πj(L−a) y−1L ) (3.21)

=j

2π(L − a)(e−2πjye2πja y

L − e−2πj(y−1)e2πja y−1L ) (3.22)

=a

L − a

j

2πa(e2πja y

L − e2πja y−1L ) (3.23)

=a

L − aF ∗a,y. (3.24)

As we see here, Fa,y and Fb,y have opposite phase and their magnitudes differ only

by a constant factor. Therefore, no matter the sequence selection, ∣ca∣ and ∣cb∣ will be

related by the same factor, and it will be impossible to adjust one of these Fourier

coefficients without having the other track the adjustment. This additional constraint

breaks the desired flexibility of the MWC, so we require fclk to be twice the highest

frequency of interest to prevent this.

We may implement additional bandwidth modes of the MWC without additional

hardware for highly divisible sequence lengths. By requiring the second half of the

mixing sequence to be identical to the first half we effectively halve the mixing period

and double the signal bandwidth. With similar requirements it is possible to achieve

tripling and quadrupling the signal bandwidth. In order to provide access to all these

bandwidth modes the sequence length must be divisible by two, three, and four.

Thus, in order to allow for 1.4 MHz input signal bands up to 900 MHz, as discussed

in Section 3.5, with the ability to increase the bandwidth to 2.8 MHz, 4.2 MHz, and

5.6 MHz, we set the sequence length and clock frequency to 1332 and 1.85 GHz


respectively.

Given the relationship between the mixing sequence and the Fourier coefficients

described in Equation 3.13. We develop an algorithm to determine an appropriate

mixing sequence given the locations of both the desired signal bands and unwanted

blocker bands. We begin with a simplified algorithm that targets a single mixer

harmonic, which we extend so as to target multiple harmonics simultaneously. From

there we introduce a multi-level mixing sequence and use the additional degree of

freedom that the additional level provides to null the blocker harmonic. Finally we

wrap up the subsection with Monte Carlo results that demonstrate the performance

consistency of our algorithm.

In order to target a specific mixer harmonic we refer once again to Equation 3.19.

Here we seek to maximize some ∣cx∣ and so choose each sy such that the complex

vectors described by sy ⋅ Fx,y add in an optimally constructive manner. Plotting Fx

in the complex plane, as in Figure 3.13, we see a set of equal-amplitude vectors with

uniformly distributed phase. In order to ensure they add constructively we set the sy

corresponding to blue Fx,y vectors to be 1 and set the sy corresponding to red Fx,y

vectors to -1. Given the inherent symmetry of the vectors described in Figure 3.13,

choosing s according to the sign of ReFx yields a provably optimal ∣cx∣.

The ideal single-target mixing signal is a sinusoid since it minimizes the baseband

contribution of non-signal frequency bands. Selecting according to a threshold ap-

plied to the complex vectors Fx,y (in this case the imaginary axis) is equivalent to

integrating the ideal mixing sinusoid and quantizing the result. Thus, the optimal

single-target mixing sequence is itself a quantized sinusoid as depicted in Figure 3.14.

Furthermore, in the frequency domain depiction presented in Figure 3.15 we see that

the desired harmonic is indeed present, and the combination of nonlinear quantization

and aliasing that results from sampling introduces additional mixing spurs.


−4

−3

−2

−1

0

1

2

3

4x 10

s

y Set to 1

sy Set to −1

Figure 3.13: A row of F plotted in the complex plane. Each sy associated with a bluevectors is set to 1, while each sy associated with a red vectors is set to -1.

Ideal SinusoidDigital Sequence

Figure 3.14: The ideal single-target mixing sequence is a sinusoid. The ideal single-target, two-level digital mixing sequence is a quantized sinusoid


Ideal SinusoidDigital Sequence

Figure 3.15: In the frequency domain both the ideal sinusoid and the quantized si-nusoid effectively target the desired harmonic. Quantization however adds additionalspurious harmonics.

For multiple target frequencies we produce a composite vector G according to

G = Fd1 + Fd2 + . . . , (3.25)

where each Fx represents a row of the F matrix and di indexes the desired Fourier

coefficients.

G is depicted graphically in the complex plane in Figure 3.16, and it is apparent

that unlike each Fx, its constituent vectors are not uniformly distributed in either

amplitude or phase. However, they are symmetric about the real axis and we can

still apply a similar thresholding technique to produce a maximal composite vector.

Here, maximizing s ⋅G produces the sequence that maximizes ∣cd1 ∣ + ∣cd2 ∣ + ∣cd3 ∣ + . . . .

Once again, in the time domain we see that the mixing signal is equivalent to a

quantization of a sum of sinusoids and in the frequency domain the desired harmonics

are targeted while the background is suppressed (Figure 3.17 and Figure 3.18). All

of the non-signal harmonics add noise to the system and are the result of nonlinear

quantization combined with time discretization.


−8

−6

−4

−2

0

2

4

6

8

x 10

s

y Set to 1

sy Set to −1

Figure 3.16: The composite vector G plotted in the complex plane.

Sum of SinusoidsDigital Sequence

Figure 3.17: The ideal multitarget mixing sequence is the sum of sinusoids. The idealmultitarget, two-level digital mixing sequence is a quantized sum of sinusoids


Digital SequenceSum of Sinusoids

Figure 3.18: In the frequency domain both the ideal multitarget signal and two-leveldigital signal effectively target the desired harmonics. Quantization however addsadditional spurious harmonic response.

We modify the above multi-target sequence generation algorithm by introducing

a third, zero-level sequence element specified according to

sy =

⎧⎪⎪⎪⎪⎪⎪⎨⎪⎪⎪⎪⎪⎪⎩

1 ReGy > T

0 T ≥ ReGy ≥ −T

−1 ReGy < −T.

(3.26)

Using a three-level mixing sequence reduces the quantization error relative to the

ideal mixing sequence and therefore reduces the noise added by spurious Fourier

coefficients. The optimum decision threshold T , chosen to minimize noise folding, is

dependent on the number of target bands. We discuss T selection in detail in Section

3.7.

The elements in each row of F possess different amplitudes and so direct summing

of the desired rows produces mixing sequences that show a preference for lower fre-

quency coefficients. Our goal is not to optimize the sum of the coefficient magnitudes,

but rather to maximize the SHR of the system, so we normalize the rows of F used

to generate G in order to improve the gain of higher frequency coefficients. Thus we


G= Fd1 + Fd2 + . . .

G= Fd1 ·∣∣∣ F1

Fd1

∣∣∣+ Fd2 ·∣∣∣ F1

Fd2

∣∣∣+ . . .

Figure 3.19: Normalizing the relevant rows of F before combining them into G as inEquation 3.27 drastically reduces the variation in desired harmonic gain and improvesoverall SHR.

update Equation 3.25 to

G = Fd1 ⋅ ∣F1

Fd1∣ + Fd2 ⋅ ∣

F1

Fd2∣ + . . . . (3.27)

In the frequency domain we see that the desired coefficients are much more uniform

in amplitude, and the SHR improves, as demonstrated in Figure 3.19.

Referring to Equation 3.26, we set to zero those sequence elements that cannot

strongly contribute to s ⋅ G. However, those same sequence elements can and do

contribute to all of the undesired Fourier coefficients. Therefore, these zero-value

sequence elements represent a new degree of freedom—toggling a subset of these

sequence elements enables us to null any specific harmonic without strongly impacting

the desired Fourier coefficients.

In choosing which zero-value sequence elements to toggle we implement the fol-

lowing greedy strategy. First, we project Fu,y for each of the zero-value sequence

elements set by Equation 3.26, onto the undesired mixer harmonic cu. Then we sort

those projections by absolute value and toggle the one that decreases ∣cu∣ the most.


Three−Level SequenceNulled Sequence

Nulled

Figure 3.20: Adjusting a small fraction of the zero-value sequence elements allows usto null a specific harmonic without sacrificing gain for the desired harmonics.

Due to the symmetry inherent to the F matrix the contribution sy ⋅ Fu,y is the com-

plex conjugate of the contribution sL−y ⋅ Fu,L−y, so that if we toggle sy we should

toggle sL−y as well. Likewise, due to symmetry, cu is guaranteed to lie along the real

axis. Therefore, in our sequence generation algorithm we iteratively adjust pairs of

zero-value sequence elements that minimize magnitude of the residual ∣cu∣. As the

adjusted zero-level sequence elements in each pair are complex conjugates, and cu is

guaranteed to lie on the real axis, the residual cu is also guaranteed to lie on the real

axis and the projections need not be recomputed nor resorted between iterations.

Comparing the mixing sequence before and after toggling the zero-level sequence

elements (depicted in Figure 3.20) we see that the desired harmonics are minimally

impacted, and the chosen harmonic is nulled.

We here note that Figures 3.15, 3.18, 3.19, and 3.20 are all depicted on linear axes.

This is done to more clearly illustrate the progression from a two-level, single-target

mixing sequence to our final three-level, multi-target mixing sequence. However,

doing so gives the false impression that the background harmonic gain is strongly

suppressed. Figure 3.21 therefore replots Figure 3.20 on a logarithmic scale. Here

we see that although most background harmonics are only 30 dB below the desired


−100

−80

−60

−40

−20

0


−100

−80

−60

−40

−20

0


Har

mon

ic P

ower

(dB

c)

Nulled

Har

mon

ic P

ower

(dB

c)

Nulled

Figure 3.21: On a logarithmic scale it is clear that most background harmonics onlyslightly attenuated, and that by toggling zero-value sequence elements we achieve amuch stronger null for an undesired harmonic.

signal harmonics, our nulled blocker harmonic is attenuated by 53 dB.

The performance of the algorithm presented above does depend on the specific

locations of both the signal and blocker bands. To demonstrate consistency of per-

formance we have run a Monte Carlo simulation and calculated the minimum ∣cd∣

and the SHR for each run. These sequence parameters, presented in Figure 3.22, are

sorted to more effectively present the distribution of each metric. As is apparent, the

minimum signal gain is reasonably constant across the simulations, and the estimated

SHR varies, but is above 50 dB for over 90% of the test cases.


0 10 20 30 40 50 60 70 80 90 100−20

−18

−16

−14

−12

−10

Min

imum

Des

ired

Har

mon

ic G

ain

(dB

)

Percentile

0 10 20 30 40 50 60 70 80 90 10030

40

50

60

70

80

90

SH

R (

dB)

|cd|: −13.9 dB

SHR: 63.8 dB

Median Values:

Figure 3.22: Sorted Monte Carlo sequence parameters for four randomly selecteddesired signal bands and one randomly selected blocker band.

3.6.2 Delay-Based Harmonic Rejection

In the previous subsection, we developed an algorithm that produces mixing sequences

that target specific desired harmonics and nulls a single harmonic corresponding to a

blocker band. In this subsection we develop a delay-based harmonic rejection tech-

nique that is independent of the mixing signal and can be dynamically adjusted so as

to null any single harmonic. Specifically, we generalize a technique known as harmonic

cancellation that is commonly used in power inverters [36].

An inverter is a common power system that converts DC voltages to AC wave-

forms. In the most common application a constant input is translated into a sinusoidal

output while minimizing the power used to make the conversion. Switching mixers are

used to produce an approximation of the desired sinusoidal output because an ideal

switch consumes no power. However, the switched waveform must be conditioned

by a passive filter network in order to acceptably approximate the intended output

sinusoid. By canceling the lowest harmonic in the output it is possible to reduce the

passive component values required in the output filter. In our RF switching mixer it


is not the lowest harmonic we wish to cancel, but rather that which corresponds to a

known blocker band.

Rejection is achieved as follows: For a delay τ applied to a periodic signal with

angular frequency ωp, the phase of the nth harmonic is rotated by nωpτ radians. Any

harmonic may be canceled by producing a delayed copy that rotates the undesired

harmonic by 180 degrees and then summing it with the original signal. Noting that a

phase rotation by any odd multiple of 180 degrees will produce the same cancellation,

for odd k, we have

nωpτ = kπ, (3.28)

which generalizes the required relationship.

Adding a delayed copy of the mixing sequence developed in Subsection 3.6.1 to

itself modifies the Fourier coefficients according to

c′x = cx (1 + e(−jxωpτ)) . (3.29)

The normalized harmonic attenuation is therefore given by

1

2∣c′xcx

∣ =1 + e(−jxωpτ)

2(3.30)

=∣1 + cos (xωpτ) − jsin (xωpτ)∣

2(3.31)

=

√

(1 + cos (xωpτ))2+ sin2 (xωpτ)

2(3.32)

=

√2 + 2cos (xωpτ)

2(3.33)

= ∣cos(xωpτ

2)∣ , (3.34)

and substituting τ chosen to cancel the nth harmonic according to Equation 3.28


500 525 550 575 6000

1

Subset of Input Bands (MHz)

Att

enu

atio

n

HarmonicAttenuation

k=19

Nulled

500 525 550 575 6000

1

Subset of Input Bands (MHz)

Att

enu

atio

n

HarmonicAttenuation

k=57

Nulled

Figure 3.23: Harmonic attenuation according to Equation 3.35 for (a) k = 19 and (b)k = 57.

yields:1

2∣c′xcx

∣ = ∣cos(πxk

2n)∣ . (3.35)

In so doing we produce attenuation that applies to all of the mixer harmonics accord-

ing to Equation 3.35 and is guaranteed to null the undesired nth mixer harmonic, as

demonstrated in Figure 3.23.

From Figure 3.23 we see that the undesired blocker harmonic is not the only

attenuated harmonic. We must choose k so as to avoid attenuating the desired mixer

harmonics as well. Unfortunately, while there is an infinite selection of odd values for


0 10 20 30 40 50 60 70 80 90 100−20

−18

−16

−14

−12

−10

Min

imum

Des

ired

Har

mon

ic G

ain

(dB

)

Percentile

: −13.35 dB : −13.73 dB : −14.07 dB : −14.48 dB

Median Values:max(|c

d|)

min(|cd|)

Figure 3.24: Sorted Monte Carlo parameters demonstrating attenuation of four de-sired harmonics as a result of delay-based harmonic cancellation.

k, they produce a finite selection of delays from which to choose. We see that

τ ≅ τ +2π

ωp(3.36)

≅kπ

nωp+

2π

ωp(3.37)

≅(k + 2n)π

nωp, (3.38)

which demonstrates that adding 2n to k yields an equivalent τ . Furthermore, there

can be only up to n2 unique values of k—k must be odd, and positive and negative

values of k are equivalent (there is no absolute time reference, so the delay is relative).

In our application of delay-based harmonic cancellation we implement an exhaus-

tive search of the choices for k to determine that which optimizes the overall SHR.

The achievable performance depends on the specific locations of both the signal and

blocker bands. We run Monte-Carlo simulations and measure the attenuation of the

desired harmonics to demonstrate consistency of performance across the input space.

These simulated parameters are presented in Figure 3.24.


Introducing an error ε to the delay in Equation 3.34 yields

1

2∣c′xcx

∣∣x=n

= ∣cos(nωp(τ + ε)

2)∣ (3.39)

=

RRRRRRRRRRRRRR

*0

cos(nωpτ

2)cos(

nωpε

2) −

*1

sin(nωpτ

2)sin(

nωpε

2)

RRRRRRRRRRRRRR

(3.40)

= ∣sin(nωpε

2)∣ , (3.41)

which allows us to determine the the shape of the filter null and the required accuracy

with which we must specify the delay. From Equation 3.41 we see that the width of

the filter null is dependent on the harmonic we wish to cancel, and so we illustrate

the notch attenuation for values across the input range in Figure 3.25. In order to

achieve 50 dB of cancellation across all frequency bands we require timing accuracy

within 0.56 ps.

Digital CMOS offers fine time-granularity, but, as discussed in Section 4.2, the

parameters that specify the absolute behavior depend on process variation (parasitic

capacitances and inverter drive strength) and on the implementation and test setup

(power supply consistency). In order to consistently achieve such fine delay specificity

we implement an online calibration scheme to measure and correct for uncertainties

and variations in the delay.

Calibration of any system parameter requires measurement (either direct or in-

direct) of that parameter and the ability to adjust that parameter. For the MWC

it is impractical to directly measure the mixing signal delays due to the minuscule

time resolution required, however a properly set delay will null an undesired mixer

harmonic, and that effect can be directly measured.

Our implementation of the MWC and its calibration scheme is depicted in Figure

3.26. Here we add an additional calibration branch and a set of switches which

we use to interpose the additional branch into the online MWC while the original


−3 −2 −1 0 1 2 3−80

−75

−70

−65

−60

−55

−50

−45

−40

−35

−30

Delay Error ε (ps)

Com

b F

ilter

Atte

nuat

ion

(dB

)

900 MHz Null

250 MHz Null

70 MHz Null

Figure 3.25: Notch attenuation plotted against delay accuracy for cancellation fre-quencies across the input band.


ADC

CAL

p(t)

p (t)

CAL

DDCSR

p(t) p (t)

Generator

Chip Boundary

x5LNA

Tone

System Controller

Figure 3.26: Our implementation of the MWC adds a fifth branch and interposerswitches to enable online calibration.

branch is removed for calibration. Once removed, we input a calibration tone in the

to-be-canceled blocker band and measure the baseband response. By sweeping the

delay around the expected optimum we determine the delay setting that minimizes the

baseband contribution of the calibration tone. Once this optimal setting is determined

the now-calibrated branch is switched back into the continuously operating MWC and

the next branch may be removed for calibration.

Calibration may be performed with either a sinusoidal or square waveform. The

comb filter set up by the delay-based harmonic cancellation nulls both the undesired

frequency and all of its odd multiples. As the Fourier series for a square wave contains

only odd harmonics the entire series is concurrently nulled. Thus, the setting that

minimizes the measured baseband power for an input square wave is identical to that

which minimizes the measured baseband power for an input sine wave.


3.6.3 Limits to SHR

Both the sequence-based and delay-based harmonic rejection techniques presented

in subsections 3.6.1 and 3.6.2 are designed to reject a single blocker independent of

each other, but there exist practical limitations to the attainable rejection. In this

subsection we will discuss the limiting factors for the independent application of both

rejection techniques as well as for both techniques used in concert.

We plot the simulated SHR against system jitter for sequence-based rejection,

delay-based rejection, and their combined application in Figure 3.27. For all three

curves the SHR at low jitter plateaus at some maximum, and at high jitter the SHR

decreases in proportion to the jitter (for the combined plot the plateau is beyond the

displayed axes).

The observed low-jitter plateau and high-jitter roll-off is fundamental. For sequence-

based nulling the algorithm nulls an undesired harmonic by composing an opposite

vector from the set of zero-value sequence elements. That set provides a fine grid of

possible vectors, but some residual error is expected. As demonstrated in Figure 3.22

each randomly generated set of desired bands yields a maximum theoretical SHR. For

the bands of interest simulated in Figure 3.27 that limit is 51.9 dB.

The SHR for delay-based harmonic rejection behaves similarly, but for different

reasons. Delay-based harmonic rejection produces an equal-and-opposite mixer har-

monic designed to minimize their sum. The extent to which they are nulled is limited

by the accuracy with which the opposite vector is generated. At low jitter mismatch

between the physical elements in the two branches limits rejection. Figure 3.27 depicts

the SHR limit in the presence of a 0.3% gain mismatch between the two branches.

Clock jitter affects delay-based cancellation through coefficient uncertainty as well.

The mixing signals both pass through digital-to-delay converters that add indepen-

dent jitter to each signal. Instantaneous differences between the clock transitions at

the mixer input directly contribute to imperfect harmonic cancellation.


0.1 1 10 10030

40

50

60

70

80

90

RMS Jitter (ps)

SH

R (

dB)

Sequence−BasedDelay−BasedCombined

Figure 3.27: Simulated SHR achieved through sequence-based harmonic rejectionplotted against RMS jitter.


The residual left by imperfect cancellation is proportional to the original harmonic

amplitude, so we expect the effects of sequence-based and delay-based rejection to

compound and improve performance. As is clear from Figure 3.27, cascading these

systems does not improve the SHR at high jitter levels, but rather reduces the point

at which we expect jitter to dominate.

3.7 Sensitivity of the MWC

Having established the SHR as the appropriate blocker rejection figure of merit for the

MWC and having developed to techniques to improve it we transition to the analysis

of the non-standard noise and distortion behavior of the MWC. In this section we

develop an equation for the sensitivity of the MWC receiver expressed as a function

of block-level parameters, taking special care to elaborate on the noise considerations

uniquely relevant to the MWC. In particular we address wideband noise folding, zero-

value threshold selection (as previously discussed in section 3.6.1), and inter-branch

delay optimization. We subdivide this section in two: First we develop the output-

referred noise of a single MWC branch and specify the optimal zero-value threshold

with respect to noise performance, then we account for the multi-branch nature of

the MWC so as to establish an overall equation for receiver sensitivity.

3.7.1 Single-Branch Noise

From the overall MWC system depicted in Figure 3.28 we elaborate on a single branch

as shown in Figure 3.29, highlighting the noise contribution from individual blocks.

As labeled, the antenna noise is given by NA, and the input-referred noise of the

LNA, mixer, low- pass filter, and ADC are given as NM , NF , and NADC respectively.

Similarly the gain of the LNA, mixer, and filter are given as AL, GM ⋅ ∣cd∣, and ZF ,

respectively. As noted in 3.2 the mixer also folds additional wide-band noise to


x(t)

p(1)(t)m = 1⋰m =M

y(1)[n]⋰y(M)[n]

Figure 3.28: Schematic of the MWC architecture.

X

NoiseFolding

Y

NA NL

ALNM

GM ⋅ ∣cd∣k NF

AFNADC

Figure 3.29: Noise sources in the MWC.

baseband, which is accounted for with the multiplicative factor k.

For the noise model presented in Figure 3.29, the total output referred noise NT

is given as

NT = (((NA +NL)A2L +NM)G2

M ∣cd∣2k +NF)Z

2F +NADC . (3.42)

For all multi-band mixing signals we here note that the signal gain and noise gain

are not identical—each in-band harmonic present in the mixing signal folds addi-

tional noise into the mixer’s output. For single-frequency mixers each higher-order

harmonic is severely attenuated relative to the fundamental so that their respective


noise contributions are negligible and are generally ignored. However, for the mix-

ing sequences used in the MWC, where multiple desired harmonics are present and

numerous undesired harmonics are only moderately attenuated, the additional noise

contribution is appreciable.

For multichannel mixers the output noise is given as

Nout,multichannel = NW∑ ∣cx∣

2, (3.43)

where N is the white noise power per Hz incident on the mixer, W is the channel

bandwidth, and each cx describes a harmonic of the mixing signal. Similarly, for

a single-channel mixer where the desired mixer harmonic cd overshadows all other

harmonics the output noise is given as

Nout,single channel = NW ∣cd∣

2. (3.44)

The additional noise gain is the ratio of multi-channel to single-channel output noise,

and defines the multiplicative noise folding parameter k, which is thus given as

k =∑ ∣c∣2

∣cd∣2. (3.45)

We also note that the noise folding parameter k encapsulates the single-sideband

noise penalty incurred by this implementation of the MWC. For a double-sideband

implementation we may treat the positive and negative input bands independently,

double the number of receiver branches, and then reduce k by a factor of two.

From Equation 3.45 we are able to quickly determine k for any given sequence.

We can quickly calculate ∣cd∣ by multiplying the sequence s by the appropriate row

of the Fourier transform matrix F. Likewise, Parseval’s theorem requires ∑ ∣c∣2 =

1T ∫T ∣p(t)∣2dt, which allows us to compute ∑ ∣c∣2 in the time domain. p(t) is defined


Branch(es) Optimal ZVT (%) k (absolute) k (dB) Minimum ∣cd∣1 0.43 2.75 4.40 0.522 0.26 6.66 8.23 0.313 0.23 10.6 10.3 0.254 0.22 14.5 11.6 0.205 0.20 18.9 12.8 0.186 0.19 22.9 13.6 0.167 0.18 27.3 14.4 0.148 0.17 31.9 15.0 0.139 0.16 36.8 15.7 0.1210 0.15 41.6 16.2 0.12

Table 3.1: Optimal values.

as a clocked, piecewise-constant function that takes on values from −1,0,1, so

the time-domain integral in Parseval’s theorem simplifies to the fraction of sequence

elements that take on non-zero values.

In Section 3.6.1 we described the procedure for generating the multitarget mixing

sequence using a specific zero-value threshold (ZVT) T from Equation 3.26, but did

not explicitly specify its value. Recalling that T discriminates between those sequence

elements that strongly contribute to the desired mixer harmonics and those that

predominantly contribute to the spurious mixer harmonics we choose T to minimize

the noise folding parameter of the MWC.

In order to determine the optimum ZVT we run a Monte Carlo simulation wherein

we randomly select 5,000 sets of desired frequency bands. For each set of bands we

sweep the ZVT and create a mixing sequence following the procedure outlined in

Section 3.6.1. For each of these sequences we determine k and specify the ZVT

so as to minimize the average noise folding parameter. The results are plotted in

Figure 3.30, and the minimum values and associated parameters are given in Table

3.1. These optimal noise folding parameters and harmonic gains may then be used

in further system calculations.


0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 10

3

6

9

12

15

18

21

Zero−Value Threshold (% of |Fi,j

|)

Noi

se F

oldi

ng F

acto

r k

(dB

)

12345678910

Branches

Figure 3.30: Noise folding vs. ZVT Monte Carlo simulations.

3.7.2 Multi-Branch Noise

Equation 3.42 gives the noise power measured at the terminal ADC of each MWC

branch, but does not encapsulate the multi-branch behavior inherent to the MWC.

The MWC is assumed to implement an identical mixing sequence in each branch

subject to a branch-dependent delay. We can therefore elaborate on the trimmed

mixing matrix expression originally defined in Equation 2.13, re-expressing it in a

more precise form applicable to this implementation:

C′ =

⎡⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎣

c(1)d1

c(1)d2

⋯ c(1)dM

c(2)d1

c(2)d2

⋯ c(2)dM

⋮ ⋮ ⋱ ⋮

c(M)d1

c(M)d2

⋯ c(M)dM

⎤⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎦

=

⎡⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎣

cd1ejω1τ1 cd2e

jω2τ1 ⋯ cdM ejωM τ1

cd1ejω1τ2 cd2e

jω2τ2 ⋯ cdM ejωM τ2

⋮ ⋮ ⋱ ⋮

cd1ejω1τM cd2e

jω2τM ⋯ cdM ejωM τM

⎤⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎦.

(3.46)


For the system depicted in Figure 3.29 the branch-independent gain is

g = ALGm∣cd∣ZF , (3.47)

which allows the entire behavior of the MWC to be summarized as

Y = gC′X′ (3.48)

For low-rate measurements Y and a-priori knowledge of both g and C′, the in-

band information X′ is back-calculated, yielding

X′ =1

gC′−1Y. (3.49)

However, in the real world, the measurements are made in the presence of noise–

thus Equation 3.48 is extended to

Y = gC′X′ +N, (3.50)

with noise vector N defined as

N = [

√

N(1)T

√

N(2)T . . .

√

N(M)T ]T . (3.51)

For simplicity each N(m)T is assumed to be independent and to have the same

magnitude NT given in Equation 3.42 (this yields a conservative estimate for the

system). We then estimate the input X′ as

X′ = X′ +1

gC′−1N, (3.52)


and the error in our estimate X′ −X′ as

X′ −X′ =1

gC′−1N. (3.53)

The power in the estimated error is given by the covariance matrix (X′−X′)(X′−

X′)T , which is given as

(X′ −X′)(X′ −X′)T =1

g2C′−1NNTC′−T . (3.54)

We note that for independent noise sources√

N(i)T N

(j≠i)T = 0, and NNT can be

simplified to NT I, with I being the identity matrix. Thus Equation 3.54 simplifies to

(X′ −X′)(X′ −X′)T =NT

g2C′−1C′−T . (3.55)

Recalling that C′ is defined by the known harmonic gains of the target frequency

bands and the specified branch-to-branch delays as expressed in Equation 3.46, we are

able to define the delays to optimize the noise performance of the MWC. Specifically,

for a given set of harmonics we wish to minimize the maximum value that lies along

the major diagonal of NTg2 C′−1C′−T . For simplicity we define the noise averaging

parameter λ according to

λ = max(diag(C′−1C′−T )), (3.56)

which allows us to simply describe the worst-case estimate of system-wide input-

referred noise power, and thus the sensitivity of the receiver as

Sensitivity =λNT

g2W (3.57)


for input bandwidth W .

The sequence optimization algorithm is designed to produce cd1 ≈ cd2 ≈ . . . ≈ cdM =

cd. Thus for an M branch MWC the matrix C′ can be normalized such that

C′ = cd√M

⎡⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎣

1√Mcd1e

jω1τ1 1√Mcd2e

jω2τ1 ⋯ 1√McdM e

jωM τ1

1√Mcd1e

jω1τ2 1√Mcd2e

jω2τ2 ⋯ 1√McdM e

jωM τ2

⋮ ⋮ ⋱ ⋮

1√Mcd1e

jω1τM 1√Mcd2e

jω2τM ⋯ 1√McdM e

jωM τM

⎤⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎦

= cd√MB′, (3.58)

and λ can be expressed as

λ = max(diag(C′−1C′−T )) =1

M ∣cd∣2max(diag(B′−1B′−T )). (3.59)

Furthermore, we see that for a given mixing sequence λ depends only on the relative

branch delays (τ1, τ2, . . . , τM).

The matrix B′ consists solely of equal-magnitude complex numbers and the columns

of B′ have unit magnitude. Without proof we assert that λ is minimized when B′

is a unitary matrix. That is to say the columns are mutually orthogonal. As intu-

itive justification, let us consider the two edge cases. First, in the case where B′ is

singular at least one of its eigenvalues must be zero. The eigenvalues of B′TB′ are

the eigenvalues of B′ squared, so at least one of its eigenvalues must also be zero.

The eigenvalues of a matrix’s inverse are the reciprocals of the original eigenvalues,

so at least one of the eigenvalues of B′−1B′−T is infinite. Furthermore, the trace of

any matrix is equal to the sum of its eigenvalues, such that

∑ eig(B′−1B′−T ) =∑diag(B′−1B′−T ), (3.60)

therefore, as at least one of these eigenvalues must be infinite so must at least one


element on the diagonal be infinite. λ as described in Equation 3.56 is the largest

diagonal element, and as we are trying to minimize λ, the case in which B′ is a singular

matrix represents the worst-case scenario. Intuitively, less singular B′ matrices have

lower λ, and the lowest possible λ corresponds to a unitary matrix. In the case where

B′ is unitary B′−1B′−T simplifies to the identity matrix, and λ simplifies to

λ =1

M ∣cd∣2, (3.61)

which matches intuition because it guarantees that for M measurements of the same

noisy channel, the RMS noise may be decreased by up to a factor of√M .

Now that we have specified optimal values for both k and λ we can explicitly

define all of the unknowns in Equation 3.57 in terms of system parameters. The

explicit system sensitivity

Sensitivity =(((NA +NL)A2

L +NM)G2Mk∣cd∣

2 +NF)Z2F +NADC

M ∣cd∣2A2LG

2MZ

2F

W (3.62)

is thus given.

3.8 Maximum Input Power of the MWC

In this section we develop a conservative estimate for the maximum allowable input

power of the MWC following the analysis presented in [37], and introduced in [26].

For a single-band system the two-tone intermodulation ratio (IMR2) relates the

output power and the third-order output intercept point (OIP3) according to

IMR2 = 2(OIP3 − Pout). (3.63)

Furthermore, under the assumption that the third-order nonlinearity is dominant,


Multiband Subsystem

p(t)

Figure 3.31: The multiband subsystem within a single MWC branch.

the IMR2 serves as an effective proxy for the signal-to-noise plus distortion ratio

(SNDR) of the system. Therefore, by rearranging Equation 3.63 to

Pin,max = OIP3 −SNDRmin

2−G, (3.64)

we describe the maximum allowable input power for a single-band system as a function

of that system’s OIP3, gain G, and required SNDRmin.

Equation 3.64 applies to single-band systems, and while each branch of the MWC

outputs only the single baseband, the input contains multiple signal bands simulta-

neously. System nonlinearity produces distortion terms for every pair of signals, so as

the number of input bands increases the distortion does as well. We therefore separate

the multiband subsystem as depicted in Figure 3.31 and account for the additional

distortion before integrating it into the overall system.

To account for multitone intermodulation we us the multitone intermodulation

ratio (M − IMR), defined by

M − IMR = IMR2 −C.F., (3.65)


with

C.F. = 10log(4n2 − 6n + 2 + 6(n + 1 mod 2)

n2) , (3.66)

which generalizes the IMR2 for many adjacent bands and constitutes the worst-case

for intermodulation distortion [38]. Here n represents the number of equal-power

coincident tones.

Equation 3.65 demonstrates that the cost associated with a multitone system

manifests as a correction factor that reduces the intermodulation ratio. Since the

intermodulation ratio and OIP3 are directly linked through Equation 3.63, the same

correction factor may be applied to the OIP3 of the multiband subsystem.

For any cascaded system the overall OIP3 can be calculated with knowledge of

its sub-blocks [39]. Here

√C.F.

OIP3subsystem=

1

OIP3LNA ⋅Gmixer

+1

OIP3mixer(3.67)

gives the linear-scale overall OIP3 of the multiband subsystem.

In our implementation of the MWC each band is assumed to have no more than

four constituent sinusoids, and no more than four total channels. We thus calculate

C.F. = 5.6 dB for n = 16, and note that in the limit as n approaches infinity C.F.

approaches 6 dB. Furthermore, this correction factor is incredibly conservative, since

it is incredibly unlikely that the bands used for the MWC should be directly adjacent.

With the effective OIP3 of the multiband subsystem calculated in 3.67 we can

reapply the cascading relation to an entire branch of the MWC, which yields

1

OIP3overall=

1

OIP3subsystem ⋅GLPF

+1

OIP3LPF. (3.68)

According to [40], the coding schemes used in LTE receivers can recover the input

signal at signal-to-noise ratios down to −6 dB. Thus, combining Equations 3.64 and


Reference Noise Figure (dB) Gain (dB) IIP3(dBm) Process (nm)

Sobhy 2011, [41] 2 23 -2.85 90Manstretta 2012, [42] 2.25 21 2.5 90

Duong 2014, [43] 1.34 17 16 65Murphy 2012, [44] 1.9 70* 13.5 40Hedayati 2015, [45] 1.8 50* 5 40

Table 3.2: State of the art LNAs. *Entire receiver chain.

3.68, we see that the maximum input power that can be applied to the MWC is given

by

Pin,max = 10log⎛

⎝

1GLNA

√C.F.

OIP3LNA+GLNAGmixer

√C.F.

OIP3mixer+GLNAGmixerGLPF

OIP3LPF

⎞

⎠−SNDRmin

2. (3.69)

3.9 Link Budget Analysis

In this section we conclude our analysis of the Modulated Wideband Converter at the

system level. Using the sensitivity and maximum input power equations developed

in Sections 3.7 and 3.8 we motivate the noise and linearity design targets for the

integrated mixer that we subsequently design in Section 4.3.

We compute the noise and linearity design targets by back-calculating from Equa-

tions 3.62 and 3.69. However, in order to apply these equations we must assume some

set of LNA design parameters. A short survey of recent wideband LNAs is presented

in Table 3.2 and we see that producing a wideband LNA with a 2.5 dB noise figure, 15

dBm OIP3, and 25 dB gain is achievable with a conservative application of current

technology.

We populate the remaining variables from Equations 3.62 and 3.69 according to

Table 3.3, which also provides an abbreviated justification for the values selected.

We require NF ≤ 23.2 pA/√Hz, in order to guarantee -96.5 dBm sensitivity and

we require OIP3mixer ≥ -6.6 dBm to guarantee a maximum of -25 dBm allowable


Variable Value JustificationNA 4kT ⋅ 50 50 Ω wideband noise densityNL 4kT ⋅ 50 ⋅ 0.78 Assumed, 2.5 dB NF sets NL = NA

NM 4kT ⋅ 250 A five 250 Ω branches give a 50 Ω input match

NF ≤ 23.2 pA/√Hz Back-calculated from equation 3.62

NADC 0 We assume the ADC noise is negligibleAL 25 dB Assumed value, reasonable according to Table 3.2GM 1/250 A 250 Ω resistance has reciprocal transconductance∣cd∣ 0.2 Optimal average, from Table 3.1ZF 10/GM This resistance is high enough to compensate for

the mixer gain ∣cd∣ while allowing for a subsequent VGAM 4 Branches of the MWC for the purpose of noise averagingW 1.4 MHz Bandwidth set by minimum LTE specifications

GLNA 20 dB Same as ALGmixer 0.2 Same as ∣cd∣GLPF 10 Combined: GM ⋅ZFC.F. 5.6 dB Multiband correction factor

OIP3LNA 15 dBm Assumed value, reasonable according to Table 3.2OIP3mixer ≥ −12 dBm Back-calculated from equation 3.64OIP3LPF 10 dBm Assumed large OIP3 due to feedback linearizationSNDRmin -6 dB Minimum recoverable signal strength according to [40]

Table 3.3: Assumed system parameters, and abbreviated justifications. Elaborationto follow in Chapter 4.

input power.

Thus, having specified design targets for each circuit block in our MWC design

we proceed to the specifics of our prototype circuit’s design in the next chapter.

3.10 Summary

In this chapter, we developed the MWC system from the mathematical framework dis-

cussed in Section 2.3 into a realizable system that can operate in real-world use-cases.

After detailing the assumptions that frame our system we introduced a separation

between detection and reception modes of the MWC, which greatly improves the


receiver’s performance. We discussed the standard detection process in the MWC

receiver, and demonstrated that directly applying it to the MWC system framed by

our assumptions does not provide robust spectrum support recovery. However, we

extended the orthogonal matching pursuit algorithm to include multiple independent

measurements and used simulations to demonstrate that our system can successfully

determine the spectral support with arbitrary confidence.

For the detection mode we established a set of design targets for our receiver in-

spired by the LTE specifications and established the single harmonic rejection (SHR)

as the appropriate blocker rejection figure of merit in our system. We introduced both

sequence-based and delay-based techniques that independently improve the SHR of

the MWC, and discuss the practical limits of both. We derived equations for linearity

and noise performance that account for the non-standard multi-band nature of the

MWC and are thus able to calculate the overall sensitivity and maximum input power

of the MWC system.

Finally, working backwards from the LTE specifications and these two system

parameters we derived requirements for the individual blocks of our circuit necessary

to achieve the overall design targets, which we design in the next chapter.

Chapter 4

Circuit Design

In this chapter, we discuss the implementation details of each circuit block within our

design. Given the overall system architecture depicted in Figure 4.1 we divide the

chapter into sections that discuss the shift registers that hold the mixing sequence,

the digital-to-delay converters used to achieve fine delay control, the implementation

of the mixer and calibration switches, and the op-amp based active-RC anti-aliasing

filter. In addition we describe the clock multiplexer and control circuitry which are

unique to our implementation.

4.1 Shift Register Data Storage

As discussed in Section 3.1, each branch of the MWC will utilize an identical mixing

sequence and differ from the other branches only in its relative delay. Likewise, as

discussed in Section 3.6.1 each three-level mixing sequence will be 1332 elements long,

and operate on a 1.85 GHz clock.

The focus of this work is on the analog circuitry and system design. We there-

fore choose a data-storage architecture with reliability, ease of design, and testing

flexibility as the primary design goals. Our design implements an independent bank

72

CHAPTER 4. CIRCUIT DESIGN 73

ADC

CAL

p(t)

p (t)

CAL

DDCSR

p(t) p (t)

Generator

Chip Boundary

x5LNA

Tone

System Controller

Figure 4.1: Our implementation of the MWC receiver.

of self-looping shift registers to store the necessary sequence data for each branch of

the MWC. We use two shift registers to store each three-level sequence, and require

two sequences per branch—the relative delay between them is necessary for delay-

based harmonic rejection—and we have five branches in our implementation of the

MWC (four plus one calibration). Therefore our entire chip requires 20 shift registers

(2 × 2 × 5), each of which contains 1332 registers, and must run at 1.85 GHz.

The employed standard-cell D flip-flop architecture is depicted in Figure 4.2(a).

Each flip-flop contains 24 transistors that total 32.6 fF of capacitance. Assuming a

50% activity factor and a 1.2 V supply voltage we estimate 578 mW of total power

consumed in the shift registers on the chip due to charging and discharging these

capacitors. This is a lot. As each shift register stores a delayed copy of the same data

it is possible to drastically reduce the overall power consumption by sharing a single

data storage location (such as an SRAM) between branches and accessing multiple

data locations concurrently. Likewise, the power consumption may be reduced by


φ’ φ

φ’

φ’

φ

φ

φ’

φ

φ’

φD Q

CLK

(a)

φCLK

φD φ

φ

φ

Q

(b)

Figure 4.2: D flip-flops. (a) depicts a standard-cell flip-flop. (b) depicts a true single-phase clock flip-flop.

implementing a true single-phase clock flip-flop (as is discussed in [46] and as illus-

trated in Figure 4.2(b)), which reduces the number of gates per register from 24 to

11. However, reliability and testing flexibility are prioritized above power efficiency

in our digital design, so we leave these design improvements to future work.

We do not expect the digital switching events to corrupt our analog signals through

the substrate despite the substantial digital power consumption because the looping

nature of our shift registers ensures that the digital current draw is periodic at 1.85

GHz and is therefore well outside our band of interest.

Simulations of the employed flip-flops function up to 6 GHz, which is only a

factor of three above our intended operating frequency. We therefore take special

care in the layout of the shift register and requisite clock distribution. We split the

shift register into 84 cells and lay out the cells as depicted in Figure 4.3. Each cell

contains 16 registers, with the exception of a single column which contains only 15.

By connecting the cells according to Figure 4.3 we efficiently utilize the chip area,

minimize the connection distance between cells, and provide eight matched clock

inputs. Minimizing the connection distance between cells reduces the odds of data

corruption due to setup or hold-time violations


clk

OutIn

Figure 4.3: Shift register cell layout.

D Q

CLK

Figure 4.4: A 16 register cell of the shift register.

We use eight (23) clock lines in the shift register to simplify the clock-distribution

tree. Additionally, the clock edge must arrive with minimum skew across the entire

shift register so we add dummy capacitances to the edge clock lines (as depicted in

Figure 4.3) to maintain equal capacitance on each line. We implement the clock tree

with a fanout of six across the entire chip.

Within each cell the registers are laid out according to Figure 4.4. Of particular

note, the clock signal propagates in the reverse direction of the data flow in order to

reduce the chance of timing violations.

For testing purposes we must be able to independently write to each shift register

and subsequently read off that data for verification. We implement a five-bit decoder

to specify the shift register in question. A write-enable pin then breaks the specified

shift register loop so that the stored data may be sourced externally. In reading the


data we note that the order of the stored sequence values is important, but there is no

well-defined beginning or end to the sequence once it is stored on chip. Rather than

the absolute delay in the sequence we are interested in the relative delay between the

data stored in two different shift registers. Thus, for data verification purposes we

pass the output of the first shift register off chip along with the output of a second

shift register selected with the same five control bits we use to select a shift register

for writing.

Post-layout extracted simulations demonstrate low frequency write and read ca-

pability as well as high frequency shift register functionality up to 4 GHz, with less

than 2 ps clock skew between the clock edges at the eight shift register inputs.

4.2 Digital-to-Delay Converter

In our implementation of the MWC, we provide blocker rejection through delay-based

harmonic rejection. As discussed in Section 3.6.2, we achieve high levels of harmonic

rejection by summing the signals from two mixers with a finely-controlled relative

delay in their mixing signals. In order to achieve 50 dB of rejection that delay must

be specified to within 0.56 ps of accuracy, and in order to avoid attenuating the desired

harmonics we must be able to specify that delay across the entire mixer period Tp ≈ 71

µs.

Fine-granularity is achievable through a digitally controlled delay line, but span-

ning the entirety of Tp with such a structure is impractical. In order to achieve the

entire desired delay range we implement the delay in a coarse-fine system as depicted

in Figure 4.5. We duplicate the entire shift-register based storage hardware to im-

plement the coarse delay. We may shift the location of the stored data within the

duplicate shift register to achieve a delay equal to any integer multiple of the digital

clock period Tclk =1

1.85 GHz ≈ 540 ps. In so doing we relax the requirements on the


Figure 4.5: Coarse-fine implementation of the DDC within each branch of the MWC.

Type Number of Cells Cell Delay (ps) Capacitance (fF × 2)A 3 1.1 0.14B 7 2.6 0.35C 7 16.1 1.84D 4 104 3.25

Total 550 28.7

Table 4.1: Sizing for each delay cell.

fine digital-to-delay converter (DDC)—in this implementation it only needs to span a

single clock cycle from 0 to 540 ps. We implement fine delay control for both mixing

signals to provide redundancy—a delay in one shift register is equivalent to a negative

delay in the other, so implementing both doubles the coverage.

The fine DDC is implemented as a digitally controlled delay line as depicted in

Figure 4.6. Within the DDC we implement cells with four different delays according

to Table 4.1. For every delay cell we use a constant single-drive-strength inverter and

adjust the delay by scaling the capacitor and switch sizes. We size the capacitors and

switches such that the delay that results from all cells of a single size is greater than

the delay of the next larger size.

In order for the DDC to achieve the required 0.56 ps delay accuracy the minimum

delay step should not exceed 1.12 ps and there may be no gaps in the achievable


From SR To Mixer

DigitalControl

CLK

Figure 4.6: Implementation of the fine DDC with 21 digitally controlled delay cells.

delay curve—nonmonotonicity and extra codes are allowable so long as the entire

delay space is covered. Thus, we engage the delay cells according to the following

algorithm: Starting from code zero, as we increment the DDC code we close the

switches in the minimum-delay A cells until they are all closed. For the next DDC

code we open all of the A switches and close the first B. We resume closing A switches,

and when they are all closed we close an additional B. Once all of the A and B

switches are closed we begin closing the C switches, and once those are all closed

we begin closing the D switches. By following this algorithm we see two types of

code transitions. Either we close a single minimum-delay A switch, or we open many

switches with greater total delay than that added by a single closed switch. Thus we

provide redundancy at the transition between cell sizes and ensure complete coverage

of the delay space. A sweep depicting the post-layout extracted delays against DDC

control code is given in Figure 4.7.


0 256 512 768 1024 12800

50

100

150

200

250

300

350

400

450

500

550

DDC Code

Exc

ess

Del

ay (

ps)

Figure 4.7: Extracted sweep of delay plotted against DDC code.

We implement the digitally switched capacitors in Figure 4.6 with deep n-well

MOS capacitors to reduce the capacitance that is not controlled by our switch. Their

nonlinear capacitance combines with the voltage-dependent drive strength of the pre-

vious inverter stage so as to apply a different delay to the rising and falling edge

transitions. We minimize this effect by dividing the capacitance within each delay

cell and placing an odd number of inverters between them. Additionally, we decouple

block-to-block effects by placing at least three inverters between each capacitor and

maintaining an odd number of inverters per delay cell.

As discussed in Section 3.6.3, clock jitter directly impacts the achievable SHR for

both sequence-based and delay-based rejection. As discussed in [47], thermal noise

adds timing uncertainty to digital gates according to

tn2=kT

C⋅ (trampVdd/2

) , (4.1)


0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 10

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Voltage UncertaintyTiming Uncertainty

t

V

Vdd

2

trise

kTC

(trise

Vdd/2

)2

Figure 4.8: During a digital transition uncertainty in voltage translates to uncertaintyin time.

and as depicted in Figure 4.8. As is shown, the thermal-noise induced voltage un-

certainty translates to timing uncertainty according to the slope of clock transition.

Unfortunately, according to Equation 4.1, adding capacitance to adjust the delay

decreases the slope of the rising edge and increases the jitter accordingly.

For cascaded systems, such as depicted in Figure 4.6, the timing uncertainty

for each stage is independent and we compute the overall uncertainty by summing

the contribution from each stage. Under the assumption that thermal-noise is the

dominant jitter source we estimate the worst-case total output RMS jitter to be

1.2 ps from post-extraction circuit parameters and verified through transient noise

simulations. Referring back to Figure 3.27 we expect no better than 51.8 dB of

sequence-based harmonic rejection, 61.0 dB of delay-based harmonic rejection, and

68.0 dB of harmonic rejection when both techniques are applied together. However,

in practice, additional clock jitter from the clock source and supply noise variations

will increase the jitter and decrease the system performance


4.3 Mixer

The core functionality of this thesis is provided within the mixer stage. Our implemen-

tation of sequence-based harmonic rejection requires a three-level mixer, and delay-

based harmonic rejection requires effective matching between parallel mixer paths.

The calibration algorithm requires additional switches which we place within the

mixer, and the resistance of the calibration and mixer switches is voltage-dependent

and contributes to system nonlinearity, and . In this section, we detail the architecture

and design decisions that trade off these considerations within the mixer subsystem.

For our design we implement a passive current-mode mixer with integrated cal-

ibration switches as illustrated in the simplified schematic of Figure 4.9. We use

passive mixers because they are easy to fabricate in CMOS, demonstrate greater lin-

earity than active Gilbert-cell mixers, and because the switches within passive mixers

are driven so as to be either fully on or off, thus allowing us to directly implement

our digital mixing sequence. Additionally, operating in the current mode allows us

to directly implement the summing operation required for delay-based harmonic re-

jection at the mixer output since the subsequent stage provides a virtual ground at

this node.

We choose the overall resistance of the mixer to provide an impedance match at

the RF input. The input RF port sees the parallel combination of the mixer resistance

from each branch and should be matched to 50 Ω. For five branches of the MWC,

each with two parallel mixing paths this sets the total resistance to 500 Ω per path,

divided amongst an n-well unsalicided polysilicon resistor and the DC resistances of

the calibration and mixer switches.

We place the mixer switches at the output of the mixer adjacent to the virtual

ground provided by the subsequent anti-aliasing filter to minimize the voltage swing

across the mixer switches (and the associated nonlinearity).


CAL

p(t)

p (t)

CAL

Generator

LNA

Tone

GM

GM

Mixer

AA Filter

ChipBoundary

5x

Figure 4.9: Simplified mixer structure displaying current-setting resistors, calibrationswitches, and mixer switches.

The polysilicon and switch resistors establish a voltage divider with the relation

VswitchVinput

=Rsw,cal +Rsw,mix

Rpoly +Rsw,cal +Rsw,mix

, (4.2)

which attenuates the voltage seen across the calibration and mixer switches. Given

the fixed total resistance set by the input matching requirement, decreasing the switch

resistance can be seen as attenuating the effect of switch nonlinearity. We therefore

implement both sets of switches with minimum length devices and set the common-

mode input voltage to 500 mV rather than the 600 mV mid-rail voltage. Increasing

the width of the switch transistors can further decrease their resistance, however,

doing so increases the parasitic switch capacitances. These capacitances introduce

crosstalk and self-mixing as well as parasitic charge pumps that also add to the

nonlinearity of the mixer. We therefore limit ourselves to Rsw,cal +Rsw,mix = 50 Ω or

10% of the total mixer resistance.

Figure 4.10 plots the current through the mixer as a function of the input voltage

when both the calibration and mixer switches are closed. From this plot we extract


−0.5 −0.25 0 0.25 0.5−10

−5

0

5

10

Vin

(V)

I in (

mA

)

Figure 4.10: Simulated current plotted against input voltage.

Coefficient Valuea0 0 Aa1 2 mA/Va2 -44.7 µA/V 2

a3 0.36 nA/V 3

Table 4.2: Combined mixer and switch resistance nonlinearity coefficients.

the nonlinearity coefficients given in Table 4.2, and from these coefficients we calculate

the IIP2 and IIP3 according to

IIP2 = 10log(1

100⋅ (a1

a2

)2

) + 30 = 42.9dBm (4.3)

and

IIP3 = 10log(1

100⋅4

3⋅ ∣a1

a3

∣) + 30 = 78.7dBm (4.4)

The high IIP values calculated in Equations 4.3 and 4.4 are well above the target

specification set forth in Section 3.9, demonstrating that the linearity specification

does not limit our design.

The sequence-design algorithm we outline in Section 3.6.1 requires a tri-state


RFInput

φp

φm

φz φz

ToAAF

InputCalibration cal

cal

Mixer Core

Figure 4.11: Simulated current plotted against input voltage.

mixer. We therefore implement the mixer core depicted in Figure 4.11 and driven

by three mutually exclusive control signals φp, φm, and φz that produce mixer levels

1, -1, and 0 respectively. Similar to standard passive mixers, during φp we close

switches to connect the input to the output terminals, and during φm we close switches

that invert the input-to-output connection. To implement a zero mixer level we

additionally implement two sets of switches that close during φz. When closed, the

switches connect both input and output ports to differential ground. We also add an

additional set of dummy resistors to provide a constant, first-order port impedance

match independent of switch state.

The delay-based harmonic rejection system introduced in Section 3.6.2 is limited

by the matching we are able to achieve between the two mixer paths. The mixer

and calibration switches are placed directly adjacent to each other, and the effect

of any switch-resistance mismatch is attenuated by the ratio given in Equation 4.2,

so we assume that the mismatch between polysilicon resistors dominates. In order

to achieve within 0.3% resistor mismatch in upwards of 95% of our resistor pairs we


apply Pelgrom’s equationσRR

=AR

√WL

, (4.5)

with A = 2 %µm for n-type polysilicon resistors, taken from [47]. We set WR = 7.5

µm and LR = 31.5 µm for the resistor, and implement both calibration and mixer

switches with W = 1 µm L = 60 nm, and 20 fingers each, thus providing 500 Ω of total

resistance between the input port and the virtual ground provided by the subsequent

transimpedance amplifier.

4.4 Active-RC Anti-Aliasing Filter

In this section we detail the anti-aliasing filter design. The filter serves two purposes

within the larger system. First, it must provide a very low impedance input node so

that the currents from the parallel mixing paths of each MWC branch sum effectively.

Second, it provides a filter that attenuates aliases added to the signal by subsequent

digitization.

A top-level schematic of the filter is given in Figure 4.12. We begin by specifying

the passive components in the feedback network. The feedback resistor Rf sets the

DC gain of the filter in conjunction with the DC resistance of the switching mixer Rm.

We design our mixer-filter system to have a total gain of 2—some small amplification

attenuates noise from subsequent stages while allowing for subsequent filter stages and

a variable-gain-amplifier. As given in Table 3.1, a four-target mixing sequence with

optimal noise performance is expected to provide gain ∣cd∣ = 0.20 and with Rm = 500

Ω set by the input matching requirement. We therefore have

Rf =2

∣cd∣ ⋅Rm

= 2.5 kΩ. (4.6)

We choose the feedback capacitor that sets a ω3dB frequency marginally above


AA Filter

Rf

Cf

A(s)

Cf

RfRm

Figure 4.12: Anti-aliasing filter.

the maximum bandwidth of our filter, thus minimizing aliasing by maximizing the

separation between the filter bandwidth and the sampling frequency. We allow signal

bandwidths up to 5.6 MHz (as discussed in Section 3.6.1), so we set Cf = 8.6 pF

and place ω3dB = 7.5 MHz. Our sampler operates at 60 MS/s, so we achieve greater

than an order of magnitude of alias attenuation at baseband.

We design the amplifier depicted in Figure 4.12 to meet the low input impedance

and noise specifications of the anti-aliasing filter stage. We target an input DC

resistance no greater 10 Ω across the signal bandwidth up to 5.6 MHz, which is well

below the 250 Ω effective mixer resistance. The low-frequency input impedance is

given by

Rin =Rf

1 +A0

, (4.7)

and so we target an op-amp transfer function with A0 ≥ 48 dB and with a 3 dB

frequency above 5.6 MHz.

Figure 4.13 presents the schematic of our two-stage op-amp design, which follows

from the design in [48], with gm/ID values given in Table 4.3.

The first stage provides 25.4 dB of DC gain while the second stage provides 24.5 dB

of DC gain, for a total DC gain of 49.9 dB. We utilize a PMOS input stage because of

its improved noise performance and because it allows us to reduce the common-mode


M1 M2

M3 M4 M5 M6

M7 M8

CMRMRCM RCM

RCM RCM

CMRM

ITICM

Figure 4.13: Schematic of the op-amp within the anti-aliasing filter.

Device gm/IDM1/M2 -15.85 mV −1

M3/M4 8.24 mV −1

M5/M6 14.24 mV −1

M7/M8 -15.10 mV −1

Table 4.3: Op-amp active device operating points.


input voltage. We target high gm/ID values for M1, M2, M5, and M6, and low gm/ID

values for M3, M4, M7, and M8 to increase noise-efficiency. However, we are limited

in how far we can reduce the gm/ID of M3, M4, M7, and M8 by our common-mode

feedback implementation. We use low-threshold-voltage PMOS devices to increase

the swing of both stages. We use standard NMOS devices in the first stage because

their output resistance is roughly twice as large as that of the low-threshold-voltage

devices, and we use high-threshold-voltage NMOS devices in the second stage to allow

the common-mode output of the first stage to sit closer to mid-rail.

We implement common-mode feedback in both stages with a direct resistor con-

nection. We adjust the common-mode output of the first stage by trimming the tail

current IT , and we adjust the common-mode output of the second stage by trimming

ICM . We design both trim systems to allow adjustments up to ±100 mV . The Miller

capacitance CM sets the dominant pole of the op-amp to 4.25 MHz, which is be-

low the 5.6 MHz design target, but was necessary to achieve stability for all trim

settings. Figure 4.14 illustrates simulated gain and phase plots of the post-layout

op-amp transfer function.

Noise in RF systems is integrated over the signal band. Within the signal band

neither the anti-aliasing filter nor the op-amp’s dominant pole have cut in, and so in

our analysis of the filter noise we include only the DC terms as illustrated in Figure

4.15. Following the analysis presented in [49], the input-referred voltage noise of the

entire mixer-filter system is given by

v2in = 4kT (Rnoise (

Rs +R

R)

2

+RsRs +R

R)∆f. (4.8)


1 kHz 1 MHz 1 GHz

−20

0

20

Frequency

Loop

Gai

n (d

B)

(a)

1 kHz 1 MHz 1 GHz

−180

−135

−90

−45

0

Frequency

Loop

Pha

se (

degr

ees)

(b)

Figure 4.14: Op-amp feedback loop transfer function: (a) gain (b) phase


Rs

R

vRs

2

vR2

vRnoise

2

Vin Vout

Mixer AAF

Figure 4.15: Noise schematic for the anti-aliasing filter.

We separate the input-referred voltage noise into contributions from the mixer resis-

tance and the anti-aliasing filter as

v2in,Mixer = 4kTRs∆f (4.9)

and

v2in,AAF = 4kT (Rnoise(

Rs +R

R)

2

+R2s

R)∆f, (4.10)

from which we derive the input-referred current noise of the anti-aliasing filter, given

as

i2in,AAF = 4kT (Rnoise

R(Rs +R

RsR) +

1

R)∆f. (4.11)

The link-budget analysis of Section 3.9 specifies that this input-referred current noise

must be below 23.2 pA/√Hz in order to achieve our sensitivity target.

Once the gm/ID values and Miller pole locations are specified we scale the device

widths and device currents until we meet the noise specification. By setting the

device parameter values to those given in Table 4.4 the anti-aliasing filter achieves

12.0 pA/√Hz input-referred current noise, and so overdesign the system. Of note, for

these values the output resistance of the second stage is 1.57 kΩ, which is appreciable

relative to the 2.5 kΩ feedback resistance. The resulting gain degradation has been


Device Parameter(s) Value(s)M1/M2 W , L, id 960 µm, 240 nm, -2.65 mAM3/M4 W , L, id 80 µm, 240 nm, 2.65 mAM5/M6 W , L, id 160 µm, 240 nm, 1.15 mAM7/M8 W , L, id 320 µm, 240 nm, -1.15 mARCM Resistance 20 kΩRM Resistance 117.7 ΩCM Capacitance 5 pF

Table 4.4: Anti-aliasing filter component values.

−0.8 −0.4 0 0.4 0.8−1.5

−1

−0.5

0

0.5

1

1.5

Input Current (mA)

Out

put V

olta

ge (

V)

Figure 4.16: DC sweep of the anti-aliasing filter.

accounted for in the numbers and plots given previously.

Finally, as shown in Figure 4.16, we sweep the output voltage as a function of input

current to measure the DC nonlinearity of the anti-aliasing filter’s transimpedance.

Table 4.5 gives the nonlinearity coefficients, and applying Equations 4.3 and 4.4 we

estimate 48.8 dBm of IIP2 and 20.13 dBm of IIP3. Comparing to the mixer non-

linearity calculated in Section 4.3 we see that the anti-aliasing filter’s nonlinearity

dominates, but still meets the design target from Section 3.9.


Coefficient Valuea0 0 Va1 9.895 V /Va2 -224.2 mV /V 2

a3 -7.522 V /V 3

Table 4.5: Anti-aliasing filter nonlinearity coefficients.

4.5 Clock and Control Considerations

In this section we describe the unique peripheral circuitry in our MWC design. Over

the course of testing the data-storage shift registers must operate at two different

clock speeds. During initialization the data within each shift register and control bits

that dictate the DDC delays and the anti-aliasing filter trim settings are specified

from an off-chip source and must be read back to that source for verification. Data

I/O is limited by the external interface circuitry and cannot run at the internal 1.85

GHz clock frequency. Therefore, we add a second low-frequency clock pin to drive

the IC during initialization and a clock multiplexer to switch to the fast clock upon

completion.

We cannot implement a standard digital multiplexer because the fast and slow

input clocks are uncorrelated. If we toggle between the two clock signals there is

some chance that the clock transition falls within the setup or hold time of a standard

multiplexer. In this case the output may produce a short glitch pulse that can corrupt

the data stored within the shift register.

Our clock multiplexer is depicted in Figure 4.17. After synchronizing the both

the slow clock and the selector bit to the fast clock it generates mutually exclu-

sive clock-enable signals CEfast and CEslow and produces an output according to

CLKout = CLKfast ⋅CEfast +CLKslow ⋅CLKslow. We construct the clock enable en-

able signals such that they can only transition when their associated clock signal is at

zero. Additionally, we ensure that the separation between positive values of CEfast


CLKSelect

CLKOut

CEfast

CEslow

CLKfast

CLKslow

Figure 4.17: Clock multiplexer.

and CEslow are separated by a full period of CLKfast, thus ensuring a glitch-free mul-

tiplexer. Figure 4.18 illustrates the output of the clock multiplexer over the course of

several state transitions as well as the values of the internal enable nodes.

Online calibration, as described in Section 3.6.2, requires that our MWC have the

ability to change the data stored within the calibration shift register while the system

is driven by the fast clock. Fortunately, as assumed in Section 3.1, the shift registers

in each branch of the MWC store the same data, so in updating each shift register

we do not need to overwrite the stored data, merely adjust its phase.

In order to adjust the phase of the signal stored in any shift register we implement

the circuit illustrated in Figure 4.19, which we place at the base of the clock tree

leading to each shift register.

When the shift register is selected, a rising edge from the externally sourced clock-

disable pin causes the shift register’s clock signal to skip a period as depicted in Figure

4.20. By repeatedly driving the clock-disable pin we are able to arbitrarily adjust the

phase delay in any shift register.

Within our chip there is a great deal of additional circuitry that is required for the

MWC to function. However, the designs for the high-frequency CML clock buffer,


Clo

ck O

utp

ut

Fas

t E

nab

leS

low

En

able

Time

Figure 4.18: Clock multiplexer output, fast enable, and slow enable.

CLKOut

CLKdisable

CLKin

Figure 4.19: Clock-disable circuit.

Clo

ck In

pu

tC

lock

Ou

tpu

t

Time

Figure 4.20: Skipped clock pulse as a result of a clock-disable rising edge.


low-distortion analog output buffers, gm-bias generation circuitry, and numerous other

circuit blocks follow standard design schema and so we omit their description here.

We thus conclude our chapter on the circuit design of our MWC implementation.

4.6 Summary

In this chapter, we translated the circuit block requirements outlined in Chapter 3

into a transistor-level design that we had fabricated. First, we discussed the mixing

sequence data storage, which we implemented with a bank of looping shift registers.

After which, we detailed the digital-to-delay converter which allows us to specify

sequence-to-sequence delays with the fine granularity necessary for effective delay-

based harmonic rejection. We designed our passive mixer to include a third, zero-level

to enable sequence-based harmonic rejection and specified the device parameters to

minimize the nonlinearity. At the end of our prototype IC’s signal chain we designed

a first-order active-RC filter that provides a low-impedance summing junction and

anti-aliasing. Finally, we detail the unique circuitry used to implement a glitch-free

clock multiplexer and a high speed shift register disable.

Chapter 5

Test Setup and Measurement

Results

In this chapter, we present the measurement results of our MWC receiver. We begin

by detailing our laboratory setup, followed by a discussion of the integrated circuit

layout and the fabrication details of our prototype.

As discussed in Chapter 3, we designed our system within a set of receiver spec-

ifications and used those to motivate the design of an integrated mixer prototype,

which we detail in Chapter 4. Our measurements therefore focus on the performance

parameters of our mixer. Specifically, we discuss the single harmonic rejection, non-

linearity, and noise measurements of our mixer, and once established, we compare

our mixer to recent harmonic rejection mixer publications. We conclude this chapter

with system-level measurements that verify signal reception in the MWC.

5.1 Test Setup

In this section we overview the instrumentation and and test setup, which we illustrate

in Figure 5.1. Testing the MWC requires up to four concurrent signals spread across

96

CHAPTER 5. TEST SETUP AND MEASUREMENT RESULTS 97

Figure 5.1: Experimental test setup.

the entire input spectrum. We produce these signals with a bank of signal generators

(HP 8657B, HP 8644B, HP 8648C, and ESG-D E4432B), and superimpose them

with a set of power combiners (3x Mini-Circuits ZFRSC-42-S+). However, the power

combiners reduce the SNR and introduce additional nonlinearity to the system, so we

abbreviate the signal generation network according to test in progress. We produce

similar tones for calibration and clock generation with an HP 8648C signal generator

and an HP 8665A signal generator respectively. We specifically choose the later to

produce a low-jitter clock.

We convert the single-ended radio frequency input signal to differential with a

Picosecond Pulse Labs 5315A differential pulse splitter, which has good differential

balance up to 17 GHz. The calibration and clock signals are much less sensitive to

signal balance and so we use on-board BalUns for both. We set the common mode

output voltage for each of these differential signals with the filtered resistor divider


5 kΩ

0.1 µF

0.1 µF

22 µF

22 µF

BeadVcm

VBIAS

Figure 5.2: On-board common-mode bias generation.

depicted in Figure 5.2.

Our MWC prototype provides the differential output from five identical branches

(4 + calibration). For each branch we produce a single output signal by applying

a differential-to-single-ended line driver (MAX4444 or INA103), which drives our

measurement ADCs.

We take measurements with an NI PXI-5105 eight-channel oscilloscope card within

an NI PXIe-1085 chassis. The oscilloscope card allows us to synchronize sampling

across all of the MWC branches and provides an additional 24 MHz internal anti-

aliasing filter.

We control and measure the internal state of our prototype IC with a Nano River

MiniBoard, which sets 13 control pins and reads 3 data pins from our prototype

IC. These pins allow us to initialize the shift registers, DDC state, and analog trim

bits on our chip as well as individually disable various circuit blocks and dictate the

calibration state of the MWC.

Our entire system is centered in MATLAB, which controls the signal generators

through a GPIB interface, the oscilloscope card with a Python script, and the Nano

River MiniBoard with a set of C++ scripts. Once assembled we are thus able to fully

automate initialization, calibration, and test for our prototype IC.


DDC Domain Analog DomainDigital Domain

Figure 5.3: Annotated die photo.

5.2 Integrated Circuit Prototype

Our prototype IC was fabricated in a 65 nm GP CMOS process and we provide an

annotated die photograph in Figure 5.3. The die measures 3.84 mm2 and is separated

into three main domains for the shift registers, digital-to-delay converters, and analog

mixer/filter blocks.

The per-branch area, decoupling capacitance, and power draw is divided amongst

the three domains as given in Table 5.1. In particular we note that the combined

digital power draw of 747.5 mW exceeds our 578 mW estimate. In our estimate

we did include power lost driving interconnect capacitances, which we believe is the

source of this discrepancy.

We separate the three on-chip domains with guard rings and implement both the

digital-to-delay converters and analog circuitry with deep n-well transistors so as to


Domain Area (mm2) DCap (pF ) Power Draw (mW )Digital 0.0206 146.72 149.5DDC 0.0025 62.88 3.8

Analog 0.0458 31.44 22.8Total 0.0689 241.04 176.1

Table 5.1: Per-branch area, decoupling capacitance, and power draw.

isolate them from substrate ground. Each of these domains has its own independent

power supply although they share a single on-chip ground.

5.3 Mixer Measurements

In this section, we overview the measurements we make of our integrated mixer and

compare them against the state of the art. We measure the single-harmonic rejec-

tion for both sequence-based and delay-based techniques. We generalize the Y-factor

method to measure the noise figure of our entire test board and then apply a general-

ization of Frii’s formula to back-calculate our mixer’s noise factor. We briefly discuss

our measurement of mixer nonlinearity and conclude this section by comparing our

prototype with recently published harmonic rejection mixers.

5.3.1 Single Harmonic Rejection Measurement

The single harmonic rejection (SHR) figure of merit introduced in Section 3.5 mea-

sures the attenuation of an undesired blocker band relative to the desired signal bands

when the locations of both are known. Thus, we measure the SHR by driving the

RF input of our mixer with two equal-power tones such that one tone lies within

the blocker band, one tone lies within a signal band, and both tones are offset from

mid-band so that they are uniquely identifiable at baseband. From the baseband mea-

surements we directly compute the SHR as the ratio of the power in the signal-band


tone to that of the blocker-band tone.

Figure 5.4 depicts SHR measurements for three cases. Figure 5.4(a) illustrates

the case when only sequence-based rejection is applied. Here the zero-level sequence

elements are toggled so as to minimize the 250 kHz baseband blocker tone while

the delays in the parallel mixing paths are matched so as to produce no delay-based

rejection. Figure 5.4(b) illustrates the case when only delay-based rejection is applied.

Here both input signals lie within bands for which the mixing signal has high harmonic

gain. However, the relative delay between the two parallel mixing paths rotates the

250 kHz baseband tone by 180 degrees so as to cancel when the two paths are summed.

Figure 5.4(c) illustrates the case when both sequence-based and delay based rejection

are applied in concert.

We add our SHR results to Figure 3.27, which plots the simulated SHR against

RMS clock jitter for these three cases to produce Figure 5.5. Figure 5.5 demonstrates

that our measured results are consistent with rejection limited by our mixing sequence,

rejection limited by mismatch, and rejection limited by jitter. According to simulation

we expect 1.2 ps of RMS jitter, but our measurements suggest 2.2 ps of RMS jitter in

our system. Our simulations did not account for clock jitter caused by supply noise,

so this discrepancy is expected.

Table 5.2 provides repeated measurement data taken from the three packaged

devices that survived testing. We note that the variance in sequence-based SHR and

combined SHR is much lower than that of the delay-based SHR. This lends support

to the theory that the delay-based SHR is mismatch limited although this result is

inconclusive due to our low sample size.

As noted in Section 3.6.2, the digitally controlled delay is set by imperfectly mod-

eled parasitic components and so must be calibrated. We calibrate each branch by

driving its input with a calibration-tone in the undesired band and sweeping the DDC

code near its anticipated value. Figure 5.6 illustrates the calibration sweep used to


−120

−80

−40

0

Harmonic Rejection Measurement:Sequence−Based HR:

50.2 dB

(a)

−120

−80

−40

0

Mea

sure

d P

ower

(dB

m)

Delay−Based HR:

59.3 dB

(b)

100 kHz 250 kHz 450 kHz 600 kHz

−120

−80

−40

0 Sequence+Delay−Based HR:

Baseband Samples

62.8 dB

(c)

Figure 5.4: Sequence-based (a), delay-based (b), and combined (c) single-harmonicrejection measurements.

Chip NumberSHR (dB) 1 2 3 Estimate

Sequence-Based 50.2 50.3 49.4 51.8Delay-Based 59.3 62.8 61.3 61.0Combined 62.8 62.1 62.3 68.0

Table 5.2: Per-branch area, decoupling capacitance, and power draw.


0.1 1 10 10030

40

50

60

70

80

90

RMS Jitter (ps)

SH

R (

dB)

Sequence−BasedDelay−BasedCombinedSimulatedMeasured

2.2 ps Assum

ed Jitter

Figure 5.5: SHR plotted against jitter for sequence-based, delay-based, and combinedSHR rejection techniques. We simulated 1.2 ps RMS jitter and assume 2.2 ps basedon the measurements.


50 100 150 200 250 300−80

−70

−60

−50

−40

DDC Code (FS=1179)

Mea

sure

d T

one

Pow

er (

dBm

)

Est

imat

ed C

ode:

66

CalibratedCode: 128

Figure 5.6: Measured calibration tone power during a calibration sweep.

produce Figure 5.4(b). As is apparent, calibration is critically important—the rejec-

tion at the calibrated DDC code is 24.3 dB greater than at the DDC code suggested

by simulation.

5.3.2 Noise Figure Measurement

In practice noise figure measurements are generally taken with a noise figure meter.

By using a meter the calibration and calculation details are accounted for internally

and the result displayed is known with high certainty. However, if the device under

test requires a testing procedure outside the programming of the meter the measure-

ment device is useless. The mixing behavior of the MWC is one such non-standard

device. In this section we extend the Y-factor method presented in [50] and general-

ize Frii’s formula. We then apply these relations to measure the single-channel noise

figure of our prototype mixer.

Generalized Y-Factor Method

In order to understand our modifications to the Y-factor method we begin with a

simple example illustrating the standard procedure for an arbitrary device under test


PXA N9030A

346B

Figure 5.7: Setup to calibrate the noise factor of the spectrum analyzer.

(DUT). First, we make two measurements of the noise in the test setup, where N ↑ is

the measurement taken with a high-temperature input noise source of known value

(hot) and N ↓ is the measurement taken with a room-temperature input noise source

(cold). The Y-factor is calculated as

Y =N ↑

N ↓. (5.1)

If we define the excess noise ratio (ENR) of the noise source (which is known for

pre-calibrated noise sources), as

ENR =T ↑ − T ↓

T0

, (5.2)

and assume T ↓ ≈ T0 = 290 K, then the noise factor of the entire system is given by

F =ENR

Y − 1. (5.3)

When the noise source is connected directly to the spectrum analyzer (as shown in

Figure 5.7) the noise factor thus calculated is that of the spectrum analyzer itself.

After measuring the noise factor of the spectrum analyzer we add the DUT be-

tween the noise source and spectrum analyzer as depicted in Figure 5.8. Once again

we make hot and cold noise measurements. We label the initial measurements taken

with just the spectrum analyzer as N ↑S and N ↓S, and label the measurements that


PXA N9030A

346B DUT

Figure 5.8: Setup to measure noise factor of the combined DUT–spectrum analyzersystem.

include the DUT in the signal path as N ↑DS and N ↓DS. We calculate the noise factor

of the cascaded system with Equation 5.3. From our measurements with and without

the DUT we also calculate the noise gain of the DUT according to

GD =N ↑DS −N

↓

DS

N ↑S −N↓

S

, (5.4)

and back-solve the DUT’s noise factor FD using Frii’s formula—

FAS = FA +FS − 1

GA

. (5.5)

The noise factor calculation method given above cannot be applied to devices

for which the signal and noise gain are not identical. As discussed in Section 3.7,

the MWC downmixes noise from the entire band and signal from a small subset of

these bands, thus guaranteeing GN ≠ GS. We therefore must generalize the Y-factor

method to encompass devices of this nature.

The noise factor is defined as the signal-to-noise ratio at the input of a device

divided by the signal-to-noise ratio at its output. For an amplifier with input noise

Ni and added input-referred noise NIR this simplifies according to

F =Si/Ni

So/No

=Si

GSSi⋅GN(Ni +NIR)

Ni

=GN

GS

⋅Ni +NIR

Ni

. (5.6)


Rearranging Equation 5.3 yields

FY =Ni +NIR

Ni

, (5.7)

and we see that it does not account for a difference in noise and signal gain. We

therefore generalize it according to

FT =GN

GS

⋅ FY (5.8)

by including a correction factor to account for the difference.

Similarly, Frii’s formula, given in Equation 5.5, assumes identical signal and noise

gain. We therefore derive a generalization of Frii’s formula for the three-block system

depicted in Figure 5.9. Once again referring to the definition of noise factor we have

F =Si/Ni

So/No

=Si

SiGS1GS2GS3

⋅No3 +GN3 (No2 +GN2 (No1 +GN1Ni))

Ni

(5.9)

for three-stage systems and

F1 =GN1Ni +No1

GS1Ni

(5.10)

for single stage systems. Applying Equation 5.10 to each stage in Equation 5.9 yields

F123 = F1 ⋅GN2

GS2

⋅GN3

GS3

+F2 −

GN2

GS2

GS1

⋅GN3

GS3

+F3 −

GN3

GS3

GS1GS2

, (5.11)

which generalizes Frii’s formula for a cascaded three-stage system.

Single-Branch Noise Factor Measurement

We arrive at the noise factor of our prototype mixer by first measuring the noise

factor of the entire test setup and then back-calculating the noise factor of the mixer


No1GS1

GN1

GS2GS3

GN2GN3

No2No3Si

Ni

SoNo

Figure 5.9: Three-block system from which we generalize Frii’s formula.

PXA N9030A

346B ZFL-2500+ 5135A IC INA103PCB:

(a)

PXA N9030A

346B ZFL-2500+5135A IC INA103PCB:

(b)

Figure 5.10: Test setups used for mixer noise factor measurement.

block. We make measurements of the two different system configurations depicted in

Figure 5.10. The configuration depicted in 5.10(b) is less accurate than that depicted

in 5.10(a), but serves as independent confirmation of the measurement procedure. Of

note, we must recalibrate the gain and noise factor of the amplifier between the two

setups because the signal band changes depending on the configuration. Additionally,

we must extrapolate the ENR of the noise source below its 10 MHz lower calibration

limit, which decreases the calibration accuracy of the amplifier in configuration (b)

and the spectrum analyzer in both configurations.

We test our PCB with two separate differential-to-single ended converter ICs, the


Noise Figure (dB) MAX4444 INA103

Amp-Mix-SA 37.49 37.14Mix-Amp-SA 39.50 38.68

Table 5.3: Calculated mixer noise figure.

Baseband Noise Recovered-Band Noise Difference

-109.60 dBm/Hz -115.64 dBm/Hz 6.04 dB

Table 5.4: Average noise power summed across integration windows.

MAX4444 line driver and the INA103 instrumentation amplifier, which have input-

referred noises of 25 nV /√Hz and 1 nV /

√Hz respectively. Table 5.3 presents the

noise factor of the mixer for both measurement setups and both converter ICs. We

see almost perfect noise figure agreement in configuration A, which is more accurate,

and so we take the single-channel noise figure of our mixer to be 37.49 dB.

Referring back to our link-budget analysis in Section 3.9, we recall that our design

targeted a single-channel noise figure of 31.55 dB, roughly 6 dB better than our

measured performance. We hypothesize that this discrepancy is a result of noise

amplification due to clock phase overlap.

As discussed in Section 3.7.2, each branch of the MWC makes an independent

measurement of the input spectrum and so benefits from noise averaging during signal

reconstruction. For a four channel MWC system we expect a 6 dB noise figure

improvement.

Figure 5.11 demonstrates that the noise floor of a single recovered band is lower

than that of the directly sampled output. We measure the noise averaging by in-

tegrating the background noise power for both signals, and as shown in Table 5.4,

the difference is almost exactly 6 dB, which matches predictions for noise averaging

across four measurements. Therefore, although we measure a 37.49 dB single-branch

noise figure of the MWC, we take the effective noise figure to be 31.49 dB.


100 200 300 400 500 600−140

−120

−100

−80

−60

−40

−20

Frequency Offset (kHz)

Sig

nal P

ower

(dB

m)

BasebandRecovered Band

Noise Integration Windows

Figure 5.11: Noise averaging reduces the noise floor of the recovered bands relativeto the baseband samples.

5.3.3 Nonlinearity Measurement

We use both the second and third order input-referred intercept points (IIP2, IIP3)

as standard metrics to compare our mixer’s linearity against other designs.

We measure the IIP2 by applying a 300 MHz tone to the input and using a

mixing sequence designed to target both the 300 MHz and 600 MHz bands, thus

directly capturing the second harmonic distortion of the mixer. We measure the

IIP3 by applying two-tones separated by 150 kHz in the 500 MHz band and mea-

suring the power of the intermodulation tone. Figure 5.12 provides our nonlinearity

measurements from which we calculate a 64.8 dBm IIP2 and a 14.3 dBm IIP3.

Our simulations in Section 4.4 estimated a 48.8 dBm IIP2 and a 20.13 dBm

IIP3, which are close to our measured results.

5.3.4 Comparison to the State of the Art

We compare our mixer against recently published harmonic rejection mixers in Table

5.5.


(a) (b)

Figure 5.12: IIP2 (a) and IIP3 (b) nonlinearity measurements.


Rafi [51] Sundstrom[52]

Yang[53]

Andrews [9] ThisWork

HR IFmixer

Dual-carrieraggrega-tion HR IFmixer

Widebandmixerfor SDR

Passivemixer-firstreceiver

Mixerfor theMWC

Technology nm 110 65 45 65 65Area/Branch mm2 0.034 0.48 0.352 0.75 0.069SupplyVoltage

V 2.7(mixer)1.3(clock)

1.2 1 2.5 (mixer)1.2 (base-band)

1.2

Min HR dB 52 68 55 35.4 62.8IIP2 dBm >75 — -2 56 64.8IIP3 dBm 12 — -3 25 14.3SSB NF dB 11 — 35 7 31 (37-

6)SignalPathPower/Branch

mW 59.4 23.6 17 70 22.8+3.8

Frequency MHz 100-300 390 500-1500

100-2400 0-900

Table 5.5: Comparison of our mixer to recently published harmonic rejection mixers.


Elaborating on the columns in Table 5.5, [51] presents an active rotational mixer

that achieves harmonic rejection through weighting of its phases, and uses clever

timing to avoid duty-cycle dependent mismatch that would otherwise limit its har-

monic rejection. It provides superior noise figure, however it only operates on a fixed

set of narrow bandwidths up to 300 MHz and demonstrates none of the flexibility

advantages inherent to the MWC architecture.

Reference [52] is an IF mixer that achieves harmonic rejection through 64 parallel

mixing branches. By selectively engaging a subset of these branches it produces a

nearly sinusoidal mixing waveform to achieve harmonic rejection. Additionally it

leverages its IF mixer to enable carrier aggregation across two bands. However, the

work presents only the IF stage of of an entire frontend. The noise figure, nonlinearity,

and frequency range, are set by the preceding stage, which is not reported.

Reference [53] is a wideband harmonic rejection mixer designed for software de-

fined radio applications, and so closely parallels the intended application space of the

MWC. It achieves rejection through a bank of ancillary mixers that downconvert the

undesired harmonics with opposite amplitude and sum them with the primary mixer

output. In order to cancel a wide range of harmonics these additional mixers must

operate over a correspondingly wide frequency range.

Finally, [9] is a passive mixer-first architecture that achieves blocker rejection

through an input impedance that matches only on a narrow frequency range and

an eight phase mixer to suppress the harmonics. Its passive mixer-first architecture

displays high linearity and acceptable noise figure over a wide tuning range, but only

moderate harmonic rejection.

In most specifications our mixer lies within the middle of these collected references.

Its low passive component count contributes to its small area, and its passive mixer

provides good linearity. The multiband mixer folds additional noise, contributing to

its high noise figure, but it does not have the highest noise figure presented. Our


per-branch signal path power, excludes the LO power and is dominated by the anti-

aliasing filter. It operates on a wide bandwidth and provides high harmonic rejection

against any in-band blocker on par with publications in a similar design space. Ad-

ditionally, our mixer enables the flexibility of the MWC architecture, enabling future

cognitive radio systems.

5.4 The MWC as an LTE Receiver

In this section we reapply the link-budget analysis introduced in Section 3.9. By

substituting our mixer’s measured performance parameters for our calculated design

targets we estimate the specifications that a receiver built around our prototype IC

could achieve.

We construct our receiver with the same hypothetical LNA (2.5 dB noise figure,

25 dB gain, and 15 dBm OIP3) and noiseless ADC assumed in Section 3.9. Applying

the cascaded system relation

Pin,max = 10log⎛

⎝

1GLNA

√C.F.

OIP3LNA+GLNAGmixer

√C.F.

OIP3mixer+GLNAGmixerGLPF

OIP3LPF

⎞

⎠−SNDRmin

2. (5.12)

(reproduced from Equation 3.69) we expect our MWC receiver to achieve greater

than 10 dB SNDR at input powers up -25 dBm. Likewise, applying the cascaded

system relation

Sensitivity =(((NA +NL)A2

L +NM)G2Mk∣cd∣

2 +NF)Z2F +NADC

M ∣cd∣2A2LG

2MZ

2F

W (5.13)

(reproduced from Equation 3.62) we expect our MWC receiver to achieve a sensitivity

of -96.1 dBm for a 5.6 MHz input bandwidth.

Our prototype IC easily meets the LTE input power requirements, but falls less


than 0.5 dB short of our sensitivity target (-96.5 dBm), which can be made up by

improving the LNA noise figure, increasing the LNA gain, or increasing the current

consumption in the anti-aliasing filter. These numbers demonstrate that the MWC

architecture can be used to build a receiver with performance comparable to tradi-

tional architectures that achieves unmatched flexibility.

5.5 Reception

The entire hardware system developed so far has been motivated by the flexibility

benefits of the MWC architecture. Unlike conventional architectures the MWC can

receive accept numerous signal bands, with adjustable bandwidth and arbitrary loca-

tions across the input spectrum, without a-priori knowledge of the signal locations.

Previous work, including [26] and [27], has effectively demonstrated the ability of the

MWC to identify unknown band locations. Here we demonstrate signal recovery.

We apply four input tones with four different offsets from midband in each of four

different signal bands to the measurement setup depicted in Figure 5.1. We make

four concurrent baseband measurements Y and invert

Y = C′ ⋅X′ (5.14)

(reproduced from Equation 2.13) to determine the content of the individual input

bands.

Figure 5.13 demonstrates effective signal recovery. From the baseband measure-

ments (only one set shown), we are able to separate the individual signal bands.

Ideally each extracted signal band would contain only a single tone, but imprecise

knowledge of the mixer harmonics guarantees some band-to-band crosstalk.

We produce an our estimate of the C′ matrix by pre-characterizing the mixer.


100200

300400

500600

−140

−120

−100

−80

−60

−40

−20

(kHz)

Frequency Offs

et

826 MHz654 MHz

MWC Signal Recovery

Recovered Band

368 MHz90 MHzSamplesBaseband

Sig

nal P

ower

(dB

m)

−37 dB

Figure 5.13: MWC reception demonstration.


To do so we apply two tones to the input, one in a fixed desired band and the other

swept across the input spectrum. We measure the relative gain and phase of the swept

mixer harmonic and populate C′ with these values. By calibrating the C′ matrix our

band-to-band isolation increases from 18 dB to 37 dB.

Having measured the performance metrics for the MWC and having demonstrated

signal reception in hardware we conclude our chapter on the measurements and results

of our prototype IC.

5.6 Summary

In this chapter, we overview the methodology we used to test our prototype IC and

provide our results. We began by detailing the circuit board and test equipment used

to validate our prototype. After which, we provide an annotated die photo for our

prototype IC and discuss the layout considerations.

As explained in Chapter 3, our prototype IC most closely resembles a wideband

mixer, and so we measured the mixer performance metrics of our prototype. Specif-

ically, we detailed the procedure to measure the single harmonic rejection of our

prototype for both sequence-based and delay-based techniques, and we demonstrated

on-line calibration of the digital-to-delay converter. We generalized both Frii’s for-

mula and the Y-factor method in order to measure the noise figure of our prototype,

and measured the nonlinearity of our prototype through direct measurement of the

second order harmonic and a two-tone test.

With measured performance parameters for our prototype IC we established over-

all receiver performance by adding a hypothetical LNA and applying the same cas-

caded relationships discussed in Chapter 3. And finally, we demonstrated the con-

current reception capability of our prototype by extracting four input bands from

multiple low-rate measurements and inverting the mixing matrix.

Chapter 6

Conclusions and Future Work

6.1 Summary

Cognitive radios that can flexibly adapt to the time and location-dependent availabil-

ity of wireless spectrum have the potential to alleviate the spectral shortage imposed

by the current license-based allocation system. Previous work has focused on flexible

receivers that can operate over extreme tuning ranges or aggregate multiple bands into

a single communications channel. We advanced the MWC as a cognitive radio system

that provides the desired flexibility without compromising receiver performance.

The MWC, first developed in [25], provides the flexibility desirous in cognitive ra-

dio systems in that it can operate over a wide range, dynamically adjust it’s channel

bandwidth, and aggregate multiple signal bands. Furthermore, as demonstrated in

[27], the MWC is able to quickly and efficiently sense the spectral environment to

determine the available channels and identify strong blockers. In this work, we com-

plete the picture and demonstrate LTE-quality reception robust to a single strong

blocker as might be found in a practical use-case.

We began by separating the detection and reception operations within the MWC

because the mixing sequence that optimizes the performance in each represents the

118

CHAPTER 6. CONCLUSIONS AND FUTURE WORK 119

worst case for the other. The detection step is effectively demonstrated in [27], and

in this thesis we focused on reception.

In order to receive the desired signal in the presence of a strong blocker, we

implement both sequence-based and delay-based harmonic rejection, each of which

can independently null a single strong blocker. For sequence-based nulling we add

a zero level to our mixing sequence. We use the degree of freedom that it provides

to null an undesired mixer harmonic without affecting the gain in the desired mixer

harmonics. For delay-based nulling we generalize a harmonic cancellation technique

common in power inverters—by producing a parallel mixing path with a delayed

mixing signal and summing the results we null the mixer harmonic corresponding

to the blocker band. We achieve 50.2 dB of sequence-based rejection, 59.3 dB of

delay-based rejection, and 62.8 dB of rejection when both techniques are applied to

the same blocker.

We designed our entire receiver prototype based on the sensitivity and maximum

input power requirements within the LTE specifications. With a hypothetical LNA

that provides 25 dB of gain, 2.5 dB of noise figure, and a -10 dBm IIP3 our system

provides -96.1 dBm of sensitivity and 10 dB of SNDR up to -25 dBm input power.

We thus demonstrated that the MWC is competitive with traditional receiver

topologies and additionally possesses flexibility advantages that enable cognitive radio

systems and the improved spectrum allocation efficiency that they provide.

6.2 Future Work

The presented work represents a drastic improvement in the flexibility of cognitive

radio architectures, however it remains a prototype designed to demonstrate a proof-

of-concept. There are numerous opportunities to improve its performance on the

circuit, system, and theoretical levels.


Our prototype IC focused heavily on the mixer stage of the receiver and omitted,

or simplified key blocks necessary for any production system. Future implementations

should include an on-chip LNA so as to provide a more direct comparison to other

recently published receivers. Likewise, our prototype only implements single-sideband

reception. Future work should recover both sidebands independently to fully utilize

the available bandwidth and to improve the receiver’s noise performance.

In Section 3.6.1 we discussed the sequence design algorithm implemented in this

work. Under the assumptions and design targets this algorithm works well, but

we have not been able to prove it to be optimal. Using convex analysis or other

techniques this may be possible. Additionally, we designed our sequences to null a

single harmonic whereas it may be possible to null, or severely attenuate multiple

undesired harmonics. Future work should research this possibility.

As mentioned in Section 4.1, the on-chip data storage is designed for reliability and

ease-of-test, rather than absolute performance. The 20 on-chip shift registers store

identical data and require 747.5 mW of power. In future work a single SRAM could

replace these to great effect. From [54] we estimate the power consumption of a 4 kB, 1

GHz SRAM implemented in a 65 nm process to be 2 mW . If we assume the SRAM is

constructed with 64 columns it would be able to support an 8 branch implementation

of our MWC architecture operating at 2 GHz (two sequence updates per SRAM

read operation, and four SRAM read operations per MWC branch). If we exclude

the digital circuitry required to multiplex the SRAM output, and assuming that once

multiplexed the 64 SRAM output bits are stored in shift registers local to each branch

of the MWC then the expected per-branch signal generation power consumption

decreases from 149.5 mW (see Table 5.1) to 7.7 mW (2/8+ 149.5 ⋅ 64/1332), a nearly

20 fold power reduction.


Finally, our prototype directly implements signal reception, but is unable to effec-

tively demonstrate signal detection due to data-transfer limitations in our implemen-

tation. Future work should integrate the sequence-generation and signal-detection

hardware onto the die to provide a more complete implementation.

Once these steps have been taken the MWC may be ready for a commercial

applications.

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