A Novel Joint-in-Via Flip-Chip Chip-Scale Package

186 IEEE TRANSACTIONS ON ADVANCED PACKAGING, VOL. 29, NO. 1, FEBRUARY 2006

A Novel Joint-in-Via Flip-Chip Chip-Scale PackageTeck Kheng Lee, Member, IEEE, Sam Zhang, Chee C. Wong, and A. C. Tan

Abstract—It is believed that the slower-than-expected adoptionof flip-chip (FC) packages is due to the lagging advancement insubstrate designs and technologies with front-end processes. Thislag has also resulted in the need for a costly redistribution layer(RDL), which fans out the die pads to meet the substrate designrule. This paper reviews the photographic metallization limitationof organic substrates and proposes an innovative joint-in-viaarchitecture using existing substrate technologies to improve thepad pitch resolutions. The joint-in-via architecture consolidatesthe landing pads, the microvias, and the flip-chip joint into onecommon element, thereby saving valuable substrate real estatefor high-density routing. It has been successfully conceptualizedon a flex laminate at a pad pitch of 70 m and a receiving padsize of 50 m, potentially enabling the removal of the RDL layerfor packaging. Robustness in flip-chip assembly is improved bythe joint-in-via architecture as it prevents solder bridging andallows the use of existing packaging infrastructure. A new flip-chipchip-scale package (FC-CSP) has evolved with the implementationof the joint-in-via architecture. With material optimization, theFC-CSP passes standard reliability tests, further demonstratingthe robustness of the joint-in-via technology.

Index Terms—Chip-scale package, flip-chip chip-scale package(FC-CSP), flex, joint-in-via, pitch, substrate limitations.

I. INTRODUCTION

THE microelectronics industry has long been concernedwith providing faster, smaller, and denser electronic com-

ponents. To address these challenges, electronic packages haveevolved from surface-mount technology and the peripheralfine-pitch lead approach to area array packaging technology.Flip-chip in a chip-scale package (CSP) may also be able toaddress these challenges by providing area bonding, minia-turization, and standardization of footprint with high thermaland electrical performance. This is achieved through its directflip-chip interconnect bump structure to the substrate carrier.

Flip-chip technologies require the substrate pads to corre-spond to the die pad pitch for bonding [1]. Current bumpingtechnologies are sufficient to meet the die pad pitch even withoutthe use of a redistribution layer (RDL). The bumping is notthe immediate stumbling block for flip-chip applications. Theelectroplating bumping process has demonstrated a pitch capa-bility of 75 m with a 20– m standoff for gold bump, while

Manuscript received April 12, 2004; revised November 8, 2004 andDecember 10, 2004. This development program is funded by EconomicDevelopment Board of Singapore.

T. K. Lee is with Micron Semiconductor Asia, Pte Ltd., Singapore S339942,and also with the School of Mechanical and Aerospace Engineering, NanyangTechnological University, Singapore 339942 (e-mail: [email protected]).

S. Zhang is with the School of Mechanical and Aerospace Engineering,Nanyang Technological University, Singapore 339942.

C. C. Wong is with the School of Materials Science and Engineering,Nanyang Technological University, Singapore 339942.

A. C. Tan is with Micron Semiconductor Asia, Pte Ltd., Singapore 339942.Digital Object Identifier 10.1109/TADVP.2005.850506

Fig. 1. New FC-CSP package using joint-in-via architecture.

an electroless bumping process offers a 50- m pitch with a lowstandoff of 5 m due to its isotropic growth mechanism [2]. Themechanical stud bump offers a fine pad pitch of 80 m with a40- m standoff. Even the advanced, low-cost stencil bumpingprocess offers a pad pitch capability of 200 m for most applica-tions [3]. The stencil bumping offers a lowest bumping cost as itcapitalized the printing technology in surface-mount technology(SMT) [4], but this technology faces difficulties in achievingfine-pitch bumping at reasonable yield. These are due to limi-tations [4]–[6] in the stencil materials and its processing tech-nologies, slumping of solder paste, poor position registration ofprinter, availability, and printability of fine solder paste. How-ever, the use of patterned dry film as stencil overcomes some ex-tent of these limitations for fine-pitch bumping down to 100- mpitch [7].

The pad pitch on the substrate has been identified as a diffi-cult challenge for flip-chip packaging by the 2003 InternationalTechnology Roadmap for Semiconductors: Packaging and As-sembly . This is due to the inability of substrate technologies tokeep up with the advancements of flip-chip applications. Con-sequently, a serious geometry mismatch exists between the diepads and the substrate receiving pads. For manufacturability, acostly redistribution layer (RDL) is currently used to fan outthe die pads to accommodate the substrate design rule. In par-ticular, the organic substrate design rule must be matched as itoffers a lower packaging cost as compared to ceramic or siliconsubstrates. Even with fine-pitch polymer flip-chip technologiessuch as conductive particle and conductive adhesive bonding,RDL is still needed to fan out the die pads to meet the organicsubstrate design rule. Advancements in substrate technologiesto meet the die pad pitch are important for wider adoption offlip-chip technologies and providing a cost-effective solution.

Another stumbling block for flip-chip packaging is the needfor precise flip-chip bonders in assembly. Existing die bondersdo not provide the necessary placement accuracy, requiring highcapital investments to replace them. The fluxing and precise

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IEEE TRANSACTIONS ON ADVANCED PACKAGING, VOL. 29, NO. 1, FEBRUARY 2006 187

Fig. 2. Schematic flow of different copper pattern processes.

alignment associated with flip-chip bonding also slows downassembly throughput. In addition, different flip-chip intercon-nect systems require different specifications for flip-chip infra-structures [8], making investment decisions more complex. Allof these factors increase the overall cost of flip-chip packagingand hinder the progress of flip-chip technologies.

Emerging CSPs resolve some of these limitations, but moststill rely on RDL to resolve the pad pitch concerns, as coppermetallization substrate is limited. This paper proposes an in-novative joint-in-via architecture to improve pad pitch resolu-tions on substrates. By capitalizing on the joint-in-via architec-ture, a robust flip-chip assembly was achieved with an existinglead-on-chip bonder. The FC-CSP, coded as Tf2, was success-fully conceptualized, as shown in Fig. 1. Material characteriza-tion studies were also conducted to select materials that wouldmeet the necessary package reliability specifications.

II. COPPER METALLIZATION TECHNOLOGIES

The CSP utilizes the substrate as an intermediate layer to de-couple the die from the PCB, thus allowing standardization ofthe package footprint. Organic substrates have been identified asa potential candidate for low-cost packaging [9]. This is due totheir unique photographic metallization and microvia processes,which offer further miniaturization, as well as performance andcost advantages for flip-chip packaging.

Fig. 2 illustrates the three copper metallization processes.Subtractive etching is the most commonly used approach forcopper circuitry due to its simplicity, high yield, and goodreliability. The copper pattern is generated by forming a neg-ative pattern mask on the photo-mask and then performingisotropic chemical etching. The isotropic etching results in atrapezoidal pad structure that is the end product for routingtraces and receiving bond pads. This trapezoidal structure may

impact flip-chip pitch and joint reliability. The subtractiveapproach achieves a fine-pitch design rule of m m and

m m for rigid and flexible substrates, respectively.Alternatively, advanced processes such as additive and semi-

additive can be used for copper circuitry formation with betterprofile and line/space design rules. These processes offer alarger selection of peripheral materials, such as base substratesand dielectric materials. Instead of removing copper, theseprocesses deposit copper using a pattern defined photo-mask.Thus, these techniques provide an avenue for implementationin high-density substrates.

The disadvantage of a fully additive process lies in the com-plex chemistry needed to achieve a seed layer for subsequentplating, as shown in Fig. 2. Even if this obstacle is overcomewith the use of sputtering, it still exposes the peripheral mate-rials to the harsh chemical environment and the potential forfuture reliability issues. Deposition processes such as electro-less plating are slow because they require a significant amountof time to develop the adequate copper thickness. The adhesionbetween the peripheral and seed layers is a reliability concern.The complex nature of additive processes impacts yield, relia-bility, and, thus, cost. Its complexity increases significantly asthe number of layers increase, which is one reason it has notbeen widely adopted by substrate suppliers.

Semiadditive processes utilize a uniform coating of thin con-ductive material for circuit formation. A material depositionprocess is achieved by electroplating with a patterned definedphoto-resist, as shown in Fig. 2. The electroplating process isrelatively fast and reduces the chemical exposure of the base pe-ripheral [10]. The inherent adhesion of the catalyst electro-lesscopper seed layer still exists. Both additive and semiadditivecopper formation processes offer fine-pitch circuitization withalmost vertical trace sidewalls [11]. The fine-pitch circuitiza-tion is typically achieved at the expense of copper thickness.


Fig. 3. Flip-chip technology and its pad pitch design [10].

A circuitization line/space of m m and below can beachieved with these approaches.

Additive and semiadditive processes offer vertical profilewalls with higher routing density for packaging than subtrac-tive processes. However, this does not directly translate to padpitch as the pad design and types of flip-chip interconnectjoints topple the line/space advantages offered by additive andsemiadditive processes.

III. FLIP-CHIP BOND PAD PITCH CHALLENGES

The properties and the design of substrates are critical to thereliability of flip-chip joints [12]. The types of flip-chip inter-connect systems, pad designs, and assembly techniques need tobe coupled in order to meet pad pitch and reliability require-ments.

For solder flip-chip application, the registration accuracy ofthe copper pads with the soldermask pattern must match thesolder bumping on the die. The receiving soldermask defined(SMD) pad or nonsoldermask defined (NSMD) pad define theshape of the joint structure for reliability and determine the as-sembly pitch for bonding. The presence of a soldermask is re-quired to arrest solder wicking and prevent solder bridging ofneighboring joints [4]. The soldermask, with its poor registra-tion tolerance, occupies real estate and limits the reduction ofthe bond pad pitch, as shown in Fig. 3 [13]. Offering bettercopper metallization capability than a soldermask in terms ofinterspacing, the SMD pad offers a slightly finer bond pad pitchfor flip-chip applications, as illustrated in Fig. 3. However, thispitch reduction is not significant enough for fine-pitch applica-tions. Moreover, its joint reliability is weaker, as indicated bythe low shear test data for the SMD ball pad [14].

As the pad pitch decreases, interspacing between pads mustbe minimized to maintain sufficient pad width for joint relia-bility. This poses a difficult challenge for a soldermask. Evenif the soldermask can meet the requirement, the narrow spacingwill result in bridging due to either the slumping of the solderpaste, the wetting of solder during reflow, or the placement accu-racy of the die bonder, etc. This creates difficulties in assembly,as it requires more accurate placement by the flip-chip bonder.

Polymer flip-chip technologies consist of conductive adhe-sive and conductive particle bonding. These technologies re-quire high precision alignment to bond the bumps onto the sub-strate pads. This is achieved at the expense of throughput [15].

Fig. 4. Comparison of bond pad pitch design rules with a minimum 30-�minter-pad spacing.

For assembly robustness, the top pad width has to account forthe equipment placement accuracy and reliability. As pitch de-creases, the contact area of the bumps and pads needs to bemaintained to ensure reliable joints. For example, a conduc-tive adhesive joint needs contact area that can withstand thermalstresses and conductivity, while a conductive particle joint needscontact area that can capture sufficient conductive particles forconducting.

From a substrate perspective, these polymer flip-chip tech-nologies offer better pitch capability than flip-chip soldering, asthe soldermask layer is eliminated (Fig. 3). Without the solder-mask layer, the copper metallization on the substrate will be theonly limiting factor for pad pitch. Assuming that a top pad widthof 80 m is needed for reliability, the subtractive process willprovide a pad pitch of 160 m for application due to the trape-zoidal profile. To further improve pad pitch, the copper thick-ness has to be reduced using a half-etching process, althoughthis does not result in a significant increase, as shown in Fig. 4.Even with the use of advanced metallization techniques, such asthe semiadditive process, a pad pitch of only 145 m is achieved.Due to this limitation of the copper metallization processes, itis difficult to obtain substrates for flip-chip assembly where thebonding pads are routed at a smaller pitch than 150 m [16].Consequently, substrate technologies will remain the limitingfor flip-chip packaging.

IV. JOINT-IN-VIA ARCHITECTURE

To date, a high routing density substrate can be achieved usingadvanced copper metallization and microvia on buildup sub-strates, but not pad pitch capability. Pad pitch has been a sig-nificant obstacle to wide adoption of flip-chip. A new substrateapproach is needed for flip-chip packaging that does not have the


TABLE ICOMPARISON OF RIGID AND FLEX LAMINATES

Fig. 5. Via architecture consolidates both the landing pads and through vias.

limitations of copper metallization and soldermask registration,yet is capable of meeting high routing density and low dielec-tric requirements. This forms the purpose of the research intojoint-in-via architecture.

The joint-in-via architecture relies on the use of micro-viatechnologies on flex laminates. It capitalizes on high routingdensity and versatile microvia technologies on flex substrates.Table I summarizes the flex advantages in packaging comparedto rigid substrates. A polymide base, flex offers a low dielec-tric constant for higher electrical performance [17]. It also al-lows a high processing temperature, thus, accommodating a va-riety of flip-chip interconnect systems. Moreover, flex has abetter copper metallization margin than rigid laminates. Theflex substrate is thin and compliant, making it suitable as chipcarrier, three-dimensional (3-D) carrier, and flip-chip assemblysubstrate [18], [19].

The microvia technologies can be classified based on the viaformation techniques, namely mechanical, chemical, and laservia technology [5]. Mechanical techniques such as drilling andpunching are limited in its microvia applications due to their dif-ficulties in blind via formation. The chemical techniques, i.e.,plasma, chemical etched, and photo-via formation are less flex-ibility in terms of via architecture due to their isotropic etchingnature. They are also limited in their base peripheral. The laserdrilling technique offers flexibility in generating different viastructures with different sizes and various degree of taper viawall. The CO laser has been exploited on polymide materialto generate a via architecture, as shown in Fig. 5. This uniquevia structure consolidates the landing pads, microvias, and flip-chip joint into one common element, saving valuable real estateon the FC-CSP packaging substrate. By using existing uniqueflex metallization technology, copper traces can be fabricatedto hang over the via openings. These copper traces are then

Fig. 6. Joint-in-via architecture for packaging.

Fig. 7. Schematic comparison of the via architecture with existing pad designs.

routed to the flip-chip joint in the via to the designated I/O of thepackage. The architecture does not contain any via wall metal-lization, thus eliminating additional processes and any wastingof vias, as well as reliability concerns over electrical disconti-nuity on the via wall. Bonding material such as solder is pluggedinto the via architecture through a stencil printing process. Thevia openings, acting as aperture openings on stencil, guide thesolder paste into the via. The joint-in-architecture makes dualuse of vias for interlayer connections and flip-chip soldering, asshown in Fig. 6.

The via architecture migrates the bond pad pitch design rulefrom copper metallization and soldermask registration to laservia capability. The via assists in arresting solder wicking andpreventing bridging, thereby removing the need for a solder-mask. This offers flip-chip soldering a pad pitch similar to thatof polymer flip-chip technologies, as the pad pitch relies on laservia capability instead of the copper metallization. The laser mi-crovia process allows narrow space and further pitch reduction,as shown in Fig. 7. The joint-in-via architecture offers a finerpad pitch capability than existing substrate technologies usinghalf-etching and an advanced semiadditive process. The com-parisons of the substrate design rules versus joint in via archi-tecture are illustrated in Figs. 8 and 9.

The joint-in-via architecture also removes the dependence onthe top pad width and relaxes the copper metallization process.


Fig. 8. Comparison between Cu metallization design rules versus joint-in-viaarchitecture.

Fig. 9. Graphical representation of Cu metallization design rules versusjoint-in-via architecture.

It also removes the dependence on copper thickness, thereby al-lowing the substrate to have thicker copper traces for better elec-trical performance and reliability. This eases the copper metal-lization process and enhances the robustness of the substrate re-liability. The via architecture has proven to have a pad capabilityas low as 70- m pitch, with a 50- m landing pad (Fig. 10). Thepad pitch capability is far smaller than that of any current coppermetallization and has the potential to eliminate the costly RDLprocess. This will help to significantly reduce the total cost offlip-chip packaging as summarized in Table II.

In our evaluation, the via architecture improves the assemblyyield by arresting the solder wicking and preventing solderbridging during bonding. For current pad pitch, the size of the

Fig. 10. Solder plugged into vias of 70-�m pitch.

TABLE IICOMPARISON OF COST IN FLIP-CHIP SOLDERING VERSUS. JOINT-IN-VIA

ARCHITECTURE

via can be enlarged to accommodate die placement accuracy,enabling conventional die bonder to be used for flip-chipassembly. This has been demonstrated at a 130- m pad pitchusing a conventional lead-on-chip bonder with maccuracy. Fig. 11 shows a planar view of unit by X-ray afterflip-chip bonding using an existing lead-on-chip bonder. Thehigh throughput of assembly will not be lost with the use ofexisting die bonder infrastructure compared to flip-chip bonder.

A new FC-CSP has evolved with the use of joint-in-viaarchitecture for flip-chip packaging on flex. This architectureresolves the pad pitch challenges for substrates and offers arobust assembly process with the use of existing packaginginfrastructure.

V. MATERIAL CHARACTERIZATION

Material characterizations have been performed to select thetypes of polymide flex and underfill material for FC-CSP. Threecommercially available flex materials with four underfill mate-rials are characterized. The studies emphasized material prop-erties, moisture, and interfacial behavior of the flex.

Flex properties such as degradation temperature, flexure mod-ulus and coefficient of thermal expansion (CTE) were cap-tured with the use of thermal analysis tools. The data is summa-rized in Table III. Different polymide material tested had distinctproperty differences. In thermogravimetric analysis (TGA), the


Fig. 11. X-ray pictures illustrating stud bump (black dot) aligned onto viaarchitecture (circular ring) using lead-on-chip bonder.

TABLE IIIFLEX MATERIAL PROPERTIES FROM THERMAL ANALYSIS

adhesiveless Flex A and Flex B have a higher degradation tem-perature, enabling the interposer to process up to 400 C. The

of flex is approximately 300 C, which is higher than theassembly processing temperature and reliability testing. Hence,CTE2 can be ignored in the material selection criterion. By com-parison, adhesiveless Flex A and C are preferred.

Flex packages are known for poor moisture performance.Therefore, a simple weight gain analysis was done to identifythe lowest moisture absorption of flex material. The resultobtained is summarized in Fig. 12. Of the material tested,adhesiveless Flex A and C offered a lower moisture saturationpoint with higher diffusivity and, thus, were preferred becausethe overall amount of moisture absorbed was reduced.

The adhesion strength between flex and copper laminates wasassessed for manufacturability. A simple shear test was per-formed on a ball pad to assess the adhesion strength. The sheartest data is presented in Fig. 13. Flex A and C offered a highercopper adhesion strength than Flex B. This agreed with materialsupplier’s data sheet.

To obtain good package performance, a good interfacial ad-hesion between the different packaging materials is desired. Es-pecially important is the adhesion of the underfill to the flexmaterial, as poor adhesion will result in delamination and elim-inate the advantages of underfilling. The adhesion strength be-tween the flex material with two conventional underfill materials

Fig. 12. Weight gain analysis on different flex materials.

Fig. 13. Adhesion strength of copper foils with flex materials.

(UF1, UF2) and two nonflow underfill (NF1, NF2) materialswas assessed using a standard die shear test. The die shear testwas performed at room temperature and at a heated conditionof 100 C. At room temperature, the nonflow underfill exhib-ited higher adhesion strength but upon application of heat, therewas a distinct reduction in adhesion strength. The predominantcohesive failure mode at room temperature had also shifted toadhesive-cohesive mixed mode. This may be due to the weak-ening of the high epoxy resin in the nonflow underfill. Due tothe drastic change in strength and failure mode for nonflow un-derfill, heat die shear strength was used as criteria for materialselection. This concurs with Lee [20] and Teo et al. [21] in theselection criteria for short-listing material candidates for relia-bility. The heated die shear strength data with the flex materialsis presented in Fig. 14. In general, UF1 demonstrated higher ad-hesion strength with cohesive failure mode for all the flex mate-rials tested. Therefore, conventional underfill UF1 was selectedas the underfill candidate for package reliability assessment.

From the material characterization, adhesiveless Flex A of-fered lower moisture absorption with good adhesion strengthusing copper and underfill material UF1. Therefore, it was se-lected as the material candidate for evaluating the FC-CSP.


Fig. 14. Interfacial adhesion strength assessment between underfill and flexmaterials using heated die shear test.

Fig. 15. Cross section of the FC-CSP using joint-in-via architecture.

VI. PACKAGE RELIABILITY PERFORMANCE

The joint-in-via architecture has enhanced the joint relia-bility by increasing the overall joint standoff and embeddingthe joint-in-via. This enhanced the joint reliability withoutcompromising on the package height. A package height of0.6 mm was obtained with the use of 0.25-mm die thickness.To understand the robustness of the joint-in-via technology, amechanical gold stud bump with eutectic solder was selectedas the interconnect system for assessment.

A 128-Mb SDRAM in an 8 9-mm CSP package with a diepitch of 150 m was used. A via size of 110 m was generatedon Flex A, and copper traces were routed using a m mline/space design rule. A bumped dummy die was then assem-bled using a lead-on-chip bonder, followed by a capillary under-fill process using UF1. The die was then peripherally encapsu-lated with underfill as protection, as shown in Fig. 15.

The failure criterion in these tests was based on continuityfailure and the Joint Electron Device Engineering Council’s(JEDEC’s) recommendation of more than 10 percent delamina-tion at the material interfaces by C-sam. The preliminary dataobtained from standard reliability tests is shown in Table IV.Even with the use of Au and eutectic solder, the intermetallicembrittlement survived JEDEC thermal cycling condition Band thermal shock condition D for 1,000 and 700 cycles. Thisdemonstrated the robustness of the joint-in-via architectureagainst thermal stress. With proper material selections, theFC-CSP package achieved MST L2 and passed autoclave testcondition C. The FC-CSP proved assembly robustness andpassed the standard reliability test requirements.

TABLE IVPACKAGE RELIABILITY BASED ON CONTINUITY RESISTANCE AND C-SAM FOR

8 mm � 9-mm PACKAGE

VII. FUTURE WORK

A 150- m joint-in-via architecture has been successfullydemonstrated on a single-layer flex and package as a FC-CSPusing current packaging infrastructure. Future work includesassessing the prototype of the joint-in-via architecture at a padpitch of 70 m. Development work is undergoing to study thejoint-in-via architecture on a buildup rigid laminate. Challengeslying ahead involve the compatibility of the laser ablationtechniques on rigid laminate. This microvia technique needsto achieve a good via wall profile with no cracking betweenthe intervia spacing on rigid laminates. In addition, other chal-lenges include the availability of the rigid laminate materialsagainst ionic migration between vias.

VIII. CONCLUSION

Pad pitch has been a great challenge for flip-chip packaging inthe fine-pitch arena. This has been attributed to the lagging sub-strate technologies in photographic metallization and pad de-signs for flip-chip interconnect systems.

The joint-in-via architecture shifts the current copper paddesigns to a microvia architecture using existing substrate tech-nologies. The joint-in-via architecture consolidates the landingpads, microvias, and flip-chip joint into one common element,thereby saving valuable substrate for high-density routing. Thepad-pitch resolution was improved by eliminating the need fora soldermask and reducing the interpad space using the laserablation capability. The new architecture enables a flip-chip padpitch as low as 70 m with receiving via pads of 50 m on aflex laminate. This eliminates the need of a costly RDL processwithout compromising joint reliability and package geometry.The joint-in-via architecture provides additional mileage forsubstrates to be used for flip-chip packaging. For the currentpad pitch, the joint-in-via architecture offers a sufficient padwidth for a robust assembly process using an existing diebonder. A new FC-CSP using flex has evolved with the use ofthe joint-in-via architecture.


The material characterization was performed to select the flexand underfill materials for package reliability assessment. TheFC-CSP package proved to be robust for assembly and relia-bility tests with proper material selection.

ACKNOWLEDGMENT

The authors would like to thank the staff of the Package De-sign and Material Department and Package Technology Sectionat Micron Semiconductor Asia, Pte. Ltd. for their support.

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Teck Kheng Lee (M’99) received the B.S. degreein mechanical engineering and the M.S. degree inmaterials science and engineering from the NationalUniversity of Singapore in 1995 and 1999, respec-tively. He is currently pursuing the Ph.D degree in theSchool of Mechanical and Aerospace Engineering,Nanyang Technological University, Singapore.

He has been with the semiconductor packaging in-dustry for the past ten years, working from the histor-ical package of DIP to recent flip-chip packages. Hejoined the Institute of Microelectronics (IME), Singa-

pore, in 1997, researching in the areas of MEMS, CSP, and flip-chip packaging.In 1999, he left IME and joined Micron Semiconductor Asia Pte Ltd, Singa-pore, where he worked in the areas of substrate and packaging technologies.Currently, he is a Senior Technical Member, responsible for substrate suppliermanagement and leading some research programs in the field of advanced pack-aging and material characterization. He has authored and coauthored more than10 international papers and currently holds 7 U.S patents, pending another 28U.S patents.

Mr. Lee serves as a committee member for ICMAT and is also a member ofthe IEEE CPMT and IMPAS societies.

Sam Zhang is the Director of Thin-Film Tech-nology Strategic Research Program at the School ofMechanical and Aerospace Engineering, NanyangTechnological University. He also serves as PrincipalEditor for the Journal of Materials Research. Hehas been in processing and characterization of thinfilms and coatings for more than ten years andhas authored/coauthored about 100 peer-reviewedinternational journal papers and some 80 conferencepapers, four book chapters, coedited two specialissues of Surface and Coatings Technology. In 2003,

he was conferred the title of Honorary Fellow of the Singapore Institute ofManufacturing Technology, and in 2004, Honorary Professor of the Institute ofSolid State Physics, Chinese Academy of Sciences. Since 1998, he has beenfrequently invited to present invited or plenary lectures at international Confer-ences and seminars; most recently, three times in Japan and the USA (2003)and seven times in 2004: Japan, France, Spain, and China. He is also frequentlyinvited by Singapore industries to conduct short courses and workshops. Since2001, 12 such short courses and workshops have been conducted at the com-pany premises or in university. Details of these and others of his research andpublications are easily accessible at http://www.ntu.edu.sg/home/msyzhang.


Chee C. Wong received the B.S. and Ph.D. degreesin materials science from the Massachusetts Instituteof Technology (MIT), Cambridge, in 1981 and 1985,respectively.

He was a Distinguished Member of TechnicalStaff at AT&T Bell Laboratories, Murray Hill, NJ,where he conducted and managed R&D in the areasof amorphous silicon devices for flat-panel displays,thin-film processing, and flip-chip technology formicroelectronics packaging. He then joined theInstitute of Microelectronics (IME), Singapore,

managing R&D in multichip modules for subsystem integration. At IME, Healso created a startup company, designing and implementing radio frequencyidentification tagging for the National Library Board of Singapore. His currentresearch focuses on self-assembly processes in colloidal systems for novelphotonic devices, advanced interconnection technologies for 3-D intergration,and strain relaxation phenomena in semiconductor thin films.

A. C. Tan received the Ph.D. degree in chemistryfrom the University of Auckland, Auckland, NewZealand, in 1977.

She is currently a Fellow with Micron Semicon-ductor Asia, Pte Ltd., Singapore. With about 20 yearsin the semiconductor Industry, her area of interestsincludes metal finishing, surface analysis, intercon-nects, and electronic packaging materials reliability.She has published numerous papers (conference pa-pers), two books (on soldering and plating), and con-ducted courses on surface analysis, metal finishings,

and polymeric materials for electronic device packaging within the plant andoccasionally outside the plant. She has also served as a committee member ofEPTC and SEMI Singapore for the past years.

Documents

A Novel Joint-in-Via Flip-Chip Chip-Scale Package