A novel current-mode min–max circuit

A novel current-mode min–max circuit

Amir Alikhani • Arash Ahmadi

Received: 9 September 2011 / Revised: 28 April 2012 / Accepted: 3 May 2012 / Published online: 22 May 2012

� Springer Science+Business Media, LLC 2012

Abstract This paper presents a new CMOS current mode

min–max circuit. The proposed circuit has lower number of

transistors, can detect minimum and maximum of the input

currents at the same time, shows high precision and has a

low cell area. It is designed in 0.25 lm standard CMOS

technology. Layout of the proposed structure is accom-

plished to extract the parasitic components, where all the

simulations are performed with HSPICE level49

(BSIM3v3) parameters obtained from post layout circuit

extraction.

Keywords CMOS � Current mode � Min–max circuit �WTA

1 Introduction

Analog minimum–maximum circuits, are versatile building

blocks for many applications such as analog signal pro-

cessing, fuzzy logic controllers, artificial neural networks,

high precision half-wave and full-wave rectifiers, tele-

communications, instrumentations, signal peak detectors,

demodulators etc. Analog min–max functions are obtained

from Winner-Take-All (WTA) circuits [1–4]. Due to the

simplicity, the proposed circuit in [1] has been the starting

point for many min–max circuits in fuzzy logic applica-

tions [4, 5]. Presented circuits in [6, 7] use two different

structures for min–max circuits. Using current-mode ana-

log circuit design has received wide attention due to the

supply voltage scaling down and their potential of lower

power consumption, gate oxide breakdown [8–10].

This paper presents a new current mode simultaneous

min–max selector based on CMOS technology with a

unique structure. In Sect. 2, proposed min–max is

explained. Performance analysis is accomplished in Sect. 3.

Simulation results, to verify the performance of the min–

max circuit, are presented in Sect. 4; where the simulations

are performed with HSPICE and level49 (BSIM3v3)

parameters for MOS transistors. Presented simulation

results are obtained from post-layout circuit extractions to

take into account parasitic components and secondary

effects. Simulation results confirmed the performance of

the proposed min–max. Conclusion of this work is pre-

sented in Sect. 5.

2 The proposed circuit

The proposed min–max circuit is depicted in Fig. 1.

Operation of the circuit is based on the modified-Wilson

current mirror in bottom of the Fig. 1, which creates equal

current in the branches under nodes A and B. Let us assume

one of the input currents, for instance I2 increases and

(I1 \ I2). This rise leads to a voltage increase at the node B

in comparison with the node A. Due to this difference M13

is on and M14 turns off, hence an extra current equal to

I2 - I1 is transferred to the other current mirror through

M13 and will be added to the minimum current of inputs

(I1) to produce the maximum output of the inputs which in

this case is I2. In other words, to obtain maximum of

the inputs, the absolute difference between two inputs

(|I1 - I2|) is added to the minimum current value of them.

Similarly, if (I1 [ I2), then node voltage of A increases in

comparison with the node voltage of B. Therefore, M13 is

off and M14 is on and the extra current (I1 - I2) is trans-

ferred to the current mirror through M14 and will be added

A. Alikhani (&) � A. Ahmadi

Razi University, Kermanshah, Islamic Republic of Iran

e-mail: [email protected]

123

Analog Integr Circ Sig Process (2012) 72:343–350

DOI 10.1007/s10470-012-9867-y

to the minimum current of the inputs to produces the

maximum value of the two input currents. If the input

currents are equal, two node voltages of A and B will be

equal and both transistors M13 and M14 will turn off. In

this case, both output currents of the circuit, minimum and

maximum, are equal.

Using this structure, both minimum and maximum of

the inputs are simultaneously detected. Obviously, one can

replace the modified-Wilson current mirror in Fig. 1 with a

simple current mirror. In this way, circuit can be imple-

mented with only 8 transistors which results in over 50 %

decrease in transistor usage and circuit area; however, this

will sacrifice precision of the minimum and maximum

outputs. Next section presents result simulations.

3 Performance analysis

In this section the characteristics of proposed min–max as

shown in Fig. 1 such as input and output impedance, and

dynamic range of inputs are considered.

3.1 Impedances

Input impedances are obtained for two input ports indi-

vidually. As shown in Fig. 2(a), first consider a state in

I1 [ I2, so M14 is on and DI pass through M14, the input

impedance from node A can be written as follows:

Rin7 ¼ R0in7jjRs;14 ð1Þ

where R0in7 and RS,14 are impedances from drain of M7 and

source of M14, respectively. Replacing the small signal

model for transistors in Fig. 2(b) yields:

RS14 �ro14 þ RDð Þ

1þ gm14ro14ð Þ ð2Þ

In similar way same equation obtained for RS13 (with

changing all 14 indexes with 13). RD can be written as:

RD ¼1

gm11

þ ro5 ð3Þ

Substituting (3) in (2) gives:

RS13 ¼ RS14 ¼ro14 þ ro5 þ 1

gm11

� �

1þ gm14ro14ð Þ � 2

gm14

ð4Þ

Replacing the small signal model for transistors in

Fig. 2(a) and assume all gm are equal with a reasonable

approximation, we have:

R0in7 � ro7 2þ gm ro2jjRLð Þ½ � ð5Þ

where RL is impedance of the current source of I2 that is

Fig. 1 Proposed min–max circuit

M1 M2

M7 M8

+-

RL

Vx

Ix

M14

Rs,14

Rin7

R´in7

A

RD

(a)

+-

RG

Vx

Ix Rs,13 or Rs,14

RinRD

M13 or M14

(b)

M1 M2

M7 M8

+-

RL

Vx

B

M13

R'in8

Rs,13

Rin8

RD

(c)

Fig. 2 Equivalent circuit to calculate input impedances. a Calculate

impedance from node A. b Calculate impedance from source of M13

or M14. c Calculate impedance from node B

344 Analog Integr Circ Sig Process (2012) 72:343–350

123

must be very large to minimize loading effect. So RL � ro2

then we have:

R0in7 � ro7 2þ gmro2½ � ð6Þ

Then final result can be written as:

Rin7 ¼ R0in7jjRs;14 � Rs;14 �2

gm14

ð7Þ

Similarly to other input port when I2 [ I1 and DI pass

through M13, as shown in Fig. 2(c) M13 is on and the input

impedance from node B can be written as:

Rin8 ¼ R0in8jjRs;13 ð8Þ

Assume RS,13 & 2/gm,13 and in similar way for R0in8

yields:

R0in8 ¼V 0xI0x¼

1gm8þ ro2

� �1þ gm1 r07 þ RLð Þ þ gm7r07ð Þ

1þ gm1 r07 þ RLð Þ þ gm7r07 þ gm2gm7ro2r07

ð9Þ

Assume all gm are equal and (RL � ro), then we have:

R0in8 �1

gm8þ ro2

� �gm1RL

gm1RL¼ 1

gm8

þ ro2 ð10Þ

Then final result can be written as:

Rin8 ¼ R0in8jjRs;13 � Rs;14 �2

gm13

ð11Þ

Thus in both cases the input impedances are very small

which is preferred when inputs are current. It is clear that

with increasing aspect ratio, input impedances are

improved with sacrificing die chip area and speed of

circuit. Output impedance for minimum output port

obtained as:

Rout;Min � ro 1þ gmro½ � ð12Þ

And for maximum output port obtained as:

Rout;Max � ro 1þ gmro½ �jjro 2þ gmro½ �f g ð13Þ

So in both output ports impedances are enough large to

transferring all of output currents to the load. According to

the equations, to improve the input impedances, one needs

to increase the aspect ratio and/or DC current bias. In

reverse, to improve the output impedance of the circuit, one

should decrease DC current bias. Therefore there is a

tradeoff to achieve the optimal point.

3.2 Dynamic range

For simplicity please neglect body effect, reconsider Fig. 1,

to operate transistors in saturation region, in the node B:

VB�VGS8 þ VDS2;sat ð14Þ

VB �ffiffiffiffiffi2I

b8

sþ Vth

( )�

ffiffiffiffiffi2I

b2

sð15Þ

where b = lCox (W/L) is transconductance parameter and

Vth is threshold voltage, assume b1 = b2 = �� = b12 = b,

b13 = b14 and after some works:

I� VB � Vth

2ffiffiffi2Ib

q

264

375

2

¼ X1 ð16Þ

Similarly to node A, we have:

VA�VGS1 þ VDS7;sat ð17Þ

VA �ffiffiffiffiffi2I

b1

sþ Vth

( )�

ffiffiffiffiffi2I

b7

sð18Þ

After some works:

I� VA � Vth

2ffiffiffi2Ib

q

264

375

2

¼ X2 ð19Þ

IMAX ¼ Min X1;X2ð Þ ð20Þ

To obtain the range of DI please assume I2 [ I1, then:

VC � VGS11�VDS5;sat ð21Þ

VC �

ffiffiffiffiffiffiffiffi2DI

b

sþ Vth

( )�


b

sð22Þ

DI� VC � Vthffiffi2b

qþ

ffiffi2b

q

264

375

2

ð23Þ

Replace VC with following equation:

VC ¼ VGS6 þ VGS12 ¼ffiffiffiffiffiffiffiffi2DI

b

sþ Vth þ


b

sþ Vth

¼ 2


b

sþ 2Vth ð24Þ

Then:

DI�2ffiffiffiffiffiffi2DIb

qþ 2Vth � Vthffiffi2b

qþ

ffiffi2b

q

264

375

2

ð25Þ

ffiffiffiffiffiffiffiffibDI

2

rþ b

8Vth� 0 ð26Þ

So:

DI� 0 ð27Þ

Analog Integr Circ Sig Process (2012) 72:343–350 345

123

To obtain maximum range of DI please note that the aim

of using M13 and M14 is creating an extra path for

absolute difference of the inputs current. Therefore either

these transistors work in saturation or in triode region the

extra current passes through this extra path created by M13

and M14. Accordingly, DI reaches to its maximum when

M13 or M14 are in triode region. Please consider a

situation that M13 is in triode region, therefore:

VBC �VSD13;sat ð28Þ

VB ¼ VGS1 þ VGS7

VC ¼ VGS6 þ VGS12

�ð29Þ

Substituting (29) in (28) yields:ffiffiffiffiffi2I

b

sþ Vth þ

ffiffiffiffiffi2I

b

sþ Vth

!

�ffiffiffiffiffiffiffiffi2DI

b

sþ Vth þ


b

sþ Vth

!�


b13

sð30Þ

After some mathematical manipulation:

DI� 4I

2þffiffiffiffiffib

b13

q� �2ð31Þ

Above equation shows the minimum value of DI that M13

and M14 are in triode. So the maximum range of DI is

equal to 2Idc. For instance, in this circuit we used 5 lA as

Idc for both inputs. The simulation results for maximum

dynamic range are shown in Fig. 11.

4 Simulation results

To verify performance of the proposed circuit, HSPICE

simulations were performed using TSMC 0.25 lm

LEVEL49 (BSIM3v3) CMOS process parameters. Simu-

lation results are obtained from post layout simulations

taking into account parasitic components. Figure 3 shows

Fig. 3 DC inputs applied to the proposed min–max compared with

ideal outputs

0u 1u 2u 3u 4u 5u 6u 7u 8u 9u 10u

Inputs [uA]

020nA40nA60nA80nA

180nA160nA

100nA

140nA120nA

|ER

RO

R|

0u 2u 4u 6u 8u 10u

Inputs [uA]

8nA7nA6nA5nA

10nA9nA

4nA3nA

|ER

RO

R|

(a)

(b)

Fig. 4 Output error for DC inputs. a Absolute and average error for

the minimum output. b Absolute and average error for the maximum

output

0 200n 1u 1.2u 1.4u 1.6u 1.8u 2u400n 600n 800n

0u

2u

4u

6u

8u

10uI1I2

0

200nA

300nA

400nA

500nA

100nA

|ER

RO

R|

Cur

rent

[uA

]

Time[ ]uS

0 200n 1u 1.2u 1.4u 1.6u 1.8u 2u400n 600n 800n

Time[ ]uS

(a)

(b)

Fig. 5 a Minimum output of the proposed min–max circuit for

sinusoidal inputs (Freq. I1 = 0.5 MHz and I2 = 1 MHz), b Corre-

sponding absolute and average error values


123

both min and max outputs for a range of two DC inputs

currents compared with the ideal minimum and maximum

outputs. Absolute and average error values are depicted for

both minimum and maximum outputs in Fig. 4.

Transient analysis with two different types of inputs is

also accomplished. Firstly, sinusoidal inputs with two dif-

ferent frequencies as: 0.5 MHz and 1 MHz are applied to

the inputs as I1 and I2 respectively and results are shown in

Figs. 5, 6, 7, and 8. Secondly, triangular inputs with dif-

ferent frequencies as: 1 MHz and 5 MHz as I1 and I2

respectively and results are shown in Figs. 9 and 10. It is

attainable form all these results that error of the minimum

and maximum outputs of the proposed circuit are very

small, which makes it a suitable choice for high precision

application.

To consider delay of the proposed circuit and in other

word obtained maximum speed of the proposed min–max,

pulse input is applied to the circuit. To verify the maximum

range of DI, minimum and maximum outputs for sinusoidal

inputs are shown in Fig. 11. Pulse input with frequency of

0 200n 1u 1.2u 1.4u 1.6u 1.8u 2u400n 600n 800nTime[ ]uS

0u

2u

4u

6u

8u

10uC

urre

nt [

uA]

I2I1

0 200n 1u 1.2u 1.4u 1.6u 1.8u 2u400n 600n 800n

0

100nA150nA200nA250nA

50nA

300nA350nA400nA

|ER

RO

R|

Time[ ]uS

(a)

(b)

Fig. 6 a Minimum output of the proposed min–max circuit for

sinusoidal inputs (Freq. I1 = 1 MHz and I2 = 0.5 MHz), b Corre-


0 200n 1u 1.2u 1.4u 1.6u 1.8u 2u400n 600n 800n

0u

2u

4u

6u

8u

10uI1I2

0 200n 1u 1.2u 1.4u 1.6u 1.8u 2u400n 600n 800n

0

200nA

400nA

600nA

Cur

rent

[uA

]

Time[ ]uS

|ER

RO

R|

Time[ ]uS

(a)

(b)

Fig. 7 a Maximum output of the proposed min–max circuit for

sinusoidal inputs (Freq. I1 = 0.5 MHz and I2 = 1 MHz), b Corre-


0 200n 1u 1.2u 1.4u 1.6u 1.8u 2u400n 600n 800n

0u

2u

4u

6u

8u

10u

I2I1

0 200n 1u 1.2u 1.4u 1.6u 1.8u 2u400n 600n 800n

0

200nA

400nA

600nA

100nA

300nA

500nA

700nA

|ER

RO

R|

Time [ ]uS

Time [ ]uS

Cur

rent

[uA

]

(a)

(b)

Fig. 8 a Maximum output of the proposed min–max circuit for

sinusoidal inputs (Freq. I1 = 1 MHz and I2 = 0.5 MHz), b Corre-


0 200n 1u 1.2u 1.4u 1.6u 1.8u 2u400n 600n 800n

0u

2u

4u

6u

8u

10uI1I2

0 200n 1u 1.2u 1.4u 1.6u 1.8u 2u400n 600n 800n

0u

2u

4u

6u

8u

10uI1I2

Time [ ]uS

Cur

rent

[uA

]

(a)

Cur

rent

[uA

]

(b)

Time [ ]uS

Fig. 9 a Minimum b Maximum outputs of the circuit for triangular

inputs (Freq. I1 = 1 MHz and I2 = 5 MHz)


123

50 MHz is applied, where results are shown in Fig. 12.

Maximum delay in rising or falling edge of the output is

considered as delay of the circuit, which is about 2 ns.

Simulations are also performed for different temperatures

as: 25, 50, 75 and 100 �C which results are shown in

Fig. 13. As it is attainable from simulation results, circuit

has a negligible thermal sensitivity. Layout of the min–max

cell is shown in Fig. 14. This cell occupies 17.625 lm 9

8.125 lm silicon area.

As it mentioned analog min–max circuits are versatile

building blocks that have many applications. As an

example, a high precision rectifier is implemented using

proposed min–max building block as presented in

Fig. 15(a). As it is known, using ordinary diode is not

suitable to rectify very small signals where around

threshold and sub threshold points the output will have a

considerable distortion. Nowadays, processing small sig-

nals are required in many applications such as instrumen-

tation systems, energy harvesting devices, etc. As it shown

in Fig. 15(a), one of the inputs of the proposed min–max

circuit is constant or only has DC value and the other input

is connected to the desired signal to be rectified. As it

clears only with proposed min–max and a current mirror

high precision full-wave rectifier is obtained. Result

obtained is shown in Fig. 15(b). The dimensions of used

transistors in proposed min–max circuit are

W = L = 0.63 lm.

0 200n 1u 1.2u 1.4u 1.6u 1.8u 2u400n 600n 800n0u

2u

4u

6u

8u

10uI2I1

0 200n 1u 1.2u 1.4u 1.6u 1.8u 2u400n 600n 800n

0u

2u

4u

6u

8u

10uI2I1

Cur

rent

[uA

](a)

Cur

rent

[uA

]

(b)Time [ ]uS

Time [ ]uS

Fig. 10 a Minimum, b Maximum outputs of the circuit for triangular

inputs (Freq. I1 = 5 MHz and I2 = 1 MHz)

0 200n 1u 1.2u 1.4u 1.6u 1.8u 2u400n 600n 800n0u

2u

4u

6u

8u

10uI1I2

0 200n 1u 1.2u 1.4u 1.6u 1.8u 2u400n 600n 800n0u

2u

4u

6u

8u

10uI1I2

Cur

rent

[uA

]

(a)

Cur

rent

[uA

]

(b)Time [ ]uS

Time [ ]uS

Fig. 11 a Maximum range of DI: Minimum output of the pro-

posed min–max circuit for sinusoidal inputs. b Maximum output

of the proposed min–max circuit for sinusoidal inputs (Freq. I1,

2 = 1 MHz)

0 5n 10n 15n

Time [ ]nS20n 30n25n 35n 40n 45n 50n

0u

2u

4u

6u

8u

10u

Cur

rent

[uA

]

Fig. 12 Input ideal pulse with frequency of 50 MHz

0u 1u 2u 3u 4u 5u 6u 7u 8u 9u 10u

Inputs [ uA]

10u

1u

2u

3u

4u

7u

00.5u

1.5u

2.5u

3.5u

4.5u5u

5.5u6u

6.5u

7.5u8u

8.5u9u

9.5u

Cur

rent

[uA

]

Minimum output in 25ºCMinimum output in 50ºCMinimum output in 75ºCMinimum output in 100ºC

Maximum output in 25ºCMaximum output in 50ºCMaximum output in 75ºCMaximum output in 100ºC

Ideal minimum and maximum also depicted

Fig. 13 Temperature sensitivity of the proposed circuit in 25 �C,

50 �C, 75 �C and 100 �C


123

5 Conclusions

This paper presents a new simultaneous current-mode min–

max selector in 0.25 lm CMOS standard technology.

Using only one structure to distinction min–max, low usage

device, high speed and precision and low die chip area are

specifications of the proposed circuit. Lay out of the pro-

posed structure is accomplished and obtained parasitic

components from it also take account in all of the

simulation results that confirmed performance of the pro-

posed circuit.

References

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2. Ramirez-Angulo, J., Ducoudray-Acevedo, G., Carvajal, R., &

Lopez-Martin, A. (2005). Low-voltage high-performance volt-

age-mode and current-mode WTA circuits based on flipped

voltage followers. IEEE Transactions on Circuits and Systems II:Express Briefs, 52, 420–423.

3. Prommee, P., & Chattrakun, K. (2011). CMOS WTA maximum

and minimum circuits with their applications to analog switch

and rectifiers. Microelectronics Journal, 42(1), 52–62.

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general propose neuro-fuzzy controller by using modified adap-

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Design of a mixed-signal digital CMOS fuzzy logic controller

(FLC) chip using new current mode circuits. InternationalJournal of Electronic and Communications (AEU).

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(2009). CMOS-based near zero-offset multiple inputs max–min

circuits and its applications. Analog Integrated Circuit and SignalProcessing, 61, 93–105.

8. Wilson, B. (1990). Recent developments in current conveyors

and current-mode circuits. IEE Proceedings Circuits, Devicesand Systems, 137(2), 63–77.

9. Roberts, G. W., & Sedra, A. S. (1989). All current-mode fre-

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Fig. 14 Lay out of the

proposed min–max circuit

1 : 1

Current Mirror

Input Out

Proposed Min-Max

Input1

Input2

Maximum Current

Maximum Current

Minimum Current

Power Supply 2.5V

Idc

Idc

IacInput Current

0 200n 1u 1.2u 1.4u400n 600n 800n

Time [ ]uS

0u2u4u6u8u

10u

-2u-4u-6u-8u

-10u

Cur

rent

[uA

]

(a)

(b)

Fig. 15 a Proposed block diagram for high precision full-wave

rectifier, b Output full-wave rectified signal with (amplitude = 10 lA

and Freq. = 1 MHz)


123

Amir Alikhani received the

BSc in Electronics Engineering

from Urmia University, Urmia,

Iran in 2009 and the MSc

degrees in Electronics Engi-

neering from Razi University

Kermanshah, Iran in 2011. His

current research interests

include analog integrated circuit

design and Fuzzy circuit design

and optimization.

Arash Ahmadi received the

BSc and the MSc degrees in

Electronics Engineering from

Sharif University of Technology

and Tarbiat Modares University,

Tehran, Iran, in 1993 and 1997

respectively and his PhD degree

in Electronics from University

of Southampton, United King-

dom in 2008. From 2008 to

2010, he was a Fellow

Researcher with the School of

Electronics and Computer Sci-

ence at the University of

Southampton. He is currently an

Assistant Professor in the Electronic Department, Razi University,

Kermanshah, Iran. His current research interests include analog signal

processing, high-level synthesis, electronic circuit design and opti-

mization and bio-inspired computing.


123

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A novel current-mode min–max circuit