Embed Size (px)
Citation preview
A novel approach for noise tolerant energy efficient TSPC dynamiccircuit design
Preeti Verma1 • Ajay K. Sharma2 • Arti Noor3 • Alok Kumar Mishra1 • Vinay S. Pandey4
Received: 9 August 2017 / Revised: 16 January 2019 / Accepted: 16 March 2019� Springer Science+Business Media, LLC, part of Springer Nature 2019
AbstractA dynamic circuit design technique on the basis of true single phase logic is presented in this paper to minimize leakage
power consumption. The circuit is comprehensively designed by incorporating a pair of diode transistor and a pair of
stacked transistors. Active mode as well as idle mode power consumption and delay is analysed at low and high die
temperature. 89–17% saving in power delay product is obtained for the same along with higher unity noise gain and
reduced voltage bouncing noise. The analysis of the circuit also includes the investigation of voltage variation effect,
process corner analysis and sizing effect analysis. The proposed technique is compared with several previously proposed
dynamic circuit design techniques and it is found to have best power delay product. Further, it is implemented on 32 output
decoder for enduring the technique. Comprehensive simulation using 90 nm technology in cadence specter, shows that the
proposed design vanquish conventional and other previously proposed dynamic circuit design techniques in terms of
power, delay, noise and robust against parameter and process corner variations.
Keywords Ultra low power � True single phase � Leakage � Unity noise gain � Bouncing noise
1 Introduction
Technology scaling reduces the feature size of the tran-
sistors, thus device density in integrated circuits getting
increased. High current density together with high clock
frequency, elevates capacitive coupling [1]. Thus logic
speed is reduced and the function may also malfunction
due to noise spikes in the circuit. To sustain circuit per-
formance we need to reduce threshold voltage while supply
voltage getting scaled. But the scaling of threshold voltage,
increases the leakage current exponentially. Thus, with the
technology advancement, solving the problem of high
power consumption during active as well as in idle mode of
operation is primary requisite. Dynamic logic are being
used in ample in many applications such as digital signal
processors, memory and microprocessors [2–7].
There are several dynamic logic styles such as dynamic
CMOS logic, NORA logic, Domino logic, TSPC logic etc.
Dynamic logic [8] suffer from cascading problem. N ? 1
transistors are required to implement a function utilizing
pseudo NMOS logic. It has drawback of high power con-
sumption. It also has low noise margin, charge leakage and
charge sharing issues. The domino logic [8] having struc-
ture similar to dynamic logic with addition of an inverter,
that removes the cascading problem. Delay is increased due
to the use of static inverter and only non inverting logic can
be implemented [9]. Various techniques are proposed
[10–14] to reduce the power consumption and enhance the
noise immunity of domino logic circuits.
& Preeti Verma
Ajay K. Sharma
Arti Noor
Vinay S. Pandey
1 Department of Electronics and Communication Engineering,
National Institute of Technology, Delhi 110040, India
2 I K G Punjab Technical University, Kapurthala, Jalandhar,
Punjab 144603, India
3 School of Electronics, Centre for Development of Advanced
Computing, Noida, India
4 Department of Applied Science, National Institute of
Technology, Delhi 110040, India
123
Analog Integrated Circuits and Signal Processinghttps://doi.org/10.1007/s10470-019-01444-8(0123456789().,-volV)(0123456789().,- volV)
To efficiently overcome the drawbacks of other designs,
true single phase circuit design technique was proposed.
True single phase clock (TSPC) circuits put forward fast
and fully pipelined digital circuits using single clock signal
[8, 15–17]. Due to single clock signal used, TSPC dynamic
CMOS circuit technique has no clock skew problem. TSPC
logic is more potent in implementations and individual-
ization [15]. In [18], authors have done the study of impact
of slope of clock and based on that perceptible limits and
need of clock buffer is presented. In [19] authors have
proposed a non full voltage swing TSPC logic to obtain a
better power delay product. A true single phase energy
recovery multiplier is presented in [20], that can work up to
140 MHz with built-in self test logic. To overcome the
problem of low noise immunity of dynamic circuits,
authors [21] have proposed a noise tolerant technique. This
is suitably applicable to Domino as well as TSPC logic
circuits. One more modified design is presented in [22] that
can be implemented either using P-block or N-block. Some
more design techniques are presented in [23–26] for power
and noise improvement in true single phase logic. By lit-
erature review it has been observed that a very few work
has been done on true single phase clock logic design
issues. Some authors have presented the analysis of prob-
lems associated, such as gate oxide leakage at lower
technologies, noise and charge sharing but not in much
detail. The lack of robustness to noise is the severe problem
in the designing and operation of circuit. Noise in deep
submicron technology regimes has emerged as a critical
issue that limits the reliability and integrity of the high
performance integrated circuits (ICs). Noise is becoming a
topic of study of nano scaled devices.
This paper address the designing of a low noise energy
efficient dynamic TSPC logic suitable for digital CMOS
circuits at both low and high temperatures.
Our proposed design technique has the following
advantages over the existing ones.
• Low energy consumption with minimal rise in delay.
• Improved unity noise gain.
• Losses are reduced due to lowered supply and ground
bounce noise spikes.
• Faster than other dynamic circuit design styles.
• Proposed design is efficient against temperature, supply
variations and process corner variations.
1.1 Leakage current characteristics of a singletransistor
The two major component of leakage currents are gate
oxide leakage (Igate) and subthreshold leakage current.
Submicrometer technologies insistent scaling of oxide
thickness (Tox) is needed to supply notable substantial
current drive at small supply voltages and also for sup-
pressing the effects due short channel such as as drain-
induced barrier lowering (DIBL). This results in generation
of eloquent amount of gate tunneling current (leakage)
[1–3]. The direct tunneling of electrons and holes through
the gate insulator causes the gate leakage current. In scaled
devices having oxide thickness less than 3 nm tunneling
current occurs through the trapezoidal energy barrier. This
happens when the potential drop across the oxide (Vox) is
less than the SiO2–Si conduction band energy difference
(øox).
The direct tunneling current density is expressed as [27]
IDT ¼ AgVox=Tox
� �2
exp�Bg 1 � 1 � Vox=�ox
� �3=2� �
Vox=Tox
0B@
1CA
ð1Þ
where Ag ¼ q3
16p2�huoxand Bg ¼ 4
ffiffiffiffiffi2 �m
p
3�hq u2=3ox .
Where IDT is direct tunneling current density, Vox gate
oxide potential drop, uox barrier height of the tunneling
electron, �m is the effective mass of an electron in the
conduction band of silicon and Tox is the oxide thickness.
Figure 1 shows the variation of direct tunneling current
variation for different oxide thickness with varying supply
voltage. Oxide thickness is scaled with every advancing
technology, and gate oxide leakage current (Igate) is
increasing. It has been depicted that tunneling current
increases with oxide potential and oxide thickness. We find
a dramatic rise in probability of charge carrier tunneling
and it has been found that subthreshold current increase by
a factor of 3–5 times per technology.
Figure 2 shows the variation of gate leakage current
(Igate) with supply voltage variation, for 90 nm and 45 nm
technologies. With the variation of oxide thickness
between the two technologies (90 nm and 45 nm), Igate
Fig. 1 Gate leakage current variation with potential drop across the
oxide
Analog Integrated Circuits and Signal Processing
123
increases by 19.4–25.7 times depending upon the supply
voltage applied.
Subthreshold leakage current flows during OFF state of
the device (Vgs\Vth). The subthreshold current is given
as
Isub ¼Wef
Lefl
ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiqesiNcef
2us
s#2T exp
Vgs � Vth
n#T
� �1 � exp
�Vds
#T
� �� �
ð2Þ
where Wef and Lef are the effective channel width and
length respectively, Ncef is the effective channel doping, us
is the surface potential, n is the subthreshold swing and #T
is the thermal voltage.
It has been observed from the above Eq. (2) that the
subthreshold leakage current has a exponential variation
with the threshold voltage. Inversion charge in channel is
negligible during subthreshold operation, hence the prin-
cipally depletion charge is present in the channel region
[28]. The depletion charge in channel depends on the
channel doping density. The comparison between gate
oxide leakage current and subthreshold leakage current for
an NMOS transistor (90 nm technology) at low and high
temperatures is shown in Fig. 3. At high temperature
(110 �C) subthreshold leakage current is 1.5 times higher
than gate oxide leakage current at 0.8 V supply voltage,
and at low temperature (25 �C) gate oxide leakage current
is 1.3 times higher than subthreshold leakage current
[28, 29]. During idle mode of operation or at low tem-
peratures major power consumption is caused by gate
oxide leakage and at high temperature or non idle mode
subthreshold leakage current is dominant. Thus, new
design should be efficient to deal with gate oxide leakage
and subthreshold leakage at low and high temperatures
respectively.
2 Leakage current characteristics in truesingle phase CMOS circuit
This section comprised of investigation of leakage current
characteristics in true single phase CMOS logic. It includes
the analysis of gate oxide leakage current and subthreshold
leakage currents of NMOS and PMOS devices. Further the
documentation and leakage current characteristics in a
standard true single phase circuit are tackled.
2.1 Leakage current characteristics of PMOSand NMOS devices in comparison with truesingle phase devices
Various components of gate oxide leakage and subthresh-
old leakage currents are shown in Fig. 4a, b. Figure 4a
shows the maximum gate oxide leakage states for NMOS
and PMOS devices while Fig. 4b depicts the maximum
subthreshold leakage states for both type of devices. Igc is
the current shared by source and drain terminals. Igb is very
small as compared to other three gate oxide leakage
components [28]. Igs and Igd are gate to source and gate to
drain tunneling currents respectively. The gate tunneling
leakage flows when transistor is operating above its
threshold voltage and having maximum potential differ-
ence between gate and other two terminals (i.e. source and
drain). Subthreshold current flows when the device is
operating below its threshold voltage and having highest
potential difference between source and drain branches. In
bulk CMOS technology, the probability of tunneling of
holes through gate oxide is much less than the probability
of tunneling of electrons.
Thus, the gate oxide leakage of PMOS transistor is
much less than the gate oxide leakage of NMOS transistor
of similar physical dimensions and equal gate insulator
Fig. 2 Gate oxide leakage for 90 nm and 45 nm technologies for
different oxide thickness
Fig. 3 Subthreshold and gate oxide leakage at low and high die
temperature for 45 nm technology
Analog Integrated Circuits and Signal Processing
123
potential difference, as shown in Fig. 5. Gate oxide leakage
produced by NMOS at supply voltage 1.2 V is 37.90 times
higher than the gate oxide current produced by PMOS at
same potential.
2.2 Standard true single phase logic
The standard true single phase clock (TSPC) logic is shown
in Fig. 6. This design has one precharge and one evaluation
transistor between which the logic transistors are placed
[8, 17]. The operation of the standard TSPC logic is as
follows. During non-idle mode or when clock is low, the
precharge transistor is ON and dynamic node gets charged.
This is called precharge phase. When the clock goes high
the evaluation transistor gets turned ON and the dynamic
node voltage evaluates depending upon the input data. This
phase of operation is called evaluation phase.
Problems associated with the standard design are high
power consumption, charge redistribution and dI/dt loss.
Due to high clock rate and switching of output with each
clock results into large power consumption in dynamic
circuits. To have the fast operation we cannot reduce the
clock speed but to some extent we can reduce the unfruitful
switching of output with each clock pulse. Power fluctua-
tion result in high rate of change of current (dI/dt), causing
bouncing or power supply noise. This happens due to the
self inductance of the power supply lines. Further it leads
to crosstalk noise and electromagnetic noise. Controlling
the voltage swing or current surge can reduce the peak
amplitude of ground bouncing up to some extent only. The
only way to minimize the ground bouncing to whatever the
least magnitude we wanted to achieve is by controlling dI/
dt. The rate of change of current is effectively controlled by
controlling the slew of wake-up signal. By increasing the
slew of the wake up signal we control the rate at which the
sleep device is switched on which ultimately decides the
rate of change of current that flow through it.
3 The proposed technique
3.1 Circuit description
The proposed technique shown in Fig. 7, is based on the
fact that more than one transistor off in any supply to
ground path is less leaky as compared to the path having
0
0 VDD
0
VDD
Igd
Igb
Igc
Igs
0
VDD
Isg
Ibg
Icg
Idg
VDD
0
Isub
VDD
0
VDDIsub
(a)
(b)
Fig. 4 Maximum leakage current states a gate oxide leakage,
b subthreshold leakage
Fig. 5 Gate oxide leakage of single NMOS and PMOS transistors in
45 nm technology
Vout
VDD
VDD
ø
ø
ø
Dynamic Node
Evaluation Transistor
Precharge Transistor
Pull Down NMOS NetworkInputs
Dynamic logic
within inverter
Fig. 6 Standard TSPC logic design technique
Analog Integrated Circuits and Signal Processing
123
only one OFF transistor. We have used one ultra low power
diode (ULPD) [30, 31] and two NMOS transistors to make
the circuit noise immune and low power consuming circuit.
ULP diode is place between the precharge PMOS transistor
TPP and footer evaluation transistor TEN, by placing these
transistors, leakage current from supply to ground path is
reduced along with the efficient curtailment of gate leakage
current of pulldown network and glitch roused fluctuation
at the ground level. Depending upon the input combination
the ULPD provides low resistance path for dynamic node
discharging and retains the dynamic node voltage as and
when needed.
Apart from ULPD network we have NMOS transistors
TS1 and TS2. When all the inputs are zero (logic low), the
dynamic node voltage holds logic high. However due to
subthreshold current of wide fan-in circuits, pulldown
network loose the stored charge at dynamic node. During
the impact of noise voltage spur at the gate input, dynamic
node voltage decreases thus resulting in change in output
logic level. To overcome that, NMOS transistors are con-
nected. When the dynamic node is to be discharged, the
NMOS transistor TS1 makes a charge discharging path
towards ground.
3.2 Circuit analysis
3.2.1 Precharge mode
During precharge phase, when clock is low, the precharge
PMOS transistor TPP is turned ON. The voltage at node NN
(approx 786 mV) is not sufficient to turn off the transistor
TLP, thus it runs into near cutoff region allowing a con-
ducting path to charge the dynamic node. Although the
resistance of TLP transistor is not as high as OFF state
resistance, it increases the supply to ground path resistance
and thus controlling the leakage conduction. The high
dynamic node voltage turns on the latch NMOS transistor,
thus it may lead to leakage. But due to TLN transistor the
voltage is shared and thus the conduction is reduced due to
reduced voltage at the gate terminal of the transistor. At the
same time the gate to source voltage of transistor TNE1 and
TS2 is low, keeping them in OFF state. Thus no direct
discharging path from dynamic node to ground during
precharge mode.
3.2.2 Evaluation mode
During evaluation mode when the clock is high, the eval-
uation transistor TNE1 and the stacked TS2 transistors are
turned on. Voltage at node NN goes low and the transistor
TLN moves to near cutoff region of operation. Depending
upon the logic inputs, the dynamic node voltage gets
evaluated. If any of the inputs of OR gate is high, then the
voltage node NN starts rising and we get two direct dis-
charging path towards ground. Thus the discharging time is
reduced. If all the inputs are at logic zero then the dynamic
node voltage holds high. Minor charge sharing loss due to
turning on of TS1 is compensated by the on TLP transistor.
Thus the ULPD and stacked transistors reduce the leakage
and make the circuit work faster.
3.2.3 Calculation of the dynamic power consumption
True single phase clock logic operates in two stages. First
stage is the dynamic stage and the second stage is the latch
stage. The average power consumed [32] by the first stage
can be calculated as
Pstd1 ¼ ·V2DDCdn þ mfVDDVpvCdn ð3Þ
where m ¼ tontonþtoff
, þ probability of input logic state change
in unit time. It has unit of frequency. toff and ton are the
OFF and ON time of input logic respectively. Vpv is the
output node pulse voltage and Cdn is the dynamic node
capacitance.
Power consumption by the second stage is
Pstd2 ¼ ·V2DD CL þ Clatch½ � þ mfVDDVpv CL þ Clatch½ � ð4Þ
Fig. 7 Proposed TSPC two input OR gate
Analog Integrated Circuits and Signal Processing
123
CL and Clatch are the load capacitance at latch output and
internal parasitic capacitance of latch respectively.
Let load capacitance is much larger than internal para-
sitic capacitance of the latch. Thus Eq. (4) can be rewritten
as
Pstd2 ¼ ·V2DDCL þ mfVDDVpvCL ð5Þ
Therefore, total power consumption of conventional
TSPC case is given as
Pstd ¼ ·pV2DD CL þ Cdn½ � þ mfVDDVpv CL þ Cdn½ � ð6Þ
Similarly for proposed TSPC case, power for first and
second stage will be
Pprop1 ¼ ·V2DDCdn prop þ mfVDDVpv propCdn prop
and Pprop2 ¼ ·V2DDCL þ mfVDDVpv propCL
where Vpv_prop is the noise pulse voltage at the output of
proposed design.
Total power consumed by the proposed design is given
as
Pprop ¼ Pprop1 þ Pprop2
¼ ·V2DD CL þ Cdn prop
� �þ mfVDDVpv prop CL þ Cdn prop
� �ð7Þ
Thus the total power saving by the proposed design is
Psaved ¼ Pstd � Pprop
As the noise of proposed design is very small as com-
pared to standard design thus it can be ignored in com-
parison. This will result in total saving as
Psaved ¼ ·V2DD Cdn � CL½ � þ mfVDDVpv CL þ Cdn½ �
The power saving ratio can be found as c ¼ Pstd�Pprop
Pstd
Taking Cdn � CL and Cdn_prop � CL
Thus, CL ? Cdn = CL and CL ? Cdn_prop = CL
c ¼ mfVDDVpvCL � mfVDDVpv propCL
·V2DDCL þ mfVDDVpvCL
Assuming high clock frequency (for simulation fre-
quency f = 500 MHz is taken)
The above equation is simplified as
c ¼Vpv � Vpvprop
� �CL
Vpv CL þ Cdn½ �
Ignoring the output noise of the latch circuit
c ¼ CL
CL þ Cdn
4 Results and analysis
Simulation is performed using cadence specter with
parameter as stated in Table 1. Domino OR2 gate, TSPC
and modified TSPC OR2 gate circuits are simulated to
study the performance parameters such as power, delay and
noise at low (25 �C) and high temperature (110 �C). The
detailed analysis includes the analysis of active power,
leakage power, delay, PDP, effect of supply voltage and
sizing, corner analysis along with unity noise gain. Later on
the comparison of proposed design is done with various
previously proposed dynamic circuit design techniques to
show the effectiveness of the proposed design.
4.1 Active mode power consumption and delayat low (25 �C) and high temperature (110 �C)
For every switching power consumption is given as the
product of supply voltage and active mode current. During
evaluation phase when the clock is at logic high, the buffer
output switch will be same as that of clock switching. This
results into large current flows through buffer. Figure 8,
shows the transient characteristics of standard and pro-
posed TSPC two input OR gate. In the figure the first and
second waveform are the data inputs (A, B), third is clock
input (C), fourth (V1) and fifth (V2) waveforms are the
output of standard and proposed OR gate respectively. It
can be seen from the figure, that the output of standard
dynamic gate contains a lot of noise. When output of
conventional gate is one, it gets switching pulses with
every switching clock. On the other hand the proposed
design output, does not have the switching pulses, thus
resulting in reduced power consumption and noise aware
faster design. The proposed technique generates slightly
weak logic levels. The logic high goes up to 1.03 V and the
logic low is at 41.4 mV.
Table 2 give gives the numerical values of power, delay
and power delay product of different designs at low and
high die temperature. For proposed design, 92% and 92.4%
Table 1 Parameter used for analysis
Parameter Description
Technology 90 nm
Channel length 100 nm
Min. gate width 120 nm
VDD 1 V
MOSFET model BSIM3v3
Clock duty cycle 50%
Delay calculation Between 50% points
Clock frequency 500 MHz for latch and gate both
Analog Integrated Circuits and Signal Processing
123
reduction in PDP is obtained as compared to domino OR
gate at low (25 �C) and high (110 �C) die temperatures
respectively. Similarly, PDP is reduced by 24.7% and 6.7%
compared to standard TSPC OR gate at low and high die
temperatures respectively. Bar graph of Fig. 9 represents
the PDP variation of diffident designs and it is representing
that the proposed design results in minimum PDP at both
low and high temperature. dynamic inverter implemented
in proposed design. So we get faster design as compared to
conventional domino logic and thus overall PDP is greatly
reduced.
Before all else switching power reduction was managed
by scaling of supply voltage. It is an compelling method to
reduce switching power dissipation, due to quadratic cre-
dence of the switching power on the supply voltage [29].
Figure 10 delicts the deviation of PDP with the alteration
in supply voltage, for the OR gate circuit designed with
Domino, TSPC and Proposed technique. We observe that
that the proposed OR gate has the smallest value of PDP
for all values of supply voltages. Table 3 tabularize the
numerical values of power delay product (PDP) at different
supply voltages. 71.3, 58 and 6.3% reduction in PDP is
established for proposed design, TSPC and dynamic
designs respectively, considering supply voltage reduction
from 1.0 to 0.6 V.
4.2 Sizing of ULPD leakage reducing transistors
The transistors of the ultra low power diode (ULPD) are
sized to review its effect on energy consumption of circuit.
Y-ULPD gates are obtained by sizing the width of leakage
reducing ULPD transistors TLP and TLN to Y times the
width of other transistors (PMOS and NMOS) of the cir-
cuit, subsequently. Table 4 gives the numerical values of
power and delay of the circuits with variation in size of
transistors of ULPD. We found by analysis that the energy
consumption increases as the size of the ULPD transistor is
increased from 1 to 2.5 times the size of other NMOS and
Fig. 8 Transient characteristics of standard and proposed TSPC OR
gate
Fig. 9 PDP comparison of domino, TSPC and proposed design
Fig. 10 PDP variation with varying supply voltage
Table 2 Power, delay and energy (PDP) at low (25 �C) and high (110 �C) die temperatures
Design 25 �C 110 �C
Power (9 10-8) W Delay (ps) PDP (9 10-20) J Power (9 10-8) W Delay (ps) PDP (9 10-20) J
Domino [8] 2.50 33.6 84.0 3.01 41.1 123.7
TSPC [17] 1.45 4.64 6.72 1.55 6.05 9.37
Proposed 1.09 4.65 5.06 1.23 7.11 8.74
Analog Integrated Circuits and Signal Processing
123
PMOS of the gate. Percentage saving from 93.9 to 92.3%
as compared to domino design and 24.7 to 4% when
compared to TSPC gate.
4.3 Leakage energy consumption
Precharge transistor is OFF during idle mode of circuit
operation and the dynamic node voltage depends upon the
data inputs to the circuit. For the analysis two different data
input conditions are endorsed along with high clock signal
for long span. First facet is when dynamic node voltage is
at logic high, i.e. all data inputs are at logic low and one
more is when dynamic node voltage is low, i.e. all the data
inputs are at logic high voltage level. Idle mode leakage
power consumption is documented in Table 5. Approach-
ing domino
OR gate and proposed OR gate, 72.7% and 73.9%
saving in leakage power devouring having all input set to
low logic and 34.4% and 3.16% saving with all inputs set
to logic high at low and high temperature accordingly.
Equivalently, analysing TSPC OR gate and proposed OR
gate, 66.6% and 68.2% saving for low inputs and 20.8%
and 16.3% saving for high inputs at low and high tem-
perature correspondingly. Thus the prospective design
works well at low as well as high temperature.
4.4 Corner analysis
Process corner characterizes the sovereign the parameter
variations within which the etched circuit must function
properly. The corner analysis confabulate a pertinent
method to measure circuit performance by using estab-
lished parameter values that comprise the sheer process
variations. The simulation which takes these variation into
consideration will differ from each other. There are five
apparent process corners: Slow–Slow (SS), Fast–Fast(FF),
Nominal–Nominal (NN), slow-Fast (SF), Fast-Slow(FS).
Three corners (NN, FF, SS) effect both type of devices
evenly and are called as even corners. The other two cor-
ners (FS, SF) are cause of concern and termed as skewed
corners. With skewed corners one type (NMOS/PMOS)
switches faster than the other one (PMOS/NMOS). So we
adduce to find the tolerance of design with process varia-
tions. Table 6 provides the PDP of different designs for all
process corners. Figure 11, depicts that the proposed
design shows best result for all process corners when it is
compared with other design.
Table 3 PDP with supply voltage variation
Supply voltage PDP (9 10-20) J
Domino [8] TSPC [17] Proposed
1.0 84.0 6.72 5.06
0.9 80.2 5.01 3.45
0.8 79.5 4.06 2.51
0.7 79.2 3.63 1.89
0.6 78.7 2.82 1.45
Table 4 Power, delay and PDP with ULPD sizing
OR gate type Power (9 10-8) W Delay (ps) PDP (10-20) J %saving w.r.t domino %saving w.r.t TSPC
Domino [8] 2.50 33.6 84.0 – –
TSPC [17] 1.45 4.64 6.72 92.0 –
ULPD 1.09 4.65 5.06 93.9 24.7
1.5 ULPD 1.16 4.71 5.46 93.5 18.7
2 ULPD 1.28 4.77 6.10 92.7 09.2
2.5 ULPD 1.34 4.82 6.45 92.3 04.0
Table 5 Leakage power comparison
Technique Leakage power (9 10-7) W
All inputs low All inputs high
25 �C 110 �C 25 �C 110 �C
Domino [8] 48.0 12.3 0.29 0.60
TSPC [17] 39.3 10.1 0.24 0.49
Proposed 13.1 3.21 0.19 0.41
Table 6 PDP at different process corners
OR gate type PDP (9 10-20) J
NN SS SF FS FF
Domino [8] 84.0 115.9 127.3 88.2 67.5
TSPC [17] 6.72 8.37 8.38 4.44 4.46
Proposed 5.06 6.31 7.40 2.99 3.76
Analog Integrated Circuits and Signal Processing
123
4.5 Noise analysis
4.5.1 Unity noise gain (UNG)
Unity noise gain (UNG) metric [33] is used for calculation
of noise. UNG is a method to measure leakage of the cir-
cuit. All inputs are replaced with a noise pulse having an
amplitude of fraction of supply voltage. Output noise
amplitude is analysed for different amplitude of input
noise. The amplitude of input noise pulse that can result
into similar amplitude of noise in output is termed as Unity
noise gain. Table 7 list out the UNG comparison of pro-
posed design with standard designs. Due to scanty number
of switching at the output, the proposed design shows
better noise performance. The unity noise gain of proposed
design is 23.11% and 20.34% improved as compared to
Domino logic and TSPC logic respectively.
4.5.2 Supply and ground bounce noise
As compared to static logic, the dynamic logic is more
sensitive to noise. Supply bounce and ground bounce noise
is caused by the high current pulses during switching. It is
also termed as switching noise [34]. In our proposed design
step charging of node capacitance is done, that reduces the
bouncing noise of the circuit. The analysis of switching
noise is done for both standard dynamic OR gate design
and propose OR gate design. Switching noise estimation is
done for all input combinations (11, 10, 01 and 11) and the
inductance, resistance and capacitance values for bouncing
noise analysis is taken as 7 nH, 0.6 X and 4 pF respec-
tively. Table 8 tabularizes the ground bounce and supply
bounce voltage levels. It is found from analysis that the
proposed design has smaller values of bouncing noise
voltage levels. 22.7% and 50.0% improved peak value
difference is obtained for proposed design as compared to
standard design.
4.6 Setup and hold time
Setup time is the time period prior to the clock becoming
active (edge or level) during which the flip-flop inputs must
remain stable. Hold time is the time after the clock
becomes inactive during which the flip-flop inputs must
remain stable [35]. Figure 12a, b represent the setup time
(T_setup), hold time (T_hold) and T_dcq delay of the
conventional and proposed design respectively.
4.7 Layout
Layout of all the circuits is designed using Cadence layout
design tool. For Domino, TSPC and Proposed OR Gate it is
presented in Fig. 13a–c respectively.
Post layout results for power, delay and PDP values are
listed in Table 9. PDP of proposed design is smaller by
91.14% and 10.23% as compared to Domino and TSPC OR
gate respectively.
4.8 Comparison of proposed TSPC designwith other dynamic circuit techniques
With a aim to design a energy efficient circuit, the PDP of
the design is target to be minimized along with optimizing
other performance parameters. Use of inverted clock create
skew problem, so the designs not having inverted clock are
considered good in comparison to those having inverted
clock. PDP, number of transistors and use of inverted clock
in the designs is tabulated in Table 10.
Due to reduction of consumption of power and high
speed, the energy of the proposed design is effectively
improved. Bar graph of Fig. 14 shows the PDP of proposed
design and previously reported designs. The figure depicts
the smallest value of PDP for proposed design. For a fair
Fig. 11 PDP at different corners
Table 7 Unity noise gain
(UNG) comparisionOR gate circuit UNG (mV) UNG comparison UNG ratio % improvement
Proposed 747.01 – – –
Domino [8] 606.75 747.01/606.75 1.23/1 23.11
TSPC [17] 595 747.01/595 1.25/1 20.34
Analog Integrated Circuits and Signal Processing
123
comparison all the designs are implemented with same
parameter values. Comparing proposed design with
recently proposed dynamic circuit designs [25, 26], we
achieve 17.05% and 89.45% improvement in PDP.
5 Application to decoder
The decoder is a circuit used to change the code into a set
of signals. The name its self tells the decoder because it has
the reverse of encoding. Decoders are used to get the
decimal digit corresponding to a specific input
combination.
Amongst its many uses, a decoder is widely used to
decode the particular memory location in the computer
memory system. Another application of the decoder can be
found in the control unit of the central processing unit.
Figure 15 shows a 5–32 line decoder having an enable
(E) input to control the operation of the design. The per-
formance analysis of the 32 output decoder is carried out at
500 MHz and supply voltage 1 V for 90 nm BSIM3V3
process models. Active mode power consumption and the
delay of the decoder is found to be 2.57 lW and 70.5 ps
respectively.
6 Conclusion
The proposed technique utilized stacking effect and ultra
low power diode concept. It is very fast and tested up to
500 MHz. Active power consumption has achieved about
92% and 92.4% improvement considering standard domino
OR gate at low (25 �C) and high (110 �C) die temperatures
respectively. 24.7 and 6.7% reduction in PDP is obtained as
compared to standard TSPC OR gate at low and high die
temperatures respectively. 71.3, 58 and 6.3% reduction in
PDP is found for proposed design, TSPC and domino
designs respectively for supply voltage reduction from 1.0
to 0.6 V. Comparing domino OR gate and proposed OR
gate, 72.7% and 73.9% saving in leakage power con-
sumption with all inputs set to logic low value and 34.4%
and 3.16% saving with all inputs set to logic high at low
and high temperature respectively. Similarly, comparing
TSPC OR gate and proposed OR gate, 66.6% and 68.2%
saving for low inputs and 20.8% and 16.3% saving for high
inputs at low and high temperature respectively. The pro-
posed design shows best result for all process corners when
it is compared with other design.
Fig. 12 Setup and hold time of a conventional design b proposed
design
Table 8 Bouncing voltage levels
Noise OR gate circuit Maximum peak Minimum peak Difference in peak values improvement
Supply bounce (V) TSPC [17] 1.00 0.998 0.002 50.0%
Proposed design 1.00 0.999 0.001
Ground bounce (mV) TSPC [17] 0.779 - 0.0731 1.51 22.7%
Proposed design 0.572 - 0.571 1.43
Analog Integrated Circuits and Signal Processing
123
The unity noise gain of proposed design is 23.11% and
20.34% improved as compared to Domino logic and TSPC
logic respectively. It is found from analysis that the pro-
posed design has smaller values of ground as well as
bFig. 13 Layout a, b and c
Fig. 14 Comparison with other techniques
Table 9 Post layout values of power, delay and PDP
Design Temperature (25 �C)
Power (9 10-8) W Delay (ps) PDP (9 10-20) J
Domino [8] 3.72 52.5 195.3
TSPC [17] 2.36 7.33 17.29
Proposed 1.65 9.41 15.52
Table 10 Comparision with other techniques
Reference PDP Use of inverted clock No of transistors
[6] 2.59E-17 – 06
[10] 1.78E-17 Yes 12
[11] 2.21E-17 Yes 11
[12] 1.45E-17 Yes 17
[17] 6.72E-20 No 07
[21] 2.16E-19 Yes 15
[23] 1.82E-19 No 10
[13] 6.24E-20 No 09
[14] 6.36E-19 No 10
[26] 4.84E-19 No 24
[25] 6.10E-20 Yes 09
Present 5.06E-20 No 11
Analog Integrated Circuits and Signal Processing
123
supply bounce voltage levels. 22.7.5% and 50.0%
improved peak value difference is obtained for proposed
design as compared to standard design.
An analysis of overall results and comparison with
already proposed designs identifies the proposed technique
as the best among other reported designs. The proposed
design is also used to implement 32 output line decoder. This
technique can be used for ultra low power applications such
as microprocessors, memory elements, signal processing.
References
1. Yeager, H. L., et al. (2004). Domino circuit topology. U. S. Patent
6784695
2. Gu, R. X., & Elmasry, M. I. (1999). Power dissipation analysis
and optimization for deep submicron CMOS digital circuits.
IEEE Journal of Solid-State Circuits, 31, 707–713.
3. Uyemura, J. (1993). A system perspective. Addison Wesley.
4. Gopalakrishnan, H., & Shiue, W. T. (2004). Leakage power
reduction using self bias transistor in VLSI circuits. In IEEE
workshop on microelectronics and electron devices (pp. 71–74).
5. Weste, N. H. E., Harris, D., & Banerjee, A. (2006). CMOS VLSI
design: A circuits and systems perspective (3rd ed.). Delhi:
Pearson Education.
6. Rabaey, J. M., Chandrakasan, A., & Nikolic, B. (2003). Digital
integrated circuits: A design perspective (2nd ed.). Delhi: Pear-
son Education.
7. Radhakrishnan, D. (2001). Low-voltage low-power CMOS full
adder. IEE Proceedings-Circuits, Devices and Systems, 148(1),
19–24.
8. Kang, S. M., & Leblebici, Y. (2003). CMOS digital integrated
circuits, analysis design (3rd ed.). New York: McGraw Hill.
9. Kar, R., Mandal, D., Khetan, G., & Meruva, S. (2011) Low power
VLSI circuit implementation using mixed static CMOS and
domino logic with delay elements. In IEEE-SCOReD (pp.
370–374), December 19–20, 2011.
10. Meimand, H. M., & Roy, K. (2004). Diode-footed domino: A leak-
age-tolerant high fan-in dynamic circuit design style. IEEE Trans-
actions on Circuits and Systems I: Regular Papers, 51(3), 495–503.
11. Frustaci, F., Corsonello, P., Perri, S., & Cocorullo, G. (2008).
High performance noise tolerant circuit techniques for CMOS
dynamic logic. IET Circuits, Devices and Systems, 2(6), 537–548.
12. Moradi, F., et al. (2013). Domino logic design for high perfor-
mance and leakage tolerant applications. Integration, the VLSI
Journal, 46, 247–254.
13. Dadoria, A., et al. (2015). A novel high-performance leakage-
tolerant, wide fan-in domino logic circuit in deep-submicron
technology. Circuits and Systems, 6, 103.
14. Manzoor, M., Verma, S., Singh, T., & Manzoor, M. (2016).
Various techniques to overcome noise in dynamic CMOS logic.
Indian Journal of Science and Technology. https://doi.org/10.
17485/ijst/2016/v9i22/90152.
15. Weste, N., & Eshraghian, K. (1994). Principles of CMOS VLSI
design. Boston: Addison-Wesley.
16. Rabaey, J. M., Chandrakasan, A., & Nikolic, B. (2004). Digital
integrated circuits (2nd ed.). Delhi: Prentice-Hall of India Private
Limited.
17. Ji-Ren, Y., Karlsson, I., & Svensson, C. (1987). A ture single-
phase-clock dynamic CMOS circuit technique. IEEE Journal of
Solid-State Circuits, 22, 899–901.
18. Larsson, P., & Svensson, C. (1994). Impact of clock slope on true
single phase clocked (TSPC) CMOS circuit. IEEE Journal of
Solid-State Circuits, 29(6), 723–726.
19. Cheng, K. H., & Huang, Y. C. (2000). The non-full voltage swing
TSPC (NSTSPC) logic design. IEEE 2000.
20. Kim, S., Ziesler, C. H., & Papaeftymiou, M. C. (2003). A true
single phase energy recovery multiplier. IEEE Transactions on
Very Large Scale Integration (VLSI) Systems, 11(2), 194–207.
21. Hernandez, F. M., Aranda, M. L., & Champac, V. (2006). Noise
tolerance improvement in dynamic CMOS logic circuits. IEE
Proceedings-Circuits, Devices and Systems, 153(6), 565–573.
22. Asati, A., & Chandrashekhar, (2009). A high speed pipelined
dynamic circuit implementation using modified TSPC logic
design style with improved performance. International Journal of
Recent Trends in Engineering, 1(3), 191.
23. Sharma, P., Chandel, R., & Sarkar, S. (2011). Noise tolerant
technique in super and sub-threshold region of TSPC logic.
Special Issue of IJCA-ICEICE, 5, 25–28.
24. Mitra, A. (2014). Design and analysis of low power high speed
1-bit full adder cell based on TSPC logic with multithreshold
CMOS. World Academy of Science, Engineering and Technology,
8(1), 185–188.
25. Rastogi, R., & Pandey, S. (2015). Implementing low power
dynamic adder in MTCMOS technology. In IEEE conference—
ICECS.
26. Wey, I. C., et al. (2015). Noise-tolerant dynamic CMOS circuits
design by using true single-phase clock latching technique. In-
ternational Journal of Circuit Theory and Applications, 43,
584–865.
27. Taur, Y., & Ning, T. H. (1998). Fundamentals of modern VLSI
devices. Cambridge: Cambridge University Press.
28. Yeo, K.-S., & Roy, K. (2004). Low voltage, low power VLSI
subsystems. New York: McGraw-Hill.
29. Verma, P., Sharma, A. K., et al. (2016). Estimation of leakage
power and delay in CMOS circuits using parametric variation.
Perspectives in Science, 8, 760–763.
30. Flandre, D., Bulteel, O., Gosset, G., Rue, B., & Bol, D. (2012).
Ultra-low-power analog and digital circuits and microsystems
using disruptive ultra-low-leakage design techniques. In ICCDCS
31. Verma, P., Sharma, A. K., Noor, A., & Pandey, V. S. (2017).
SDTSPC-technique for low power noise aware 1-bit full adder.
Analog Integrated Circuits and Signal Processing, 92(2),
303–314.
32. Tang, F., Zhu, K., Gan, Q., & Tang, J. G. (2008). Low-noise and
power dynamic logic circuit design based on semi-dynamic
buffer. In IEEE-ASID, 2nd international conference.
Y0 Y1 Y2 Y3 Y4 Y5
I0 I1 I2 I3 I4 E
Y28 Y29 Y30 Y31
5 to 32 Line Decoder
Fig. 15 Decoder with 32 output lines
Analog Integrated Circuits and Signal Processing
123
33. Larsson, P., & Svensson, C. (1994). Noise in digital dynamic
CMOs circuits. IEEE Journal of Solid-State Circuits, 29(6),
656–662.
34. Peiravi, A., Moradi, F., & Wisland, D. T. (2009). Leakage tol-
erant, noise immune domino logic for circuit design in the ultra
deep submicron CMOS technology for high fan-in gates. Journal
of Applied Sciences, 9(2), 392–396.
35. Oklobdzija, V. G. (2003). Clocking and clocked storage elements
in a multigiga-hertz environment. IBM Journal of Research and
Development, 47, 567–584.
Preeti Verma is Research Scho-
lar at National Institute of
Technology, Delhi. She did
M.Tech. in Microelectronics
and VLSI design from Motilal
Nehru National Institute of
Technology, Allahabad in year
2011. Her area of interest is
Integrated circuits, low power
CMOS circuit design.
Dr. Ajay K. Sharma is the Vice
Chancellor at I K G Punjab
Technical University, Punjab
since March 2018. Prior to this
he was working as Director,
National Institute of Technol-
ogy, Delhi from October 2013.
He received his BE in Elec-
tronics and Electrical Commu-
nication Engineering from
Punjab University Chandigarh,
India in 1986, M.S. in Elec-
tronics and Control from Birla
Institute of Technology (BITS),
Pilani in the year 1994 and
Ph.D. in Electronics Communication and Computer Engineering in
the year 1999. His Ph.D. thesis was on ‘‘Studies on Broadband
Optical Communication Systems and Networks’’. After serving var-
ious organizations from 1986 to 1995, he has joined National Institute
of Technology (Erstwhile Regional Engineering College) Jalandhar as
Assistant Professor in the Department of Electronics and Communi-
cation Engineering in the year 1996. From November 2001, he has
worked as Professor in the ECE department and thereafter he has
worked as Professor in Computer Science and Engineering from 2007
to 2013 in the same institute. His major areas of interest are broad-
band optical wireless communication systems and networks, disper-
sion compensation, fiber nonlinearities, optical soliton transmission,
WDM systems and networks, Radio-over-Fiber (RoF) and wireless
sensor networks and computer communication. He has published 280
research papers in the International/National Journals/Conferences
and 12 books. He has supervised 26 Ph.D. and 52 M.Tech. thesis. He
has completed two R&D projects funded by Government of India and
one project is on going. He was associated to implement the World
Bank project of 209 Million for TEQIP-I programme of the institute.
He has been appointed as member of technical Committee on Tele-
com under International Association of Science and Technology
Development (IASTD) Canada for the term 2004–2007 and he is Life
Member of Optical Society of America, USA, (LM ID-361253),
Computer Society of India, Mumbai, India, (LM-Associate:
01099298), Advanced Computing & Communications Society, Indian
Institute of Science, Bangalore, India, (L284M1100306), SPIE, USA,
(ID: 619838), Indian Society for Technical Education (I.S.T.E.), New
Delhi, India, (LM-11724), Fellow The Institution of Electronics and
Telecommunication Engineers (IETE), (F-224647).
Dr. Arti Noor is currently work-
ing as Joint Director, Centre for
development of advanced com-
puting, Noida. She has more
than 24 Years of R&D experi-
ence in the field of VLSI design
& technology characterization,
VHDL & computer program-
ming, and speech synthesis. She
obtained her Ph.D. (Electronics
and communication Engineer-
ing) in 1990 from Banaras
Hindu University, Banaras. She
started her career from CEERI,
Pilani. She was also involved in
various research development activities in CEERI, Pilani and in
CDAC, Noida. She worked on many consultancy projects for ISRO
Bangalore, IIT Delhi, ISAC Bangalore, and VSSC Trivandrum.
Alok Kumar Mishra is Research
Scholar at National Institute of
Technology, Delhi. He com-
pleted B.Tech. in Electronics
Engineering in year 2012. He
did M.Tech. in Electronics
design and Technology from
Tezpur University, 2017. His
area of interest is Integrated
circuits, low power CMOS cir-
cuit design.
Dr. Vinay S. Pandey is working
as Assistant professor at
National Institute of Technol-
ogy, Delhi. completed his M.Sc.
and Ph.d. from IIT BHU in year
2000 and 2006 respectively. His
research interest is in the area of
CMOS VLSI design, MHD
simulations, Nonlinear plasma
theory, Non-uniform transmis-
sion lines. He has research
experience of Physical research
Laboratory (Department of
pace, Gov. of India), World
Class University (WCU) Pro-
ject-under the collaboration of KAS/JAXA and NASA, at School of
Space Research, Kyung Hee University, South Korea. He is also the
referee’s of various National and International journals such as
Journal of Plasma Physics: Cambridge University Press, Astrophysics
and Space Science: Springer, Indian Journal of Physics: Springer etc.
Publisher’s Note Springer Nature remains neutral with regard to
jurisdictional claims in published maps and institutional affiliations.
Analog Integrated Circuits and Signal Processing
123
