A new switching strategy for transformer-less back-to-back cascaded H-bridge multilevel converter

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Published in IET Power ElectronicsReceived on 11th April 2013Revised on 12th January 2014Accepted on 29th January 2014doi: 10.1049/iet-pel.2013.0593

868The Institution of Engineering and Technology 2014

ISSN 1755-4535

A new switching strategy for transformer-lessback-to-back cascaded H-bridgemultilevel converterMohammadreza Miranbeigi, Hossein Iman-Eini, Mohsen Asoodar

School of Electrical and Computer Engineering, College of Engineering, University of Tehran,

North Karegar Street, P.O. Box 14395-515, Tehran, Iran

E-mail: [email protected]

Abstract: In this study, a new switching strategy is introduced for transformer-less back-to-back cascaded H-bridge (CHB)converters. The main purpose of this novel switching algorithm is to eliminate the need for an isolation stage between theline side and the load side H-bridge cells. In other words, using this strategy, the CHB rectifier and the CHB inverter can beconnected directly to each other in a back-to-back structure. The CHB rectifier regulates the intermediate DC bus voltages tothe reference value, whereas the CHB inverter generates a controllable AC voltage from the intermediate DC links. The low-frequency selective harmonic elimination technique is applied to eliminate specific harmonics from the output voltage and tominimise the switching loss. The validity and effectiveness of the proposed method are verified by simulations andexperiments on a five-level back-to-back converter.

1 Introduction

In recent years, multilevel power converters have gainedmuch attention in high-power medium-voltage applicationsbecause of their many advantages in comparison with theconventional inverters. The most prominent benefits aretheir low voltage distortion, less dv/dt, less common modenoise generation and their ability to operate under lowswitching frequencies [1].The main goal of using multilevel converters is to create a

sinusoidal voltage from distinct DC voltage levels. As thenumber of levels increases, the total harmonic distortion(THD) and dv/dt of the voltage (or current) waveformreduces more; however; increasing voltage levels will leadto a more complex control algorithm, especially for aback-to-back multilevel structure, where the intermediateDC links have to be equally balanced.The most popular and common structures of the multilevel

converters are cascaded H-bridge (CHB) [2–4], diodeclamped [5] and flying capacitor [2, 6, 7]. Recently, somenew structures have also been introduced to reduce thenumber of switching devices [8, 9]. In this paper, CHBconverter is chosen for the back-to-back structure becauseof the following advantages:

† This structure requires the least number of componentsamong all structures in order to create the same number ofvoltage levels [2].† The CHB converter is extremely modular and can be easilyextended to different voltage and power levels [2].† A considerable number of redundant switching states canbe used in modulation of a CHB converter.

† Three-phase structure is simply derived from star or deltaconnection of three single-phase CHB converters.

In practice, back-to-back CHB structures are mostly used inmedium-voltage drives [10], electric frequency changers [11]and power electronic transformers [12–14]. These convertersmay be used in high-voltage electronic tap changers [15] andhigh-voltage cycloconverters [16] as well. The mainchallenges for these converters are related to the controlsystem in the rectifier side, efficiency improvement andreduction of total size and weight. The rectifier controlsystem should control the input current to be sinusoidal andkeep the voltage balanced among the series connectedH-bridge cells. The converter size and weight must also beconsidered because of the insertion of low-frequency (ormedium frequency) isolating transformers. In this paper, notonly the isolating transformers are eliminated but also theappropriate current control and modulating strategies areselected to help overcome these problems.The proposed current control methods for the CHB

rectifiers are the hysteresis current control [17], thepredictive current control [18], and the proportion resonance(PR) control [19]. The main drawback of hysteresis currentcontrol is its variable switching frequency. The predictivecurrent control depends on system parameters, hence itsperformance degrades when the parameters of the systemchange. Nevertheless, the PR controller is independent fromsystem parameters and uses the fixed-frequency switchingmethod. It also has a simple structure and is able toeliminate the low-order harmonics. Therefore, thiscontrolling method is chosen to be used in the proposedcontrol system.

IET Power Electron., 2014, Vol. 7, Iss. 7, pp. 1868–1877doi: 10.1049/iet-pel.2013.0593

Fig. 1 Structure of five-level back-to-back CHB converter withoutany isolating device

Fig. 2 Efficiency curve

Dashed line: new proposed converter, solid line: conventional converter (thelosses of current shaping inductor and output filter have not been considered)

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Among all modulation strategies available for CHB
inverters, an appropriate one should be selected to limit theswitching loss and to increase the efficiency. The standardmodulating strategies in the CHB inverters are divided intothree categories: high-frequency pulse-width modulation(PWM), low-frequency modulation and hybrid modulationtechniques. To achieve a higher efficiency, it is necessary touse a low-frequency modulation technique such as theselective harmonic elimination (SHE) [20], nearest vectorcontrol (NVC) [21] or nearest level control (NLC) [22].Among these methods, SHE modulation is preferred sincethe NVC and NLC methods approximate the value ofoutput voltage and the switching frequency varies with thechange of modulation index.This paper introduces a new switching strategy to eliminate

isolating transformers from the structure of back-to-back CHBconverters. It is an extension of a preliminary idea [23], wherethe early idea has significantly been improved and verified byexperimental results. This idea helps to improve the efficiencyof back-to-back converters and leads to a smaller, cheaper andmore applicable structure for high-power applications. Theproposed algorithm can be extended to any number ofvoltage levels and can be implemented with a simpleprocessor. The feasibility and superiority of the proposedalgorithm are verified by several simulations andexperiments on a five-level back-to-back converter.

2 Circuit configuration

2.1 Conventional structures and difficulties

There are three typical isolating methods for implementation ofback-to-back CHB structures. The first design consists of anisolating transformer at the input of a back-to-back CHBconverter [11]. Due to the low-frequency voltage (50 Hz) ofthese transformers, the magnetic cores are usually very bulkyto prevent core saturation; furthermore, these bulky cores areusually heavy, which increases the overall weight of theback-to-back structure. The second method is to install theisolation stage at the output links of the back-to-backstructure [11]. The drawback of this design is the same as thefirst method. The third method is to use a DC/DC converterbetween two H-bridge units [12]. In this structure, by using ahigh-frequency transformer for providing the necessaryisolation, the size and weight of the structure reducesnotably. However, this structure has three power processingstages and the switching losses in the middle stage willsignificantly increase the overall loss in the converter, henceit cannot be considered as an efficient solution.

2.2 Non-isolated back-to-back CHB converter

The case study in this paper is a five-level non-isolatedback-to-back CHB converter which is shown in Fig. 1.Each CHB unit consists of four insulated gate bipolartransistor switches with anti-parallel diodes.In the demonstrated structure, the line side and load side

H-bridge cells are directly connected to each other withoutusing any isolation stage. It is also assumed that the powerswitches on the rectifier side and inverter side are switchedindependently. In this case, there are some switching states atwhich one or both of the DC link capacitors will beshort-circuited. For example, if the CHB inverter iscommanded to produce zero voltage by making −VDC on theupper cell and +VDC on the lower cell, and if the CHBrectifier is commanded to produce −2VDC by making −VDC on


both cells, the terminals of the lower capacitor will be shorted.The short-circuit (SC) path has been indicated in Fig. 1 with adashed line. Since this fault occurs in many switching states,the conventional back-to-back CHB converters cannot be usedwithout any isolating device if the line side and load sideconverters are to be switched independently.The new proposed algorithm aims to find faulty states, and

remove them, and therefore makes it possible for the twoconverters to directly connect to each other. This leads to ahigher efficiency, compared with the conventionalback-to-back CHB converters, and also makes the wholesystem smaller because of elimination of the bulkytransformer. Efficiency curve of the new converter and aconventional structure are depicted in Fig. 2. Theconventional structure which has been used for thecomparison is an electronic frequency converter proposed in[11], without parallel connection of DC links and the use oflow-frequency transformer at the output side. Thecomparison has been made for a three-phase structure withnominal voltage and power of 2.3 kV and 800 kVA. It isworth mentioning that, in the demonstrated curves, the lossesof input inductor and the output filter have not been considered.

3 Proposed control strategy for theback-to-back CHB converter

3.1 Main layout of the controller

The main challenge in the transformer-less back-to-back CHBconverter is to prevent SC conditions when the rectifier and

1869& The Institution of Engineering and Technology 2014

Fig. 3 Proposed control strategy for the back-to-back CHB converter

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the inverter control circuits modulate the line side and the loadside AC terminals, respectively. The proposed control systemto satisfy this requirement is shown in Fig. 3. In this structure,a conventional proportional–integral (PI) controller is used toset the sum of DC-link voltages to a reference value. Then,the output of PI controller is multiplied by a sinusoidalwaveform, which is in-phase with the input voltage, andmakes the reference input current. A PR controller then isused to shape the input current, that is, making it sinusoidaland in-phase with grid voltage. The PR controller has atransfer function with a resonance frequency equal to thegrid frequency. If the coefficients are chosen properly, theresults will theoretically have zero steady-state error andthe rectifier will show good dynamic performance. Extratransfer functions having the same resonance frequency asthe harmonics of grid voltage could also be added toweaken harmonics of the input current. The output ofthe current controller is a sinusoidal wave which is used asthe reference voltage for rectifier AC terminal voltage.In the inverter side, SHE-PWM is utilised to generate the

Fig. 4a Simplified structure for analysis of SC conditionsb Corresponding graph


appropriate switching angles, that is, α1, α2, …, αn for theload side H-bridge cells. Then, reference modulationwaveform (Vmod) and the inverter switching angles areentered into the ‘SC preventing algorithm’. The algorithm isused to avoid any switching state at which a SC fault willoccur and also tries to balance the DC-link capacitors. Inthe following subsections, the main idea for recognising theSC conditions and the strategy used to prevent the SCconditions are explained in detail.

3.2 Extraction of SC conditions in the back-to backCHB converter

In this part, an algorithm is introduced to find faulty states in afive-level CHB back-to-back converter. First, the situationscausing SC current to flow through the converter should berecognised. In a five-level back-to-back structure, one of thefollowing conditions leads to a SC state.

1. Terminals of the upper capacitor become shorted.


Table 1 Faulty switching configurations for a five-levelsimplified structure

Type of SC Corresponding switchnumbers

first type(upper capacitoris shorted)

1 4 5 61 4 7 82 3 5 62 3 7 8

second type(lower capacitor is shorted)

3 4 5 81 2 5 81 2 6 73 4 6 7

third type(two capacitors are connectedin opposite direction to each other)

1 4 6 72 3 5 8

Fig. 5 All possible (acceptable and unacceptable) switching statesfor a five-level back-to-back CHB structure

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2. Terminals of the lower capacitor become shorted.3. Opposite terminals of two capacitors become connected toeach other.

It is essential to know that the SC current always flowsthrough the zero impedance lines that connect the H-bridge

Fig. 6 Output voltage of the inverter according to SHE-PWM


cells. In other words, the legs connected to the source andload terminals play no role in making SC states and theycould be removed to make the analysis simpler. Thesimplified structure is shown in Fig. 4a.To analyse faulty configurations, a back-to-back structure

could be modelled with a connected graph, where electricalnodes are modelled with vertices, and every switch ismodelled with a specific edge which can be identified bythe corresponding switch number. Fig. 4b shows thecorresponding graph. Finding faulty configurations isidentical to finding specific simple paths in thedemonstrated graph. As an example, a SC configuration andits corresponding path are shown in Fig. 4.In the first SC condition discussed above, finding switching

configurations which connect electrical node ‘a’ to electricalnode ‘b’ is desired. In the corresponding graph, this isidentical to finding all simple paths connecting vertex ‘a’ tovertex ‘b’. Since the two switches in a leg should never beswitched on at the same time, the edges which belong tothe same leg, that is, {(1,3),(2,4), (5,7),(6,8)}, should not beselected simultaneously. The analysis of the second SCcondition is similar to that of the first. In the third SCcondition, all paths connecting vertex ‘a’ to vertex ‘d’ andvertex ‘b’ to vertex ‘c’ should be selected.This problem could be solved with the modified

breadth-first search algorithm [24]. After using thealgorithm, the faulty configurations are found. There are 10faulty states out of 16 possible states for a five-levelstructure. These states are shown in Table 1.With a similar strategy, the aforementioned technique

could be used for higher level converters. Based on thisanalysis, all configurations are organised in a matrix shownin Fig. 5. In this matrix, each row refers to a switching stateat the inverter side and each column refers to a switchingstate at the rectifier side. Therefore, each element denotesone specific switching configuration. Number ‘1’ indicatesthat the switching configuration is applicable, whereas,number ‘0’ shows an unusable switching configuration.This matrix will be used for the algorithm in the next part.

3.3 Short-circuit preventing algorithm

Before the explanation of the algorithm, the term of ‘ith zone’is defined. In fact, the ith zone determines the interval inwhich the inverter voltage phase is between αi and αi+1,that is, αi≤ ωt≤ αi+1. Therefore, according to Fig. 6, in thisalgorithm, 25 zones could be defined. Since the inverter


Fig. 7 SC preventing algorithm flowchart

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switching frequency is low compared with the rectifier, oneswitching period of inverter consists of numerous switchingperiods of rectifier. Hence, choosing a proper switchingstate of the inverter plays a vital role in the algorithm.Hereafter, the algorithm is explained.In the proposed algorithm, the inverter switching angles are
distinguished by the index ‘n’, where α0 is considered to bezero, as shown in Fig. 6. The values of DC-link voltages,sign of input current and output current, and the referencemodulation waveform produced by PR controller are givento the algorithm to regulate the DC-link voltages and togenerate the rectifier switching commands. Subsequently,the reference phase, that is, ωt, and the inverter switchingangles (α1, α2, …, αn) are entered into the algorithm, usedfor inverter switching commands. Note that the outputvoltage is in-phase with the input voltage. The reason willbe discussed later. Because of low-frequency modulation ofthe inverter, its switching state is determined prior to theswitching state of the rectifier. After receiving input values,the zone of the inverter is found. Then, for the current zoneof the inverter, the set of voltage levels which is producedby the rectifier is chosen. For example, if the inverter zoneis 7, the set of voltage levels for the rectifier will be +2Vdc

and +Vdc. If the inverter zone is 4, the set of voltage levelswill be 0 and +Vdc, and so on. Knowing this fact,switching commands of the inverter will be determined ineach zone according to the following priorities:

1. Since it is known which voltage levels will be produced bythe rectifier in the ith zone, inverter switching states whichhave at least one safe configuration for every of thesevoltage levels are chosen2. If there is more than one inverter switching state whichsatisfy condition 1, then those which give the rectifier moresafe configurations will be chosen. Referring to Fig. 5, itmeans the rows which have more ‘1’ element (or acceptableconfiguration) for the aforementioned rectifier voltage levelsare selected. It gives the rectifier more freedom to changeits switching states, and therefore the rectifier will have ahigher capability to balance the DC links.3. If there are two or more inverter states which exactlyproduce the same amount of safe configurations for therectifier, then the balancing capability will be the criterion.Based on the voltage of DC links and the sign of loadcurrent, the one which helps better to balance the DC linkswill be chosen.

As an example, consider α1≤ ωt≤ α2. In this case, theinverter zone is 2, and the set of voltage levels which therectifier will produce is {0, + Vdc}. Referring to Fig. 5, allof four inverter configurations are candidate for this zone,that is, {{(1,4), (3,4)}, {(1,4), (1,2)}, {(1,2), (1,4)}, {(3,4),(1,4)}}. Set of {{(1,4), (3,4)}, {(1,2), (1,4)}} are candidateaccording to second condition, since they give morefreedom to the rectifier to produce zero voltage. Nowcondition 3 should be checked for them. If Vc1≤ Vc2, and ILis positive, then {(1,4), (3,4)} should be selected, since thisconfiguration charges the upper capacitor and helps systemto balance the DC links more effectively compared with theother configuration. After the selection of inverter switchingstate, it remains constant during the period, and rectifierswitching states will be chosen based on this inverterconfiguration, as will be explained in following.The rectifier modulation technique used in this paper is

based on the algorithm explained in [25]. The algorithmsuggests that in order to balance the voltage of two loads


and decrease the effective switching frequency of rectifier,hybrid modulation could be used. In the aforementionedmodulation, at the beginning of each switching period, onlyone cell works in the PWM mode, and other cells produceconstant ‘ +Vdc’, ‘−Vdc’ or zero voltage. The mode of cellsis chosen based on the sign of input current and the DClink voltages to achieve the best state of voltage balancing.The same modulation technique is used here. However, the

switching commands of the rectifier depend on theconfiguration of the inverter, and they should be chosencarefully, so that no SC state happens. For example, if theinverter configuration is {(1,4), (3,4)}, and if cell 1 and cell


Table 2 Selected parameters for the simulation andexperimental investigation

Parameters Symbol Value

grid voltage Vrms-phase 80 Vnominal active power P 156 Wnominal reactive power Q 0line frequency fsource 50 Hztotal DC bus voltage VDC 120 Vinput inductance L 8 mHDC bus capacitor C 3 mFeffective rectifier switching frequency fsw 1.25 kHzsampling period TS 60 μs

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2 are forced to produce ‘0’ and ‘PWM+’, respectively, thenset of {{(1,2), (1,4)}, {(1,2), (1,2)}} is a safe configurationto produce the waveform. The whole procedure issummarised in the flowchart shown in Fig. 7. Note that thesign of ‘Iin’ and ‘IL’, that is, ‘the direction of input and loadcurrent’, is needed to determine the power flow directionwhich plays the key role for balancing [25]. However, inunity power factor applications, input voltage and inputcurrent are in phase. Hence, the sign of ‘input voltage’could be used instead of the input current, and its signwould not be necessary for the algorithm.
3.4 Safe operating margins

One remaining question is that if there is always a safeconfiguration in all of the states mentioned above or not.Investigation of all of the switching states shows that forevery inverter voltage level, there exists at least one saferectifier state when the difference between voltage levels oftwo converters are not beyond 2Vdc. For example, if theinverter generates the voltage level of +Vdc, there is at leastone safe switching state when the rectifier generates +2Vdc, +Vdc, 0 or −Vdc. This fact could be easily found outfrom Fig. 5. If the inverter is forced to produce alow-frequency waveform, like the algorithm used in thispaper, the converter is limited to produce an output voltagein-phase with the input voltage, in a limited range ofmodulation index. However, if a high-frequencymodulation, for example, sinusodial PWM, is used for bothof the converters, the inverter will be able to operate in awider range. That is because at the beginning of eachswitching period, both rectifier and inverter states couldchange simultaneously and more freedom will be given tothe switching states. In this case, the converter will be ableto produce wider range of modulation index for the inverterside. Also, the phase of output voltage could change fromthe phase of input voltage up to some degree. This factcould be more elaborated by Fig. 8.In Fig. 8, horizontal axis shows the voltage level of

rectifier, whereas the vertical axis indicates the voltage levelof the inverter. All of the permissible voltage levels areshown by points. As it could be seen, the points whichrepresent more than two voltage level difference (2Vdc)between two converters are not selected. In single-phaseapplications, every point between two voltage levels, that is,Vk ≤ V ∗

ab ≤ Vk+1, could be synthesised by these voltagelevels. Knowing this fact, a permissible range formodulation index and phase shift could be found. This is

Fig. 8 Permissible area in the plane of inverter-rectifier voltagelevel


shown by the dashed-line area in Fig. 8. As an example, ifthe reference modulation waveforms for rectifier andinverter are 0.5sin(ωt) and sin(ωt−(π/3)), respectively, thenthe indicated curve will be the representation of thewaveforms in the inverter-rectifier voltage level plane. As itcould be seen, the waveform is in the specified area,therefore all of the switching states could be selected insuch a way that no SC state happens.

4 Simulation results

In this part, the behaviour of the new control strategy andswitching algorithm is verified by simulations on afive-level back-to-back CHB converter. The systemparameters used in simulations are identical to thecorresponding experimental system parameters and areshown in Table 2.The first simulation investigates the steady state behaviour

of the converter. In this study, the load side converter shouldeliminate the 5th, 7th, 11th, 13th and 17th harmonics from theoutput voltage, whereas the line side converter shouldperform the active rectification. Fig. 9 shows the obtainedresults for the input voltage, input current and outputvoltage of the converter. The harmonic spectrum and THD

Fig. 9 Steady-state behaviour of the back-to-back CHB converter

a Input voltage and current, where input voltage has been scaled downb Output voltage of the inverterc Harmonic spectrum and THD of input current


Fig. 10 Investigation of the back-to-back converter under loadstep

a Input currentb DC bus voltage of first cellc DC bus voltage of second celld Output voltage

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of input current is calculated and shown in Fig. 9c, and thecorresponding power factor is derived as 0.9928. Theobtained results prove that the input current is sinusoidaland in-phase with the input voltage. The FFT analysis ofoutput voltage confirms that the selected harmonics havebeen completely removed. It is worth mentioning that thetriplen harmonics will be removed automatically in the loadcurrent of a three-phase balanced system. So, it is notnecessary to remove such harmonics in the generated output

Fig. 11 Investigation of the back-to-back converter behaviourunder voltage sag condition

a Input voltageb DC bus voltage of first cellc DC bus voltage of second cell


voltage by the inverter. To investigate the quality of theoutput current, three single-phase back-to-back convertersbecome connected to each other, supplying a three-phaseresistive load. A low-pass level control filter is used beforethe load to mitigate higher-order harmonics. The result isthat the THD of output current reduces to 4.3%, whichsatisfies IEEE-519 standard.To evaluate the dynamic performance of the system, some

dynamic tests have also been done. Fig. 10 shows thedynamic behaviour of the system when the load value ischanged in a stepwise manner. In this test, the load value isreduced from 50 to 25 Ω at t = 0.4 s, and restored to theinitial value at t = 0.7 s. As it is seen, the input current issinusoidal during the period of analysis, and the DC-link

Fig. 12 Steady-state behaviour of the converter

a Input voltage, input current and output voltageb Voltage and current waveforms of switch S3 (belonging to upper cell) in therectifier and inverterc Harmonic spectrum and THD of input current


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voltages remain constant; hence there is no change in theoutput voltage. This simulation confirms correct behaviourof this back-to-back converter in case of abrupt load changes.In practice, the input voltage magnitude could reduce
because of some faults in the electrical networks. In thenext simulation, the performance of the converter undervoltage sag conditions is evaluated. In this test, the inputvoltage is stepped down from 80 to 54 V, and returned to80 V after 0.6 s. As Fig. 11 demonstrates, the system is ableto keep the DC-link voltages constant under voltage sagconditions. Hence, the output voltage remains constant andcorrect operation of the converter is confirmed.

5 Experimental results

To verify the validity of the proposed control strategy, thesimulation results are checked by experiments on asingle-phase five-level back-to-back CHB converter. Thecircuit configuration of the hardware prototype employs thesame parameters in Table 2. In this prototype, aTMS-320F28335 DSP processor is employed to performthe control functions and to generate the switching signalsfor the H-bridge cells. The switches used in the H-bridgecells are power MOSFETs IRFP260N.

Fig. 13 Performance of the converter under different loads

a Input current, input voltage, output current and output voltage underinductive loadb Input current, input voltage, output current and output voltage undernon-linear load


The DSP board is installed on an extension board whichconsists of three-state buffers between the DSP I/Os and theH-bridge cells. For each H-bridge cell, two gate signals aregenerated by the DSP and each one is applied to ahalf-bridge driver (e.g. IR2104) located in the H-bridge cell.Then, the half-bridge driver generates two complementarysignals for the power switches in a leg. The switchingcommands are finally applied to the power switches by the

Fig. 14 Dynamic behaviour of the converter

a Load current, DC bus voltage and load voltage under load stepb Input voltage, DC bus voltage of first and second cells under voltage sagconditionc DC bust voltage of first and second cells and current of DC load inserted tothe upper link to investigate the voltage balancing mechanism


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appropriate optcouplers (e.g. HCPL3120). The necessaryvoltage and current feedbacks are sampled by the analogueisolation amplifiers (e.g. HCPL7840) and the Hal effectcurrent sensors (e.g. LTS25-NP), respectively.The first experiment verifies the steady state behaviour of
the converter same as the first simulation. The obtainedresults in Fig. 12a demonstrate the input voltage, inputcurrent and output voltage of the converter, respectively. Toverify the stress of power switches, the voltage and currentwaveforms of two switches, for example, switch S3 inupper cell of both rectifier and inverter converters areshown in Fig. 12b. It is seen that the voltage of each switchis limited to the voltage of DC-link capacitor, that is, 60 V.Moreover, the frequency of power switch in the inverter ismuch lower than the rectifier switch because of SHEmodulation. Fig. 12c shows the harmonic spectrum andTHD of input current. The power factor is also measuredand equals to 0.9908. The difference of harmonicamplitudes in simulation and experimental results isbecause of following reasons:

1. The source voltage is not harmonic-free, unlike the voltagesource in the SIMULINK.2. Current shaping inductor has non-linear behaviour inpractice.3. Limitation of sampling frequency of DSP.

The next experiment investigates the behaviour ofconverter when it is connected to inductive and non-linearloads. The inductive load consists of a 30 Ω resistor inseries with a 10 mH inductor, and the non-linear loadconsists of a diode bridge connected in parallel with a 1 mFcapacitor and a 30 Ω resistor. The results are shown inFigs. 13a and b for inductive and non-linear loads,respectively. It can be seen that the input current remainssinusoidal and in-phase with the input voltage, although theload is inductive or non-linear. It is worth noting that, inthe experiments, the input voltage is provided by anauto-transformer which has considerable series impedance,and therefore a little distortion can be seen at the inputvoltage when the load is inductive or non-linear. However,this distortion is removed when the input voltage isprovided by a low-impedance source.Fig. 14 evaluates the converter performance under dynamic

conditions. Fig. 14a shows the waveforms under stepwiseload change and Fig. 14b shows the behaviour of converterunder voltage sag conditions. Besides, to examine thevoltage balancing scheme, a 120 Ω resistor is connected (ina stepwise manner) to one of the DC links, and the resultsare shown in Fig. 14c. All experimental results are in goodagreement with the simulation results and confirm stableoperation of the system under static and dynamicconditions. Moreover, DC-link voltages remain constant,although a 120 Ω resistor is connected to one of the DClinks. This result confirms the validity of voltage balancingmechanism in the back-to-back converter.

6 Conclusions

In this paper, a new switching algorithm was proposed fortransformer-less back-to-back CHB converters whichremoves the necessity for an isolation stage. Compared withthe conventional multilevel structures, this circuit has acheaper and simpler structure. This new algorithm alsooffers the control of the load side converter with a


low-frequency modulation technique to achieve a higherefficiency. Moreover, the line side converter is controlledactively to obtain voltage balance among the DC-linkcapacitors and to shape the input current to be in sinusoidalform. The new algorithm was applied to a five-levelback-to-back converter and its validity was confirmed bysimulation and experimental results in both steady state anddynamic conditions. It is worth mentioning that althoughthis structure has several advantages over traditionalback-to-back CHB converters, it has its own limits; in thisstructure the frequency of input and output voltage to be thesame and the phase of output voltage cannot increase froma specific value compared with the input voltage. Theselimitations restrict the use of this structure in someapplications like constant v/f motor drives. Nevertheless, infixed-frequency applications such as power electronictransformers and high-power voltage regulators, thisstructure is very promising and can be utilised.

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Documents

A new switching strategy for transformer-less back-to-back cascaded H-bridge multilevel converter