CORRESPONDENCE

vertex 1 as an example, which has the following operations:

1 0001 1 0001

3 0011, 0011 3 0011, 0011

Then

1 0001 1 0001

5 0101, 0101 5 0101, 0101

Then

1 0001 1 0001, 0001, 0001

9 1001,1001 3 001IX, 0011x5 0101 X, 0101 x9 1001X, 1001X

Here only three more comparisons are needed than the operationson the 0-cube for the same vertex in the classical method. Hence,the additional operations to accomplish Table VII are only 12 morecomparisons than on the 0-cube with the classical method, Note thatthe additional operations needed in this method must also be neededin the higher cube tables in the classical method, but the reverse isnot true. It is clear that this additional number of operations isfewer than those needed in the higher cube tables.Thus we conclude that the advantages of the algorithm presented

in this correspondence are as follows.1) The operation sequence to find the prime implicant is unique.2) It is faster than the classical tabular method.3) It is suitable for programming.

ACKNOWLEDGMENTThe author is grateful to referee A for his valuable suggestions to

revise this correspondence.REFERENCES

[11 M. Karnaugh, "The map method for synthesis of combinationallogic circuits," AIEE Trans., vol. 72, pp. 593-599, Nov. 1953.

[21 E. J. McCluskey, Jr., "Minimization of Boolean functions,;" BellSyst. Tech. J., vol. 35, pp. 1417-1444, Nov. 1956.

131 A. B. Marcovitz and C. M. Shub, "Am improved algorithm for thesimplification of switching functions using unique identifiers on aKarnaugh map," IEEE Trans. Comput., vol. C-18, pp. 376-378,Apr. 1969.

[4] W. V. Quine, "A way to simplify truth function," Amer. Math.Monthly, vol. 62, pp. 627-631, Nov. 1955.

[51 --, "On cores and prime implicants of truth functions," Amer.Math. Monthly, vol. 66, pp. 755-760, Nov. 1959.

[61 J. P. Roth and R. M. Karp, "Minimization over Boolean graphs,"IBM J. Res. Develop., vol. 6, no. 2, pp. 227-238, 1962.

[71 E. W. Samson and B. E. Mills, "Circuit minimization: Algebra andalgorithms for new Boolean canonical expressions," Air ForceCambridge Res. Center, Cambridge, Mass., Tech. Rep. 54-21, Apr.1954.

[81 E. W. Veitch, "A chart method for simplifying truth functions," inProc. Ass. Comput. Mach., May 1952, pp. 127-133.

Index Terms-Code conversion, natural binary code, reflectedbinary code, signed digit representation.

In the following, a new explanation is given of the reflected binarycode in relation with the natural binary (NB) code, leading to abetter insight in the reflected binary (RB) code and its implementa-tion in counters and code converters.For a number of applications it is a disadvantage of the NB code

that successive code words differ in general in a number of bits(e.g., stepping from 0111 to 1000 involves a stage change of all fourbits). This means that with different operating speeds of the switch-ing elements, any transient state can occur.

Progressive codes in which successive words differ in one bit only,do not have this disadvantage. Differences in operating speed of theswitching elements can only cause a small shift in the moment ofchange.By means of the signed digit (SD) representation [3], code words

of the NB code can be converted into a code with a distance of 2between successive code wdrds. In this code conversion any group ofsuccessive 1 bits can be replaced by two signed digit 1 bits.

(1)2n + 2n-1 +... + 2n- = +2n+l - 2n-m.

In its sirnplest form, (1) becomes as follows.

2n = +2n+l - 2n. (2)In this type of code conversion, the most significant 1 bit will be

positive and further 1 bits will alternately be negative and positive.The value of the bits in the (SD) code words follows from the mod 2sum of the pairs of adjacent bits in the corresponding NB code words.When the bits in the NB code words are indicated with ai and those

in the SD code words with Ai, a digit in t-he SD code word will bedefined by (3).

Ai= as EDai-e.

Example of a code conversion:

3225= 025 = +1

16 8 41 1 00 -1 0

20

+1

11

-1

(3)

in NBin SD.

Any two successive SD code words in accordance with (1) and (2)differ in two bits only. It can easily be checked that the places of thesetwo bits coincide with the 1 bits of the SD representation of the mod 2sum of the pair of successive NB code words involved.

Example:

367.= 1 0 1 1 0 1 1 1 1368= 1 0 1 1 1 0 0 0 0

s.d. =367 = +1368 = +1

0 000 00

-1 +1 0-1 +1 0

0+1-10

1 1 1 10 0 0 0

+1 0 0 0-1 0 0 0

1-1-10

A New Explanation of the Reflected Binary Code

R. M. M. OBERMAN

Abstract-Reflected binary (RB) code words plus an even paritycheck can be considered as signed digit (SD) representations ofthe corresponding natural binary (NB) code words. The SD codewords allow a simple serial conversion with the least significant bitleading of their digits forming the RB code words into the NBcode words.

Manuscript received September 17, 1973; revised November 21, 1973.The author is with the Department of Electrical Engineering, Tech-

nical University, Delft, The Netherlands.

0 0 0 0 1 0 0 0 0 1

It follows from the above that any SD code word obtained via(1) and (2) will have an even number of bits. Furthermore it followsfrom the above that any pair of successive SD code words of thisconstruction will differ in two digit places, one of which is always theleast significant digit place. Hence, these SD code words without thedigit on the least significant digit place, form a progressive code inwhich successive code words differ in one bit only.

In Table I the 4-bit NB code and the corresponding 5-bit SD codeare shown [1].The weights of the bits of the NB code words and those of the SD

code words are shown on top of Table I. The fact that the SD codegroup shows a difference in at least two digit places between any pairof code words, means that this code group has single-error-detectingpower. This follows also from the fact that all SD code words havean even number of 1 bits.The least significant column with weight -1 is, as already said,

redundant. The remaining bits of the SD code words will have weightswhich are one less than they have in the complete SD code words.,The weight of the bits of these reduced code words will then be 15

641

IEEE TRANSACTIONS ON COMPUTERS, JUNE 1974

signed digit and refI. bin. output

NO

0

1

234567

891011

12131415

8 4 2 1

0 0 0 0

0 0 0 1O 0 1 0

0o0 1 1

0 1 0 0

0 1 0 10 1 1 00 1 1 1

1 0 0 0

1 0 0 11 0 1 01 0 1 1

1 1 0 0

1 1 0 1

1 1 1 01 1 1 1

16 ±8 ±4 ±2 -115 ±7 ±3 ±1 C

0 0 0 0 0

0 0 0 1 1O 0 1 1 0

O 0 1 0 1

0 1 1 0 00 1 1 1 1

0 1 0 1 00 1 0 0 11 1 0 0 0

1 1 0 1 11 1 1 1 0

1 1 1 0 1

1 0 1 0 0

1 0 1 1 1

1 0 0 1 0

1 0 0 0 1

d 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

SD RB I NB-1 Z Ch

A 1

± 2 Y ±1

2

±4 X±3

JC-U C 4

±8 W±7'16 V 15 r-

Fig. 1. Time diagram.

A7, 43, 41, which are the characteristic weights of the bits in 4-bitreflected binary (RB) code words, also called Gray code in honor ofits inventor.

It is noted that the code conversion from a SD code word inaccordance with (1) and (2) back into the NB code, is defined by thefollowing equation.

n

ai= Ai (mod 2). (4)i=i

A code conversion in accordance with (4) can be performedserially, either with the least significant bit or with the most sig-nificant bit of the SD code word as leading element. Hence, whenextending RB code words with a parity check bit, their serial codeconversion to natural binary code words can be performed withoutdelay [2].The very narrow relation between the NB code, the SD binary

code and the RB code is also illustrated by the fact that an asyn-

chronous operating n-bit natural binary counter consisting of n

binary unit counters can simultaneously generate the SD code andthe RB code.A time diagram of a 4-bit asynchronous NB counter consisting of

four MS flip-flops is shown in Fig. 1. The master parts of the flip-flops Z, Y, X, W together with slave part V, generate the SB and RBcode, slave parts D, C, B, and A generate the NB code.This means that a combined counter can be derived from any

asynchronous NB counter provided that the outputs of the masterparts are available, which is not the case with commercial I.C.counters.The simplest combined counter will be obtained by using two

groups of clocked latches as is shown in the circuit of Fig. 2. Latchpairs Z/A, Y/B, X/C, and W/VD form binary unit counters.Outputs Q and Q of the A, B, C, and D slave parts drive the nextpair of latches in an asynchronous way in accordance with the timediagram of Fig. 1.

nat.bin out putFig. 2. NB, SD, and RB counter.

REFERENCES[11 G. C. Tootill. "The use of cyclic permuted codes in relay counting

circuits," Proc. Inst. Elec. Eng. (London), vol. 103, pp. 432-436, 1956.121 H. J. Gray, Jr., P. V. Levonian, and M. Rubinoff, "An analogue to

digital converter for serial computing machines," Proc. IRE, vol. 41,pp. 1462-1465, 1953.

[3] R. M. M. Oberman, Disciplines in Combinational and SequentialCircuit Design. New York: McGraw-Hill, 1970.

Parallel Algorithms for Joining Two Points by aStraight-Line Segment

C. D. STAMOPOULOS

Abstract-After an overview of the cellular logic image processor,CLIP 3, parallel algorithms for joining two points are described.These real time algorithms are simple, work properly, preserve theconnectivity, are based only on logic, and show much of the behaviorof processing occurring in sensory elements of animals.

Index Terms-Artificial intelligence, cellular logic, cybernetics,image processing, parallel digital computing, parallel processing,pattern recognition.

INTRODUCTIONBefore explaining the details of some algorithms for joining two

points by a straight-line segment, it will be useful to give a shortoverview of the processor used. The cellular logic image processor,CLIP 3, is a parallel processor with a 12 X 16 192 logic cell arraypermitting square (S) or hexagonal (H) tessellations, both underprogram control [1], [2]. The general organization of CLiP 3 isshown in Fig. 1.The function generator has two inputs, P and A, and two outputs,

N and D. The N output conveys information propagated to andreceived from the neighbors of each cell. The D output may bestored in the D memory, the contents of which may be displayed inthe A or B displays under program control. The A display is con-nected to the A input so that the image displayed in A is also theinput image. The information propagated by the neighbors is thresh-olded by 2 f and the result T may be "oRed" with the contents ofthe B display, used in general to display the output. Thus the ORresult B + T is the P input to the function generator. Fig. 2 givesan idea of the propagation directions provided in the square andhexagonal mode and the interconnections from one ceel to its neigh-bors, for hexagonal tessellation.

OBJECTIVEAn efficient algorithm for joining two points by a straight-line

segment should satisfy certain conditions. If the points to be joinedare in one and the same direction, as provided by the array mode,

Manuscript received September 17, 1973; revised February 27, 1974.The author was with ICS, University of London, London, England.He is now with the Institute of Biomedical Sciences, 'University of SSoPaulo, Brazil.

642

TABLE I