Journal ofNeuroseienceMethods, 27 (1989) 165-172 165 Elsevier

NSM00912

A monolithic patch-clamping amplifier with capacitive feedback

J. Prakash 1, j . j . Paulos 1 and D.N. Jensen 2

l Department of Electrical and Computer Engineering, North Carolina State Universi(v, Raleigh, NC 27695-7911 (U.S.A.) and -" Department of Medicine, Duke UniversiO' Medical Center, Durham, NC 27710 (U.S.A.)

(Received 17 May 1988) (Revised 10 October 1988)

(Accepted 14 October 1988)

K e y words: V o l t a g e - c l a m p ; Single-channel record ing

Patch-clamping is an established method for directly measuring ionic transport through cellular membranes with sufficient resolution to observe open/close transitions of individual channel molecules. This paper describes an alternative technique for patch-clamping which uses a capacitor as the transimpedance element. This approach eliminates bandwidth and saturation limitations experienced with resistive patch-clamping amplifiers. A complete monolithic design featuring an on-chip operational amplifier, a capacitor array with gain-ranging from 30 pF down to 0.03 pF, and reset and gain ranging switches has been fabricated using 5 ~m CMOS technology. It is shown that the voltage noise of the CMOS operational amplifier limits the overall noise performance, but that performance competitive with conventional instruments can he achieved over a 10 kHz bandwidth, at least for small input capacitances (_< 5 pF). Results are presented along with an analysis and comparison of noise performance using both resistive and capacitive elements.

Introduction

Patch-c lamping is widely used to measure ionic t r anspor t th rough cel lular membranes . In recent years, the technique has been ex tended to the observa t ion of ind iv idua l ionic channels for a var ie ty of cell types (Hami l l et al., 1981; Aue rbach and Sachs, 1984; Rae and Levis, 1984). This has been made poss ib le by the use of suct ion in the p ipe t t e to form a Ga2 seal resis tance be tween the p ipe t te and m e m b r a n e (Hami l l et al., 1981). The fo rmat ion of a G~2 seal reduces the in t r ins ic back- g round noise level to the po in t where it is poss ib le to detect the o p e n / c l o s e t rans i t ions of ind iv idua l ionic channels .

T r a d i t i o n a l p a t c h - c l a m p i n g i n s t r u m e n t a t i o n consis ts of a t r ans impedance ampl i f ie r with a re-

Correspondence: J. Paulos, Department of Electrical and Com- puter Engineering, North Carolina State University, Raleigh, NC 27695-7911, U.S.A.

s is tor as the feedback e lement (Sigworth, 1983). Large-va lued resis tors (>_ 10 G~2) are required to ma in ta in a high s ignal - to-noise ra t io in the current recording. This imposes two serious l imi ta t ions on the measurement . Firs t , the shunt capac i t ance of the la rge-va lued res is tor l imits the measuremen t bandwid th . A n d second, there is an observa t ion ' d e a d - t i m e ' in the measu remen t of vol tage-act i - va ted channels as the capac i t ance at the measure- ment node is charged through the feedback resis- tor (Sigworth, 1983).

A n a l te rna t ive technique for pa t ch -c l amping has been inves t iga ted which e l iminates these p rob- lems by using a capac i to r as the t r ans impedance e lement (Offner and Clark , 1985, Prakash et al., 1987). This p a p e r descr ibes a fully monol i th ic imp lemen ta t i on of this a p p r o a c h which features on-ch ip capac i to r s for the feedback e lement and an on-ch ip reset switch to cont ro l sa tu ra t ion ' d e a d t ime' . The ci rcui t also features on-chip gain rang- ing, which is p r o g r a m m e d f rom TTL-level inputs. Noise measu remen t s of the in tegra ted circuit are

0165-0270/89/$03.50 ,v~ 1989 Elsevier Science Publishers B.V. (Biomedical Division)

166

presented along with an analysis of noise sources for both resistive and capacitive feedback. Noise sources in CMOS technology are considered in comparison to the more commonly used JFET approaches.

Patch-Clamping Using Resistive Feedback

Fig. 1 shows the circuit typically used in patch- clamping instruments. Given typical resistor val- ues of 10 or 20 GO, a parasitic shunt capacitance of only 0.1 pF will limit the frequency response of the amplifier to 1 kHz, which is inadequate to resolve the fast openings and closings exhibited by many channels (Sigworth, 1983). A high-frequency boost amplifier is often used to compensate for this limited response. However, the patch-clamp- ing amplifier will generally not have a single pole roll-off at high frequencies due to a non-uniform distribution of parasitic capacitance within the feedback resistor. This limits the effectiveness of simple compensation circuits. The high-frequency boost circuit also acts as an added source of noise.

Saturation 'dead time' is often a problem for resistive patch-clamping amplifiers in the study of voltage-activated channels. Upon the application of a voltage step at the command input, the amplifier tries to force the pipette voltage to fol- low the command signal. To do this, current must flow through the feedback resistor to charge the total capacitance at the inverting input. As only a limited amount of current can flow through the

R F

I < .

Vout

--~---- Pipet t e Command

- ~ Voltage

Fig. 1. Patch-clamping amplifier with resistive feedback. Schematic of a conventional patch-clamping amplifier with a resistor (R F) as the transimpedance element. The output volt- age is directly proportional to the pipette (membrane) current.

I <

_ _ P i p e t t e

i

__F2_ l~ese,'

Vout

Command - - - ~ Voltage

Fig. 2. Patch-clamping amplifier with capacitive feedback. Schematic of an integrating patch-clamping amplifier with a capacitor (CF) as the transimpedance element. The output voltage is proportional to the integral of the pipette (mem-

brane) current.

high-valued resistor, the amplifier output will saturate and the current measurement will be lost for a period of time determined by the value of the feedback resistor and the net charge that must be delivered to the input capacitance. The satura- tion time can be reduced by charging the input capacitance through a separate pathway, generally a coupling capacitor connected to the inverting terminal (Sigworth, 1983). Although the magni- tude of the cancellation voltage step can be varied to adjust the cancellation charge, there will still be in practice a reduced but finite 'dead-time'.

Patch-Clamping Using Capacitive Feedback

The limitations of patch-clamping with resistive feedback can be overcome by using a capacitor as the feedback element, as shown in Fig. 2. Use of a capacitor avoids the frequency limitations experi- enced with large-valued discrete resistors, and ob- servation 'dead-time' can be eliminated by turning on a reset switch as the command voltage is applied. This provides a tow resistance path for the transient charging current, which prevents pro- longed saturation of the operational amplifier out- put. The recovery time of the amplifier is now limited by its settling time, which can easily be kept to a few microseconds.

For a patch-clamping amplifier with capacitive feedback, the output represents the integral of the input current. The original signal can be recovered through the use of a differentiator circuit. Notice that the reset switch needs to be closed periodi- cally to keep the output from saturating as the result of leakage currents at the input. This intro- duces an upper limit on the continuous observa- tion time. Fortunately, the reset periods are very brief and can easily be removed from the record.

There are several significant advantages of monolithic implementation of patch-clamping with capacitive feedback. First, small-valued, high-qu- ality capacitors can be precisely defined with reso- lution down to 0.01 pF. Second, the stray capaci- tances associated with a discrete implementation are virtually eliminated by including the amplifier, the capacitor, and the reset switch all on one chip. Finally, minimum-geometry devices with low leakage and small parasitic capacitance can be used for the reset switch. This minimizes the input leakage current as well as the charge injected on the measurement node when the feedback switch opens. In contrast, most commercially available analog switches use relatively large geometry tran- sistors with significant package capacitances.

CMOS technology is ideally suited for capaci- tive patch-clamping due to the ease of implement- ing the reset switch and in defining precise capaci- tor structures. More importantly, CMOS technol- ogy is the only standard integrated circuit technol- ogy which features highly linear capacitors with negligible (series or parallel) parasitic resistance and low dielectric relaxation (Lee and Hodges, 1984). On the other hand, CMOS amplifiers gen- erally exhibit much higher noise levels than either bipolar or JFET designs. A critical goal of this work was to demonstrate that the noise level of a CMOS amplifier would not severely degrade the performance of the overall patch-clamping circuit.

A Monolithic Patch-Clamping Amplifier

An integrated circuit which includes an oper- ational amplifier, an array of capacitors with gain-ranging switches, and a reset switch was fabricated using CMOS technology. The specific

167

configuration is shown in Fig. 3. All essential features of the circuit were implemented on-chip using the G TE 5 ~m CMOS process. The capaci- tor array was implemented using two layers of polysilicon with an oxide dielectric thickness of 115 nm. The array is based on unit cells of nomi- nally 0.1 pF, and can be configured to provide 0.03, 0.1, 0.3, 1,0, 3.0, 10.0, or 30.0 pF of total feedback capacitance. The gain-ranging switches are n-channel MOSFET's in a p-type device well which is tied to the command voltage. In this configuration, the source and drain junctions are held at zero bias, essentially eliminating the junc- tion leakage currents. In addition to gain-ranging, varying the feedback capacitor makes it possible to trade noise performance for continuous ob- servation time.

The reset switch was implemented using a parallel combination of p-channel and n-channel transistors with complementary control signals at their respective gates. This helps to reduce charge dump onto the feedback capacitor since the charge from the n-channel transistor is approximately cancelled by charge from the p-channel transistor. On-chip level shifters were provided to translate

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I I ~ s2 c2

T Fig. 3. Detailed schematic of the monolithic patch-clamping amplifier. All switch transistors are 20 ~m wide by 7 p.m long.

168

TABLE I

OP-AMP PERFORMANCE SPECIFICATIONS

Measured performance of the CMOS operational amplifier. All data taken at room temperature.

Parameter Measured

Input offset voltage < 5 mV Input noise, 100 Hz 87 nV. Hz ~,2

1 kHz 34 n V . H z l.,:

Slew rate 3.27 V//~s Supply voltage _+ 5 V DC gain 99 dB CMRR 85 dB PSRR 89 dB Unity-gain frequency 1.6 MHz

qq'L-level inputs into the ± 5 V swing required at the gates of the reset and gain-ranging switches.

The operational amplifier is a three-stage de- sign with a conventional differential input stage. The measured performance is summarized in Ta- ble I. As noted above, MOS input stages exhibit much higher voltage noise than either bipolar or JFET designs. Flicker, or l / f , noise is often the dominant noise source in MOS amplifiers at low frequencies, and 1 / f corner frequencies in the tens of kilohertz are quite common (Jolly and Mc- Charles, 1982). The magnitude of the flicker noise is dependent upon the device geometry and the process used to fabricate the device. Flicker noise performance improves as device size increases,

TABLE II

SYSTEM GAIN AND OBSERVATION TIME VS FEED- BACK CAPACITANCE

Transimpedance gain and maximum continuous observation time calculated for each possible capacitor selection. Assumes differentiator circuit with a unity-gain frequency of 333 r a d / s and 0.25 pA of input leakage current,

Capacitance Gain Observation time (pF) (G[2) (s)

0.03 100.0 0.6 0.1 33.3 2.0 O.3 10.0 6.0 1.0 3.3 20.0 3.0 1.0 60.0

10.0 0.33 200.0 30,0 0.1 600.0

and in this design, the input devices were sized to produce approximately 2.0 pF of input capaci- tance. The voltage noise of the operational ampli- fier is 87 nV. Hz -~/2 at 100 Hz, with a 1 / f corner of approximately 1.3 kHz. This performance ex- ceeds the best results reported to date (Jolly and McCharles, 1982). Unfortunately, these results are process dependent and may not be reproducible.

The maximum continuous observation time is determined by the value of the feedback capacitor and the input leakage current. Table I1 sum- marizes the transimpedance gain and continuous observation time of the patch-clamping amplifier for each capacitor selection. These numbers are based on an experimental leakage current of 0.25 pA and a differentiator unity-gain frequency of w0 = 333 rad/s . The differentiator circuit used is described in a later section.

The charge dump from the reset switch and the input leakage current were measured with an open circuit at the input. The charge dump occurs as the result of capacitive feedthrough of the reset clock into the virtual ground node as the reset switch is turned off. The charge dump varies from 5 to 25 fC for control line transition times ranging from 5 to 50 ns. (The charge dump is lower for longer transition times since some of the charge is able to return to the source through the 'ON" resistance of the switch.)

Noise Analysis of Resistive Feedback

The total noise observed with resistive patch- clamping includes contributions from the elec- tronic circuitry, the pipette, and the membrane itself. The noise sources in the electronic circuitry include the Johnson noise of the feedback resistor as well as the voltage and current noise of the operational amplifier. The Johnson current noise of the feedback resistor contributes directly to the total input-referred current noise. This noise can be expressed as a power spectral density as follows

if¢ v = 4 k T R e { Y~: } (A2/Hz) (1}

where R e { Y v} represents the real part of the admittance of the feedback resistor. If the physical resistor can be represented as an ideal resistor

with a shunt capacitance, then the real part of the admittance is simply 1 / R v. Unfortunately, most large valued resistors have a non-uniformly dis- tributed shunt capacitance, in which case, the real part of the admittance can be significantly larger than 1 / R v. This phenomenon has been demon- strated to produce experimental current noise which is several times larger than that predicted by Eqn. 1 (Rae and Levis, 1984).

The operational amplifier, or other preampli- f ier /amplif ier combination, can be characterized by an input-referred current noise and an input- referred voltage noise. Conventional patch-clamp- ing amplifiers often utilize a JFET preamplifier followed by a low-noise operational amplifier (Hamill et al., 1981). In this configuration, the input-referred current noise is essentially the shot noise associated with the input gate current. This can be written as a power spectral density as follows

i~; = 2q I~ (A2/Hz) (2)

where lg is the input gate current (typically 0.2-5 pAl. This current noise will also contribute di- rectly to the overall equivalent input noise. For example, an input gate current of 5 pA produces input current noise equal to that of a 10 G~2 feedback resistor.

The voltage noise of the amplifier can be re- ferred back as an equivalent input current by dividing by the effective impedance at the in- verting input. This effective impedance is equal to the parallel combination of the seal resistance, the seal (or membrane) capacitance, the feedback re- sistance, and the parasitic capacitance of the feedback resistor. Generally, the time constant of this impedance is so low that the nodal capaci- tance dominates over the frequency range of inter- est ( > 10 Hz). The equivalent input current noise spectral density is therefore given by

iv = ( ~ CT )21/2 (A2/Hz) ( 3 )

where Cw is the total capacitance at the input and V 2 is the voltage noise power spectral density of the amplifier. This noise contribution increases with frequency and can dominate the overall noise performance at higher frequencies.

169

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o

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J _ .

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~ , , i l l l l l [ i i [ I L I L L [ _ . ~ I I I , , ,

102 103 10 ~

F r e q u e n c y ( H z )

Fig. 4. Noise contributions with resistive feedback. Equiwdent input current noise contributions (spectral density) plotted vs frequency: from seal or feedback resistance (R = 20 G~2I, 1 R, from amplifier noise current, 1~, from amplifier noise voltage, I v. Calculations based on specifications for U-401 JFET.

Assumes 5 pF of additional input capacitance.

A sample calculation of the noise contributions for resistive patch-clamping was performed to provide a basis of comparison with the capacitive case. The results are shown in Fig. 4. These calcu- lations are based on the published specifications of a typical low noise JFET device (U-401). A pipette capacitance of 5 pF is assumed to be present at the input node in addition to the 10 pF input capacitance of the U-401 device. For resis- tive patch-clamping there are 4 primary noise sources: the seal resistance, the feedback resistor, the current noise of the JFET preamplifier, and the voltage noise of the JFET preamplifier. In Fig. 4, the current noise of a 20 G ~ resistor is plotted to indicate the noise levels expected from the seal and feedback resistances (on the order of 1.0 fA. Hz ~/2). The calculated shot noise for the U-401 is comparatively small, given an assumed gate current of 0.3 pA (Sigworth, 1983). For fre- quencies below 1 kHz, the input-referred noise current produced by the (3 n V - H z 1,/2) voltage noise of the U-401 is swamped by the resistor noise sources. However, this contribution begins to dominate at frequencies above 5 kHz.

170

Noise Analysis of Capacitive Feedback

For patch-clamping with capacitive feedback, the Johnson noise due to the feedback resistor is eliminated completely. In principle, the shot noise of the amplifier is also reduced since the gate current of a MOSFET is essentially zero. How- ever, input leakage currents are present due to the reset switch and the input-protection diodes (not shown in Fig. 3). The voltage noise of the CMOS amplifier is again referred back as an equivalent input current through the effective impedance (capacitance) at the inverting input.

Since the capacitive patch-clamping amplifier is inherently an integrator, it is necessary to follow the amplifier with a differentiator circuit. A buffer/differentiator circuit was designed and constructed to perform noise measurements and to facilitate a comparison of noise performance with resistive and capacitive feedback. An Analog Devices OP-27 operational amplifier was used in a non-inverting gain of three configuration to pro- vide a low capacitance load for the CMOS oper- ational amplifier and to scale the + 5 V swing of the CMOS amplifier to a + 15 V range. A differ- entiator circuit was then constructed using a Sig- netics NE5534 operational amplifier. The unity- gain frequency of the differentiator was 1.0 krad/s , with high-frequency poles located at 40.8 and 31.9 kHz. An analog switch was used to clamp the differentiator output during the reset transient. Given the combined buffer/differentiator unity- gain frequency of 333 rad/s , the output of the overall system in response to an input current is given by

V0_ 3 . 1 0 - 3 0 = 3 ~ -TG~ given C F in pF (4)

C--~ /i~

Thus a feedback capacitance of 0.3 pF provides the same overall transimpedance gain as a 10 G~? resistor.

The buffer/differentiator circuit was treated as an additional noise source which is referred back to the input through the transimpedance gain of the patch clamping amplifier. For small-valued capacitors ( < 1 pF), the transimpedance gain is large enough to keep the noise contribution of the buffer/differentiator circuit below that of a typi-

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i ~ l 1 i l l l t l t I I I , t i l l l , 1 • i J J l

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F r e q u e n c y ( H z )

Fig. 5. Noise contributions with capacitive feedback. Equiv- alent input current noise contributions (spectral density) plotted vs frequency: from seal resistance (R= 20 G~2), 1 R, from amplifier noise current, I~, from amplifier noise voltage. I v, from buffer/differentiator circuit, 18. Calculations based on noise measurements of monolithic patch-clamping amplifier.

Assumes 5 pF of additional input capacitance.

cal seal resistance, at least for frequencies below 10 kHz.

All 4 noise components for the capacitive patch-clamping amplifier are shown together in Fig. 5 for a feedback capacitor of 1 pF. The current noise of a 20 GO resistor is plotted for reference and to indicate the typical noise level of the seal resistance. The input current noise of the CMOS amplifier is essentially negligible. The noise contribution from the voltage noise of the CMOS amplifier is much larger than for the U-401 JFET, and begins to dominate above 1 kHz. (The plotted curve is calculated from the measured noise of the CMOS amplifier.) For a feedback capacitor of 1 pF, the input-referred noise introduced by the buffer/differentiator is negligible.

Noise Comparison

The total noise for a given input capacitance can be calculated by summing and integrating the contributions from the individual noise sources over the 10 kHz bandwidth using data similar to that of Figs. 4 and 5. The results are shown in Fig. 6, where the total input-referred current noise is

171

i _ _ . 1 _ L l I . I l t

,.00 O.SO 1.00 1.50 2.00

Input Capacitance (pF) ( x 10)

Fig. 6. Total noise versus input capacitance. Calculated total equivalent input current noise over a 10 kHz bandwidth plotted vs additional input capacitance. Solid line for capacitive feed-

back, dashed line for resistive feedback.

plotted versus the input (pipette plus membrane) capacitance. The total noise for the capacitive feedback case is a strong function of the input capacitance since the amplifier voltage noise is the dominant noise source. The experimental noise of the integrated circuit was found to be 1.7 pA for an input capacitance of 10 pF. This is approxi- mately 40% higher than the value predicted in Fig. 6. A small part of this discrepancy may be due to noise from the gain ranging switches. However, the resistance of these switches is less than 2 k~2, and it is estimated that the gain-ranging switches contribute less than 0.2 pA of equivalent input noise for the 1 pF configuration.

It is clear from Fig. 6 that the calculated noise for the monolithic patch-clamping amplifier is sig- nificantly greater than that expected from a high- quality resistor design. This is almost entirely the result of the poor voltage noise performance of the CMOS operational amplifier. It should be noted at this point that we have neglected for the resis- tive case the effect of non-uniformly distributed stray capacitance in the feedback resistor and noise from the high-frequency boost circuit. Also, given the experimental 1 / f corner frequency of 1.3 kHz, it would appear that the noise of the CMOS amplifier is limited more by thermal noise than by 1 / f noise. Although the 1 / f noise has been opti- mized given the constraints on the input capaci-

tance, the thermal noise performance could be improved considerably. Taken together, it would appear that a fully monolithic implementation of capacitive patch-clamping could provide competi- tive noise performance relative to conventional resistive feedback circuits, at least for input capa- citances of less than 5-10 pF.

Conclusion

A fully monolithic patch-clamping amplifier fabricated in a 5/~m CMOS technology and using capacitive feedback has been described. The des- ign incorporates features which overcome band- width and saturation 'dead-time' problems experi- enced with traditional patch-clamping amplifiers. It has been shown that the voltage noise of the CMOS operational amplifier limits the overall noise performance, but that performance competi- tive with conventional instruments could be achieved over a 10 kHz bandwidth, at least for small input capacitances (_< 5 pF). Therefore, monolithic implementations of capacitive patch- clamping may be well suited to single-channel recording where stray capacitance is limited. For whole-cell recordings, resistive feedback using low-noise JFET amplifiers will generally provide superior noise performance. Hybrid approaches are currently being explored which will combine the capacitive technique with available low-noise JFET amplifiers to obtain improved performance over either conventional resistive approaches or the monolithic implementation described here.

Acknowledgements

The authors would like to thank the Govern- ment Systems Division of the GTE Corporation in Needham, Massachusetts for providing for fabri- cation of the patch-clamping amplifier. The authors would also like to thank Drs. Augustus Grant, Harold Strauss, and Frank Starmer of the Duke University Medical Center for introducing them to the problem, and for the benefit of their experience in patch-clamp recording. This work has been supported in part by NIH Grant HL32708 and by Analog Devices Inc.

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Lee, H.S. and Hodges, D.A, (1984) A precision measurement technique for residual polarization in integrated circuit capacitors, IEEE Electr. Dev. Lett., EDL-5: 417-420.

Offner, F.F. and Clark, B. (1985) An improved amplifier for patch-clamp recording, Biophys. J., 47: 142a~

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Rae, J.L. and Levis, R.A. (1984) Patch voltage clamp of lens epithelial cells: theory and practice, Molec. Physiol., 6: 115-162.

Sigworth, F.J. (1983) Electronic design of the patch clamp, tn Sakmann, B. and Neher, E. (Eds), Single Channel Record- ings, Plenum, New York, pp. 13-35.