A Modified SEPIC Converter for High power factor Rectifier and Universal Input Voltage Applications

310 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 25, NO. 2, FEBRUARY 2010

A Modified SEPIC Converter for High-Power-FactorRectifier and Universal Input Voltage Applications

Priscila Facco de Melo, Roger Gules, Member, IEEE, Eduardo Felix Ribeiro Romaneli,

and Rafael Christiano Annunziato

Abstract—A high-power-factor rectifier suitable for universalline base on a modified version of the single-ended primary induc-tance converter (SEPIC) is presented in this paper. The voltagemultiplier technique is applied to the classical SEPIC circuit, ob-taining new operation characteristics as low-switch-voltage opera-tion and high static gain at low line voltage. The new configurationalso allows the reduction of the losses associated to the diode re-verse recovery current, and soft commutation is obtained with asimple regenerative snubber circuit. The operation analysis, de-sign procedure, and experimental results obtained from a 650-Wuniversal line power-factor-correction prototype of the proposedconverter are presented. The theoretical analysis and experimen-tal results obtained with the proposed structure are compared withthe classical boost topology.

Index Terms—AC–DC power conversion, switched circuits,voltage multipliers.

I. INTRODUCTION

THE BOOST converter is the usual structure utilized in

high-power-factor (HPF) rectifiers in order to improve

power factor (PF) and reduce the total current harmonic distor-

tion (THDi). However, for universal input voltage application,

the efficiency can be reduced mainly in the lowest input volt-

age, and the worst operation condition must be considered in the

power converter design procedure [1]. The improvement of the

efficiency at lower line voltage is important because the thermal

design and heat sinks size are defined considering the worst op-

eration point. Many works were developed in order to improve

the operation characteristics of the power converter utilized in

HPF universal input rectifiers. A review of the main single-phase

topologies and techniques used in an HPF rectifier is presented

in [2]–[4]. A discussion about the use of single stage and two

stages structures is presented in [5]. A two switches topology for

universal input HPF rectifier is presented in [6]. Some single-

stage-isolated HPF rectifiers are presented in [7]–[14].

The use of high static gain and low-switch voltage topologies

can improve the efficiency operating with low input voltage, as

presented in [15]–[18]. The voltage multiplier technique was

presented in [18] for a boost converter in order to increase the

static gain with reduced switch voltage. However, the boost volt-

age doubler cannot be used for a universal input voltage HPF

rectifier because the output voltage must be higher than the dou-

ble of the maximum input voltage (Vo = 800 V). A modification

in the multiphase boost voltage doubler was proposed in [1] for

Manuscript received February 19, 2009; revised May 13, 2009. Currentversion published February 12, 2010. Recommended for publication byAssociate Editor P.-T. Cheng.

The authors are with the Federal University of Technology Parana (UTFPR,),Curitiba PR 80230-901, Brazil (e-mail: [email protected]).

Digital Object Identifier 10.1109/TPEL.2009.2027323

Fig. 1. Classical SEPIC converter.

a universal input HPF rectifier, in order to obtain high static gain

at the lower input voltage with the same dc output voltage level

of a classical boost converter (Vo = 400 V).

The integration of a voltage multiplier cell with a classical

single-ended primary inductance converter (SEPIC) is proposed

in this paper in order to obtain a high step-up static gain oper-

ating with low input voltage and a low step-up static gain for

the high input voltage operation. The operation characteristics

obtained with this modification makes the proposed structure

an interesting alternative for the universal input HPF rectifier or

wide input voltage range applications, operating with high effi-

ciency. The proposed converter operates with a switch voltage

lower than the output voltage, and with an input current ripple

lower than the classical boost converter. The power circuit of the

proposed converter can be integrated with a simple regenerative

snubber, obtaining soft-switching commutation and increasing

the efficiency.

II. PROPOSED CONVERTER

The power circuit of the classical SEPIC converter is pre-

sented in Fig. 1. The step-up and step-down static gains of the

SEPIC converter is an interesting operation characteristic for a

wide input voltage-range application. However, as the switch

voltage is equal to the sum of the input and output voltages, this

topology is not used for a universal input HPF rectifier.

The voltage multiplier technique was presented in [18] in or-

der to increase the static gain of single-phase and multiphase

boost dc–dc converters. An adaptation of the voltage multiplier

technique with the SEPIC converter is presented in Fig. 2. The

modification of the SEPIC converter is accomplished with the

inclusion of the diode DM and the capacitor CM. Many op-

erational characteristics of the classical SEPIC converter are

changed with the proposed modification.

The capacitor CM is charged with the output voltage of the

classical boost converter. Therefore, the voltage applied to the

inductor L2 during the conduction of the power switch (S) is

0885-8993/$26.00 © 2010 IEEE

Authorized licensed use limited to: IEEE Xplore. Downloaded on May 13,2010 at 11:44:15 UTC from IEEE Xplore. Restrictions apply.

DE MELO et al.: MODIFIED SEPIC CONVERTER FOR HIGH-POWER-FACTOR RECTIFIER AND UNIVERSAL INPUT VOLTAGE APPLICATIONS 311

Fig. 2. Modified SEPIC converter.

Fig. 3. First operation stage.

Fig. 4. Second operation stage.

higher than that in the classical SEPIC, thereby increasing the

static gain. The polarity of the voltage stored in the capacitor

CS is inverted in the proposed converter, and the expressions of

the capacitors voltages and others operation characteristics are

presented in the theoretical analysis.

The continuous conduction-mode (CCM) operation of the

modified SEPIC converter presents the following two operation

stages.

1) First stage ([t0 , t1] Fig. 3)—At the instant t0 , the switch S

is turned-off and the energy stored in the input inductor L1

is transferred to the output through the capacitor CS and

output diode Do , and also to the capacitor CM through the

diode DM. Therefore, the switch voltage is equal to the

capacitor CM voltage. The energy stored in the inductor

L2 is transferred to the output through the diode Do .

2) Second stage ([t1 , t2] Fig. 4)—At the instant t1 , the switch

S is turned-on and the diodes DM and Do are blocked, and

the inductors L1 and L2 store energy. The input voltage

is applied to the input inductor L1 and the voltage VCS −

VCM is applied to the inductor L2 . The voltage VCM is

higher than the voltage VCS .

The main theoretical waveforms operating with hard-

switching commutation are presented in Fig. 5.

Fig. 5. Main theoretical waveforms.

The voltage in all diodes and the power switch is equal to the

capacitor CM voltage. The output voltage is equal to the sum of

the CS and CM capacitors’ voltages. The average L1 inductor

current is equal to the input current and the average L2 inductor

current is equal to the output current.

III. THEORETICAL ANALYSIS

The main equations and the theoretical analysis of the pro-

posed converter are presented in this section. The results of the

theoretical analysis are compared with the classical boost con-

verter in order to show the positive and negative aspects of the

proposed converter.

Some comparison with the classical SEPIC converter is also

presented because the proposed topology is obtained from this

converter.

The equations defined by the theoretical analysis are utilized

for the determination of the inductances and capacitances of the

proposed converter. The theoretical analysis is developed con-

sidering the operation as an HPF rectifier, and the utilization

of an ac voltage source and a full-bridge diode rectifier con-

nected to the input of the proposed converter is considered. All



Fig. 6. Static Gain.

analyses are accomplished for an application with an ac input

voltage changing from Vi = 100 Vrms to Vi = 240 Vrms , an

output voltage equal to Vo = 425 Vdc , and a nominal output

power equal to Po = 650 W.

A. Static Gain

The static gain of the proposed converter can be obtained

considering that the average inductor voltage is zero at the steady

state. Therefore, the relation presented in (1) must occur at the

steady state for the inductor L1

VitON = (VCM − Vi) tOFF (1)

ViD = (VCM − Vi) (1 − D) . (2)

Therefore, the CM capacitor voltage is defined by (3), which

is the same equation of the classical boost static gain given by

VCM

Vi

=1

1 − D. (3)

During the period where the power switch is turned-off (tOFF),

the diodes DM and D0 are in conduction state, and the following

relation can be defined:

Vo = VCS + VCM . (4)

The L2 average voltage is zero at the steady state, and the

following relations can be considered:

(VCM − VCS) tON = (Vo − VCM ) tOFF (5)

(VCM − VCS)D = (Vo − VCM )(1 − D). (6)

Substituting (3) and (7) in (6), the static gain of the proposed

converter is obtained and presented in (8)

VCS = Vo − VCM (7)

Vo

Vi

=1 + D

1 − D. (8)

The static gain variation as a function of the duty cycle of

the modified SEPIC and the static gain of other converters is

presented in Fig. 6. The voltage doubler boost converter [18]

presents the highest static gain and is interesting for the opera-

tion with the lower input voltage. However, the minimal output

TABLE IDUTY-CYCLE VARIATION AS A FUNCTION OF THE INPUT

AND OUTPUT VOLTAGES

voltage (D = 0) is the double of the input voltage. Therefore,

this structure cannot be used for a universal input application.

The static gain of the classical boost converter is half of the

voltage doubler boost, and can be used in a universal input ap-

plication. The modified SEPIC converter presents a static gain

closed to the classical boost for low values of duty cycle, and

a static gain closed to the voltage doubler for high values of

duty cycle. Therefore, the static gain is higher than the classical

structures in the operation with high values of duty cycle that oc-

curs in the operation with low input voltage. The operation with

a higher static gain results in an improvement in the operation

with the lower input voltage. The step-up and step-down char-

acteristics of the classical SEPIC converter are not maintained

in the modified SEPIC converter. The proposed structure cannot

operate with an output voltage lower than the input voltage.

The voltage of the series capacitor (VCS ) is defined by sub-

stituting (3) and (8) in (7), resulting the following equation:

VCS

Vi

=D

1 − D. (9)

B. Input Current Ripple and L1–L2 Inductances

The input inductance value is defined as a function of the

maximum input current ripple. As the classical SEPIC, boost,

and the modified SEPIC converters present the same input stage,

the equation for the determination of the input current ripple is

the same for all converters. The input current ripple (∆iL1)

during the conduction of the power switch is defined by the

following equation:

∆iL1 =ViD

L1f(10)

where f is the switching frequency.

Although the same equation can be used to calculate the input

ripple, the input current ripple for each converter is not the same

because the duty-cycle variation is different for each topology,

as presented in Fig. 6. The duty-cycle variation as a function of

the input and output voltages is presented in Table I.

In order to show the duty-cycle variation in a universal input

rectifier application, the instantaneous input voltage signal is

considered in a semicycle of the input line voltage. Fig. 7 is

obtained considering an input line voltage equal to 100 Vrms ,

and Fig. 8 is obtained considering an input line voltage equal to

240 Vrms . The output voltage is equal to Vo = 425 Vdc for both

figures.

As can be observed in Figs. 7 and 8, the modified SEPIC

converter presents the lowest duty-cycle value in all range of

the input voltage. Lower duty cycle results in a lower switch

conduction interval (tON).



Fig. 7. Duty-cycle variation (Vi = 100 Vrm s and Vo = 425 Vdc ).

Fig. 8. Duty-cycle variation (Vi = 240 Vrm s and Vo = 425 Vdc ).

A lower input current ripple is also obtained because the

input voltage (Vi) is applied to the input inductor L1 in a shorter

interval during the tON period.

The parameterized input current ripple (∆iL1) is defined from

(10) and presented in (11).

Replacing in (11) the duty cycle of each converter presented

in Table I, the parameterized input current ripple is obtained and

presented in Fig. 9 for an input voltage equal to 100 Vrms , and

in Fig. 10, for an input voltage equal to 240 Vrms , considering

an output voltage equal to Vo = 425 Vdc

∆iL1 = ∆iL1L1f = ViD. (11)

The input inductance can be defined by (13) obtained from

(11). The input inductance is calculated for the power con-

verter operating at the peak of the lowest input voltage. For

this operation point, the instantaneous input voltage is equal

to Vipk = 141 V, the converter duty cycle is equal to D = 0.5,

and the input current ripple (∆iL1) considered is 23% of the

peak input current (iinpk). Therefore, the input current ripple is

calculated as follows:

∆iL1 = iinpk × 0.23 = 6.5 × 0.23 = 1.5 A. (12)

The input inductance calculated is equal to

L1 =ViD

∆iL1f=

141 × 0.5

1.5 × 48000= 97 916 µH. (13)

Fig. 9. Parameterized input current ripple (Vi = 100 Vrm s and Vo =425 Vdc ).

Fig. 10. Parameterized input current ripple (Vi = 240 Vrm s and Vo =425 Vdc ).

The input inductance value utilized in the practical imple-

mentation is equal to L1 = 1 mH.

The input inductance of the proposed converter is 27% lower

than the input inductance of the classical boost converter, and

33% lower than the input inductance of the classical SEPIC

converter for the same specifications, as presented in Fig. 9.

The inductor L2 presents the same equation as the L1 inductor

current ripple. However, the L1 inductor average current is equal

to the average input current, and the L2 average current is equal

to the output current. As the average input current is higher

than the average output current for a step-up converter, the L2

inductor volume is lower than the L1 inductor volume. The L2

peak current is three times lower than the L1 peak current for the

operation with the lower line input voltage. Also, the L2 current

ripple can be higher than the L1 current ripple because the input

current ripple depends only on the L1 current ripple. Therefore,

the proposed converter uses two inductors, but the L1 inductor

can be 27% lower than the input inductor of the classical boost,



Fig. 11. Parameterized switch voltage (Vi = 100 Vrm s and Vo = 425 Vdc ).

Fig. 12. Parameterized switch voltage (Vi = 240 Vrm s and Vo = 425 Vdc ).

and the L2 volume is smaller than the L1 inductance. The L2

inductance utilized in the practical implementation is half of the

L1 inductance (L2 = 500 µH).

C. Power Switch Voltage

The power switch voltage is also an important parameter of

the circuit in a wide input voltage application, and presents in-

fluence in the converter efficiency and cost. The modification

proposed in this paper significantly changes the drawback of the

operation with high switch voltage of the classical SEPIC con-

verter. A comparison of the power switch voltage is presented

in Fig. 11, considering a line input voltage equal to 100 Vrms ,

and in Fig. 12, for an input voltage equal to 240 Vrms . In both

figures, the output voltage is equal to 425 Vdc , and the switch

voltage is presented parameterized in relation to the output volt-

age. The switch voltage is equal to the output voltage for the

boost converter. Therefore, the parameterized voltage of this

converter is unitary in all voltage ranges. The switch voltage for

the classical SEPIC is equal to the sum of the input and output

voltages. Therefore, the operation voltage is very high, mainly

in the maximum input voltage condition (240 Vrms). The switch

voltage of the modified SEPIC converter is equal to the voltage

of the capacitor CM. This voltage is determined by (3), but with

the duty cycle of the modified SEPIC converter presented in

Table I.

As can be observed in Figs. 11 and 12, the switch voltage of

the modified SEPIC is lower than the output voltage in all input

voltage ranges. Figs. 11 and 12 also show the capacitor voltages

VCM and VCS . The output voltage is equal to the sum of the

VCM and VCS capacitors’ voltages.

D. Series Capacitor (CS ) and Multiplier Capacitor (CM )

The CS series capacitor voltage and the CM multiplier ca-

pacitor voltage change with the line input voltage variation, as

shown in Figs. 11 and 12. Therefore, these capacitances can-

not be large as the output filter capacitor (Co ). However, these

capacitances present a high-frequency voltage ripple due to the

circulating current and the capacitor charge variation (∆Q). As

the circulating current in both capacitances are equal, the high-

frequency voltage ripple is the same. During the power switch

turn-on period, the current in the CS and CM capacitances is

equal to the L2 inductor current. The capacitor charge variation

∆Q is calculated as

∆Q = iL2DT. (14)

The high-frequency capacitor voltage ripple (∆Vc ) can be

defined by (15), as a function of the capacitor charge variation

∆Vc =∆Q

C. (15)

Therefore, the CS and CM capacitances can be defined as

follows:

CS = CM =iL2D

∆Vcf(16)

where f is the switching frequency.

The highest capacitor voltage ripple occurs at the peak of the

lowest line input voltage. The average current of the inductor L2

is equal to the output current (io ), and its peak value must be used

in (16). Considering an input voltage equal to Vi = 100 Vrms

and a maximum capacitor voltage ripple equal to 12% of the

output voltage (∆Vc = 50 V), the capacitors CS and CM can

be defined as

CS = CM =iL2D

∆Vcf=

3 × 0.5

50 × 48000= 625 nF. (17)

The capacitances utilized in the practical implementation of

the proposed converter is equal to CS = CM = 660 nF, com-

posed of two capacitors (330 nF) connected in parallel. A

polypropylene capacitor is used in the practical implementation,

and as the equivalent series resistance (ESR) of the polypropy-

lene capacitor is very low (ESR = 12 mΩ at 100 kHz), the

influence of this resistance in the calculation of the capacitor

voltage ripple is not considered.



Fig. 13. Turn-on regenerative snubber with switch voltage equal to Vo .

E. Output Capacitor

The output filter capacitor (Co ) is determined as in the clas-

sical boost converter. The capacitance is defined by a function

of the output power (Po ), the grid frequency (fG ), and the low-

frequency output voltage ripple (∆Vo ). Considering an output

voltage ripple equal to 1% of the output voltage, the output

capacitance is calculated as

Co =Po

2πfG × 2Vo∆Vo

=650

2π60× 2× 425× 4.25= 477 µF.

(18)

The output filter capacitor utilized in the practical implemen-

tation is equal to Co = 500 µF.

F. Regenerative Snubber

A classical problem presented by the hard-switching struc-

tures operating in CCM is the reduction of the efficiency due

to the additional losses caused by the reverse recovery current

of the diodes. This problem is an important source of losses

in a universal input HPF rectifier. There are some regenerative

snubbers proposed for the classical boost converter that can

reduce the effects of this problem [19]. However, the correct

operation of these snubbers in all input voltage ranges is dif-

ficult. Therefore, the use of these snubber integrated with the

classical boost converter cannot be effective for the universal in-

put HPF rectifier. There are some soft-switching configurations

with the inclusion of an active switch and other components in

order to reduce the reverse recovery current and eliminate the

commutation losses [4], [20], [21]. This alternative can be used

in high-performance applications, but increases the complexity

and cost of the converter.

The power circuit of the modified SEPIC converter allows the

integration of three regenerative snubbers that reduces the diode

reverse recovery current problem, and is effective in all input

voltage ranges. The simplest regenerative snubber is presented

in Fig. 13. A small inductance Lsnb (typically, 5–20 µH) is con-

nected in series with the power switch. This inductance limits

the di/dt at the switch turn-on instant and zero-current switching

(ZCS) is obtained. When the power switch is turned-off, the en-

ergy stored in the Lsnb inductance is transferred to the capacitor

CS through the diode Dsnb . This configuration eliminates the

turn-on commutation loss, which is the most significant part of

the commutation losses. The turn-off commutation is dissipa-

tive and the power switch voltage is equal to the output voltage

Fig. 14. Turn-on/ turn-off regenerative snubber with switch voltage equal toVo .

Fig. 15. Turn-on/ turn-off regenerative snubbers with switch voltage equal toVCM .

with the inclusion of the diode Dsnb .The soft-switching turn-on

and turn-off commutation snubbers, presented in Fig. 14, can be

obtained including some additional components to the circuit

presented in Fig. 13. The inductor Lsnb limits the di/dt at the

switch turn-on, and when the power switch is turned-off, the

energy stored in this inductance is transferred to the capacitor

Csnb through the diode Dsnb1 . The initial condition of the volt-

age in the capacitor Csnb is zero, and the reduced capacitance

value (typically, 3–30 nF) limits the dv/dt of the power switch

voltage. The voltage in this capacitor increases until it reaches

the output voltage value when the diode Dsnb2 conducts. Dur-

ing the conduction of the power switch, the energy stored in

the capacitor Csnb is transferred to the capacitor Cs through the

diode Dsnb2 and inductor Lsnb until the Csnb voltage becomes

null. The peak current is limited by the Lsnb inductor during this

energy transference. The switch voltage is limited to the output

voltage with the use of this snubber.

Fig. 15 presents the turn-on and turn-off snubbers with the

power switch voltage equal to VCM , which is lower than the

output voltage. The operation of this snubber is almost the same

as the circuit presented in Fig. 14. The unique difference is

that during the energy transference from the inductor Lsnb to

the capacitor Csnb , after the power switch turn-off, the capaci-

tor voltage increases until it reaches the CM voltage when the

diode Dsnb3 conducts, maintaining the switch voltage equal

to the voltage VCM , as in the hard-switching circuit. During

the conduction of the power switch, the snubber capacitor is

discharged through the diode Dsnb2 and inductor Lsnb , trans-

ferring energy to the capacitor Cs . All snubber circuits does

not change the static and dynamic operations of the power



Fig. 16. Modified SEPIC converter with magnetic coupling.

circuit, which acts only in the commutation periods, eliminating

the commutation losses and reducing the negative effects of the

reverse recovery current of all diodes.

G. Magnetic Coupling

The inductors L1 and L2 of the proposed converter presented

in Fig. 2 cannot be coupled as in the classical SEPIC topology

without changing significantly the operation characteristics pre-

sented in this paper. Therefore, the magnetic coupling of these

inductors is not analyzed for the proposed modification of the

SEPIC converter. The operation of the proposed converter with

isolation between the input and output with the inductor L2 op-

erating as a flyback transformer is possible, but is not presented

in this paper. The inductor L2 can also be used as a flyback

transformer without isolation, as presented in Fig. 16. The ad-

vantage of this modification is that the transformer turns ratio

(nLp2 /nLs2) allows the converter operation with a very high

static gain without increasing the power switch voltage.

Therefore, this modification can be interesting for low input

voltage and high output voltage applications.

H. Control System

The control algorithm of the proposed converter is based

on the classical structure of the average current-mode control

with the digital implementation and the power system operat-

ing in CCM. The design procedure of the control system for

the boost converter is well established and used in this imple-

mentation. The implementation of the control system for the

proposed converter is accomplished by using exactly the same

control designed for the classical boost converter. This approx-

imation is possible because the additional poles inserted by the

inductor L2 and capacitors CS and CM occur in a frequency

higher than the poles inserter by the inductor L1 and the output

filter capacitor Co . As presented in Section III-D, the capacitors

CS and CM are very small comparing with the output filter ca-

pacitor. The inductor L2 is also a fraction of the input inductor

L1 . As the crossing frequencies of the voltage and current con-

trol loops are lower than the frequency of the lower frequency

poles, the additional higher frequency poles does not present a

significant influence in the phase margin and the gain margin,

thus maintaining approximately the same dynamic response for

both power stage structures. In order to show this characteristic,

the same control algorithm designed for the classical boost con-

Fig. 17. Implemented prototype.

verter is used with the proposed converter and the experimental

results obtained confirm this consideration.

The simplified block diagram of the digital control system

utilized in the implementation of the high-RF rectifier is pre-

sented in Fig. 17. The control algorithm is developed using the

MC56F8013 digital signal controller operating with a sampling

rate equal to 24 kHz. The sample of the output voltage is com-

pared with a reference of the output voltage (Vref ). The error

signal obtained (Ev ) is applied to a digital proportional–integral

(PI) controller. The result obtained from the voltage controller

(VCv ) is multiplied by a sample of the rectified input voltage,

and the resultant signal is the reference waveform for the current

control loop (iref ). The sampling of the rectified input current

is compared with the current reference (Iref ). The result (Ei) is

applied to a digital PI controller. The output of the current con-

troller (VCi) is applied to the pulse width modulator, generating

the command signal of the power switch.

IV. EXPERIMENTAL RESULTS

The proposed converter presented in Fig. 15 is tested with the

implementation of an experimental prototype, and the perfor-

mance of the modified SEPIC converter is compared with the

classical boost converter.

A prototype of the classical boost is also built with the same

specification of the proposed converter. The power circuit with

the component’s parameters and a representation of the simpli-

fied block diagram of the digital control system are presented in

Fig. 17. The experimental waveforms are obtained with the ex-

perimental prototype operating with the nominal output power

Po = 650 W and with an input voltage changing from Vi =100 Vrms to Vi = 240 Vrms . The output voltage is regulated in

Vo = 425 Vdc . The input voltage and current waveform are pre-

sented in Fig. 18 for an input voltage equal to Vi = 127 Vrms .

The THDi obtained is equal to THDi = 5.49%, and the PF is

equal to PF = 0.99865. The THDi variation as a function of the



Fig. 18. Input voltage (Vi ) and current (Ii ) waveform for an input voltageVi = 127 Vrm s (100 V/division, 5 A/division, and 5 ms/division).

Fig. 19. Total current harmonic distortion as a function of the input voltagevariation.

Fig. 20. Power-factor variation as a function of the input voltage variation.

input voltage of the proposed converter and the classical boost

converter is shown in Fig. 19.

The PF variation as a function of the input voltage of the

proposed converter and the classical boost converter is shown

in Fig. 20.

The current waveform of the L1 input inductor and L2 in-

ductor of the proposed converter operating with Vi = 127 Vrms

are presented in Fig. 21. The measured current ripple of the

input current is equal to ∆iL1 = 1.5 A. The current waveform

of the input inductor of the classical boost converter operating

Fig. 21. L1 and L2 inductors current of the proposed converter operating withVi = 127 Vrm s (5 A/division and 5 ms/division).

Fig. 22. Input inductor current of the classical boost converter operating withVi = 127 Vrm s (2.5 A/division and 5 ms/division).

with Vi = 127 Vrms is presented in Fig. 22. The measured input

current ripple presented by the classical boost converter is equal

to ∆iL = 2 A, using the same value of the input inductor of the

modified SEPIC converter (L1 = Lboost = 1 mH).

Therefore, the modified SEPIC input current ripple is 25%

lower than the current ripple of the boost converter using the

same inductance value, as presented in Section III.

The voltage waveform of the capacitors CS and CM are

presented in Fig. 23 for an input voltage equal to Vi = 127 Vrms ,

and in Fig. 24, for an input voltage equal to Vi = 220 Vrms . The

experimental waveforms presented in Figs. 23 and 24 agree well

with the theoretical waveforms presented in Figs. 11 and 12,

considering as null the high-frequency capacitor voltage ripple.

The high-frequency voltage ripple presented in Fig. 23 is close

to 50 V.

A comparison of the switch voltage and current between the

proposed converter and the classical boost converter can be

done with the waveforms presented in Figs. 25 and 26. Fig. 25

shows the switch voltage and current of the proposed converter

operating with the nominal output power and an input voltage

equal to Vin = 127 Vrms .



Fig. 23. CS and CM capacitors voltage operating with Vi = 127 Vrm s

(100 V/division and 5 ms/division).

Fig. 24. CS and CM capacitors voltage operating with Vi = 220 Vrm s

(100 V/division and 5 ms/division).

Fig. 25. Switch current and voltage of the proposed converter operating withVi = 127 Vrm s (100 V/division, 5 A/division, and 5 ms/division).

Fig. 26. Switch current and voltage of the classical boost converter operatingwith Vi = 127 Vrm s (100 V/division, 5 A/division, and 5 ms/division).

Fig. 27. Turn-on and turn-off switch commutations of the proposed con-verter operating with Vi = 127 Vrm s (100 V/division, 5 A/division, and2.5 µs/division).

The switch voltage is equal to the CM capacitor voltage and

the maximum value is equal to VSmax = 320 V. The switch

peak current value is equal to IS = 10 A. The switch voltage

and current of the classical boost converter are shown in Fig. 26.

The switch voltage is equal to the output voltage and the

maximum value is equal to VSmax = 420 V. The switch peak

current value is equal to IS = 9 A.

The commutation improvement obtained with the regenera-

tive snubber presented in Fig. 15 is shown in Fig. 27. Fig. 27

presents the turn-on and turn-off commutations of the power

switch. As can be seen in this figure, the turn-on and turn-off

commutations are soft switching and the commutation losses are

minimized. The maximum switch voltage is equal to the CM

capacitor voltage with the snubber presented in Fig. 15. The

proposed snubber is effective in all ranges of the input voltage

variation and in all ranges of the output power variation.

Fig. 28 presents the switch commutation operating with light

load. As can be seen in this figure, the snubber circuit maintains

the reduction of the commutation losses.



Fig. 28. Turn-on and turn-off switch commutations of the proposed con-verter operating with Vi = 127 Vrm s (100 V/division, 2.5 A/division, and2.5 µs/division).

Fig. 29. Efficiency curve of the proposed converter and the classical boostconverter with and without nondissipative snubber as a function of the inputvoltage.

The efficiency curves of the proposed converter and the clas-

sical boost converter with hard switching and a nondissipative

snubber, operating with the nominal output power Po = 650 W,

are presented in Fig. 29. The highest efficiency is obtained with

the highest input voltage Vi = 240 Vrms , and is equal to 97.4%

for the proposed converter and 95.5% for the classical boost

converter.

The efficiency of the classical boost converter with the nondis-

sipative snubber is equal to 97.2%. The lowest efficiency is ob-

tained with the lowest input voltage Vi = 85 Vrms , and is equal

to 92.6% for the proposed converter and 89% for the boost

converter with the nondissipative snubber.

Therefore, the efficiency improvement with the proposed con-

verter in relation, the classical boost converter in the worst op-

eration condition is equal to 3.6%. The efficiency curves of the

proposed converter as a function of the output power and oper-

ating with the input voltage equal to 90, 127, 220, and 240 Vrms

are presented in Fig. 30.

The dynamic response of the high-PF rectifier implemented

with the modified SEPIC and the classical boost converters are

presented in Figs. 31 and 32, respectively. Fig. 31 presents the

output voltage (Vo ) and the input inductor current (iL1) of the

Fig. 30. Efficiency curves of the proposed converter as a function of the outputpower.

Fig. 31. Output voltage (Vo ) and input inductor current (iL 1 ) of the proposedconverter operating with Vi = 127 Vrm s and with the output power reductionfrom 650 to 300 W (100 V/division, 2.5 A/division, and 50 ms/division).

Fig. 32. Output voltage (Vo ) and input inductor current (iLboost ) of theclassical boost converter operating with Vi = 127 Vrm s and with the out-put power reduction from 650 to 300 W (100 V/division, 2.5 A/division, and50 ms/division).

proposed converter operating with an input voltage equal to

Vi = 127 V. The output power is reduced from the nominal

value Po = 650 W to Po = 300 W. The output voltage rises

from the nominal value Vo = 425 V to the maximum value

Vo = 475 V during the load transient. The transient duration is

equal to 150 ms. Fig. 32 presents the output voltage (Vo ) and the



input inductor current (iLboost) of the classical boost converter

operating with the same specifications of the proposed converter.

The output power is reduced from the nominal value Po =650 W to Po = 300 W, and the output voltage rises from the

nominal value Vo = 425 V to the maximum value Vo = 465 V

during the load transient. The transient duration is also 150 ms.

Therefore, the overshoot of the output voltage presented by the

proposed converter is equal to 11.76%, and the overshoot of the

classical boost converter is equal to 9.4% for the same controller

parameters.

V. CONCLUSION

A modified version of the SEPIC converter is proposed for the

implementation of a high-PF rectifier suitable for universal line

application. Although the proposed structure presents a higher

circuit complexity than the classical boost converter, the advan-

tages obtained are the higher static gain for the operation with

the lower input voltage range, lower switch voltage operation,

higher efficiency operation with the lowest input voltage, lower

input current ripple, and easy integration with a regenerative

snubber. Three snubber circuits are proposed in order to ob-

tain a reduction of the diode reverse recovery current problem,

and also obtaining turn-on and turn-off soft switching for all

input voltage ranges and output power variation. The average

current-mode control is used for the classical boost converter

and also for the proposed converter, and the dynamic response

obtained with both converters is approximately the same. The

experimental results are obtained with the implementation of

a rectifier with an output power equal to Po = 650 W, using

the boost and the modified SEPIC converters, and the efficiency

improvement with the proposed topology is equal to 3.6% for

the worst operation condition.

REFERENCES

[1] Y. Jang and M. M. Jovanovic, “Interleaved boost converter with intrinsicvoltage-doubler characteristic for universal-line PFC front end,” IEEE

Trans. Power Electron., vol. 22, no. 4, pp. 1394–1401, Jul. 2007.[2] O. Garcıa, J. A. Cobos, R. Prieto, P. Alou, and J. Uceda, “Single phase

power factor correction: A survey,” IEEE Trans. Power Electron., vol. 18,no. 3, pp. 749–755, May 2003.

[3] B. Singh, B. N. Singh, A. Chandra, K. Al-Haddad, A. Pandey, andD. P. Kothari, “A review of single-phase improved power quality AC–DC converters,” IEEE Trans. Ind. Electron., vol. 50, no. 5, pp. 962–981,Oct. 2003.

[4] M. M. Jovanovic and Y. Jang, “State-of-the-art, single-phase, active power-factor correction techniques for high-power applications—An overview,”IEEE Trans. Ind. Electron., vol. 52, no. 3, pp. 701–708, Jun. 2005.

[5] J. Zhang, M. M. Jovanovic, and F. C. Lee, “Comparison between CCMsingle-stage and two-stage boost PFC converters,” in Proc. Appl. Power

Electron. Conf. Expo. (APEC), Mar. 1999, vol. 1, pp. 335–341.[6] J. Chen, D. Maksimovic, and R. W. Erickson, “Analysis and design of

a low-stress buck-boost converter in universal-input PFC applications,”IEEE Trans. Power Electron., vol. 21, no. 2, pp. 320–329, Mar. 2006.

[7] C. Qiao and K. M. Smedley, “A universal input single-phase single-stagepower supply with power factor correction and automatic voltage clamp-ing,” in Proc. Power Electron. Spec. Conf. (PESC), Jun. 2001, pp. 907–913.

[8] D. D. C. Lu, H. H. C. Iu, and V. Pjevalica, “A single-stage AC/DC converterwith high power factor, regulated bus voltage, and output voltage,” IEEE

Trans. Power Electron., vol. 23, no. 1, pp. 218–228, Jan. 2008.[9] J. Qian, Q. Zhao, and F. C. Lee, “Single-stage single-switch power factor

correction ac/dc converters with dc-bus voltage feedback for universal line

application,” IEEE Trans. Power Electron., vol. 13, no. 6, pp. 1079–1098,Nov. 1998.

[10] J. Qian and F. C. Lee, “A high efficient single stage single switch highpower factor ac/dc converter with universal input,” IEEE Trans. Power

Electron., vol. 13, no. 4, pp. 699–705, Jul. 1998.[11] L. Huber and M. M. Jovanovic, “Single stage single switch isolated power

supply technique with input current shaping and fast output voltage regu-lation for universal input voltage range applications,” in Proc. IEEE Appl.

Power Electron. Conf. Expo. (APEC), 1997, pp. 272–280.[12] C. Qiao and K. M. Smedley, “A topology survey of single-stage power

factor corrector with a boost type input current-shaper,” IEEE Trans.

Power Electron., vol. 16, no. 3, pp. 360–368, May 2001.[13] M. H. L. Chow, Y. S. Lee, and C. K. Tse, “Single-stage single-switch

isolated PFC regulator with unity power factor, fast transient response,and low-voltage stress,” IEEE Trans. Power Electron., vol. 15, no. 1,pp. 156–163, Jan. 2000.

[14] J. L. Lin, W. K. Yao, and S. P. Yang, “Analysis and design for a novelsingle-stage high power factor correction diagonal half-bridge forwardac-dc converter,” IEEE Trans. Power Electron., vol. 53, no. 10, pp. 2274–2286, Oct. 2006.

[15] Q. Zhao and F. C. Lee, “High-efficiency, high step-up DC–DC converters,”IEEE Trans. Power Electron., vol. 18, no. 1, pp. 65–73, Jan. 2003.

[16] R.-J. Wai and R.-Y. Duan, “High step-up converter with coupled-inductor,”IEEE Trans. Power Electron., vol. 20, no. 5, pp. 1025–1035, Sep. 2005.

[17] R.-J. Wai and R.-Y. Duan, “High-efficiency power conversion for lowpower fuel cell generation system,” IEEE Trans. Power Electron., vol. 20,no. 4, pp. 847–856, Jul. 2005.

[18] M. Prudente, L. L. Pfitscher, G. Emmendoerfer, E. F. R. Romaneli, andR. Gules, “Voltage multiplier cells applied to non-isolated DC–DC con-verters,” IEEE Trans. Power Electron., vol. 23, no. 2, pp. 871–887, Mar.2008.

[19] K. M. Smith, Jr. and K. M. Smedley, “Engineering design of lossless pas-sive soft switching methods for PWM converters—Part I: With minimumvoltage stress circuit cells,” IEEE Trans. Power Electron., vol. 16, no. 3,pp. 336–344, May 2001.

[20] C. M. C. Duarte and I. Barbi, “A new ZVS-PWM active-clamping highpower factor rectifier: Analysis, design and experimentation,” in Proc.

Appl. Power Electron. Conf. Expo. (APEC), Feb. 1998, vol. 1, pp. 230–236.

[21] H. M. Suryawanshi, M. R. Ramteke, K. L. Thakre, and V. B. Borghate,“Unity-power-factor operation of three-phase AC–DC soft switched con-verter based on boost active clamp topology in modular approach,” IEEE

Trans. Power Electron., vol. 23, no. 1, pp. 229–236, Jan. 2008.

Priscila Facco de Melo was born in Curitiba, Brazil,in 1984. She received the B.S. degree in electrical en-gineering from the Federal Technological Universityof Parana, Curitiba, in 2008, where she is currentlyworking toward the M.S. degree.

Her current research interests include power elec-tronics, power quality, and digital control.

Roger Gules (M’09) was born in Bento Goncalves,Rio Grande do Sul, Brazil, in 1971. He received theB.S. degree from the Federal University of SantaMaria, Rio Grande do Sul, and the M.S. and Ph.D. de-grees from the Federal University of Santa Catarina,Florianopolis, Brazil, in 1998 and 2001, respectively.

From 2001 to 2005, he was a Professor at theUniversidade do Vale do Rio dos Sinos, Rio Grandedo Sul. Since 2006, he has been a Professor at theFederal Technological University of Parana, Curitiba,Brazil. His current research interests include power-

switching converters and renewable energy applications.



Eduardo Felix Ribeiro Romaneli received the B.S.degree, and the Master’s and Doctorate degrees inelectrical engineering from the Federal University ofSanta Catarina, Florianopolis, Brazil, in 1993, 1998,and 2001, respectively.

Since 2003, he has been a Full-Time Professorat the Federal Technological University of Parana,Curitiba, Brazil. His research has spanned a severaldisciplines, emphasizing power electronics. His cur-rent research interests are focused but not restrictedto uninterruptible power system (UPS), power-factor

correction, and digital control.

Rafael Christiano Annunziato was born in Curitiba,Brazil, in 1978. He is currently working toward thedegree in technology of automation at the FederalTechnology University of Parana, Curitiba.

Since 1997, he has been with the National HealthService (NHS) Sistemas Eletronicos Ltda, Curitiba,where he has been engaged in the development ofpower electronics and microcontroller’s firmware foruninterruptible power system (UPS). His current re-search interests include power converters and digitalcontrol applied to UPS and power-correction factor.


Documents

A Modified SEPIC Converter for High power factor Rectifier and Universal Input Voltage Applications