A MIM-cap free digitally tunable NMOS capacitor

Anthony Thomas1,2, Winfried Bakalski1, Thomas Ussmuller2 and Robert Weigel2

1Infineon Technologies, RF and Protection Devices, Neubiberg, 85579, Germany2University of Erlangen Nuremberg, 91058 Erlangen, Germany

Abstract—A novel approach of digitally tunable capacitorsusing only NMOS transistors of a Bulk-CMOS process is pre-sented. Instead of using MIM-capacitors, stacked transistors areused to tune the capacitance value and have an additional low lossthrough mode. Using the 0.13µm Bulk CMOS triple well processfrom Infineon Technologies, the device features a tuning range of0.2 to 3.0 pF with a maximum Q of 90 at 900 MHz. The throughmode shows an insertion loss of only 0.2 dB at 900 MHz. Includingthe MIPI control interface, voltage regulator and charge-pump,the Chip size is only 1100µm x 900µm. Current consumption isabout 110µA at 3.5 V operation. The design is cost effective, asno MIM capacitances are required.

Keywords—Antenna, adaptive matching, capacitance, Q.factor,transistors.

I. INTRODUCTION

The increasing amount of frequency bands and functional-ity in wireless equipment implies the increased need on tunabledevices. Applications like RF filters and RF matching becomemore a need to address higher amounts of frequency bandcombinations while maintaining a limited PCB or chip area.Furthermore as digital to analog conversion takes chipsize andsuffers also from nonideal behavior, are native digital controlis prefered. In combination with the MIPI/RFFE standard [1],multiple tunable devices can be combined. However tunablecapacitors have several compromises in common [2]:

• Quality factor. The higher the Q value, the lowerthe losses, the limitations are usually given by seriesresistance elements.

• Tuning ratio. The tuning ratio is limited by the topol-ogy, the required Q factors and the transistor parasiticsas well as package parasitics. For example bumpcapacitance can summarize up to some 100 fF, limitinga minimum capacitance.

• Linearity. Especially for voltage dependent capacitors,nonlinearites are a product of the rf voltage itself,causing the capacitance to change. Harmonic productsare usually resulting from such effects.

• Maximum RF voltage. Any capacitance has a voltagelimit. For MIM caps the dielectric lifetime and break-down behavior, for transistors breakdown voltages andstress.

• ESD ruggedness. Capacitors in semiconductors gener-ally suffer from ESD weakness, as long as no furtherprotection is used.

• Chip-size. Especially high voltages lead to low spe-cific capacitances or high transistors stackings. As

a result chip size increases to maintain a certain Qfactor.

The aim of the design is the avoidance of ESD sensitive MIM-caps and the realization of high tuning ranges. The structurehas the potential to achieve very high tuning ranges whilemaintaining high Q factors.

II. TECHNOLOGY AND REALISATION

Fig. 1. Chip photography of the digital tunable capacitor. The chipsize is1.1 x 0.9 mm2

The chip in Fig. 1 was manufactured in the Infineon 130 nmtriple well RF Switch Process C11NP. It features all logictransistors such as NMOS and PMOS in the triple-well, IOtransistors, and furthermore optional high-Q MIM-capacitorsand the RF switch transistors placed in the bulk with a deviceRonCoff figure of merit of 180fs. The chip integrates a charge-pump for negative bulk bias, a voltage regulator and a digitalcontrol interface acording to the MIPI/RFFE standard [1]. Foroperation a supply of 2.5 V to 5 V and a current of 100µA isrequired. Using bumps, the chip can be mounted flip-chip asa chip-scale package (CSP).

III. STATE OF THE ART CIRCUIT DESIGN

Todays state-of the art digital tunable capacitors rely on aswitching element. However switches are non-ideal, and thebasic parasitics are the series resistance in ON-mode RON

and the OFF-Capacitance COFF as shown in Fig. 2. The ON-mode is usually obtained by forcing the transistor into stronginversion. In the used process by applying the maximum gatevoltage of 1.5 V via a high ohmic resistor to the gate fingers.The OFF-mode is realized by deep subtreshold operation usinga negative gate voltage of -1.5 V. The negative voltage isusually generated by an on-chip charge pump [3]. As one can

see, a level shifter is required for each switch to transfer thelogic signal into a positive or negative gate voltage.

NMOS

-VGATE

NMOS

+VGATE

COFF

RON

Fig. 2. The NMOS transistor acting as a switch device.

Using this RF switch, todays digital tunable capacitorsare designed using the series circuit of a cap and a switchdevice [4], weighted by N bits, with LSB (least significantbit) representing the smallest capacitance step and MSB (mostsignificant bit) as the maximum switchable capacitance bit.Fig. 3 shows the usual circuit.

+/-VGATE

...

...

+/-VGATE

...

...

+/-VGATE

...

...

W s

cale

s w

ith C

Switch

High-Q MIM

LSB MSB

M s

tacked

Devic

es

M s

tacked

Devic

es

M s

tacked

Devic

es

... „N Bits“=

Fig. 3. State-of-art digital tunable capacitor.

The main trade-offs for this circuit are :

• ESD ruggedness is directly related to the MIM ESDperformance.

• The maximum allowed voltage of the capacitors. Toachieve higher maximum voltages, several capacitorshave to be switched in series.

• The maximum RF transistor voltage. This usuallylimited by the ”OFF”-mode of the switches, when theimpedance of the RF switch paths are far bigger thanthe capacitances, leading in a high RF voltage swingat the port of the stacked transistors.

• The required Q-factor. For a high capacitance, a verylow RON of the transistor is required.

• The minimum capacitance Cmin which is resultingfrom the maximum capacitance switched in series tothe overall COFF capacitance resulting from the tran-sistors. Taking for simplicity a maximum capacitanceof 10 pF and a COFF = 0.5 pF, the resulting Cmin can

not be below 0.48 pF. As COFF scales with transistorwidth and this reciprocal to RON , one can see, thatit ends up in a trade-off between tuning ratio and Q-factor.

IV. THE NMOS-BASED TUNABLE CAPACITANCE

The main idea to achieve an alternative approach is theusage of the parasitic capacitance of a NMOS transistor itself.Hence, Using transistors of very high width automaticallyincreases the parasitic capacitances, in switch processes dom-inated by CGS and CGD. Increasing the transistor width intothe multi-mm region shifts the COFF into capacitance valuesof several pF. On the other hand, its high width leads to avery low RON . An additional effect of very high capacitancevalues is the limitation of RF voltage over the transistor, so thatthe capacitance automatically protects the transistor. Placingthe high width transistors in series, a tunable capacitor canbe realized just by the use of the parasitics. Fig. 4 shows thecircuit diagram.

+/-

VG

AT

E

...N

+/-

VG

AT

E

+/-

VG

AT

E

COFF

RON

COFF

RON

COFF

RON

COFF

RON

Fig. 4. The NMOS based tunable capacitance.

In comparison to Fig. 3, the structure has a different be-havior:

• The minimum capacitance and thus the tuning ratiois given by the stacking and not by the parasiticcapacitance itself.

• In case all transistors are switched to ON-mode, a verylow loss bypass is found, due to the high transistorwidth and the low RON . Thus, the structure is inher-ently a Single-Pole-Single-Throw switch (SPST).

• The Q factor is generally high due to its high transistorwidthes and low RON . For low capacitances, the Qfactor is high as well, as only parasitic capacitance isused. However it is in fact limited by the values ofdischarge resistors and gate resistors.

• The structure gives more steps in the low capacitancerange as for high capacitances. However this behaviorcan be changed by different transistor widths in thecircuit.

• The maximum voltage is not identical over all states,however the higher the COFF is selected, the lowerthe voltage stress will be.

• The ESD ruggedness is only limited by the switchprocess technology used.

It is important to mention that this structure can only work,as long as the main capacitance contributor are the overlap

capacitances CGS and CGD is dominant. For this purpose,the substrate diodes have to be deactived. This is done by theusage of a negative substrate bias in combination with a lowconductive substrate. In this case, the bulk bias generated bythe same integrated charge-pump as required for the negativegate voltage to operate transistors in the deep subthresholdregion.

As this structure has N states, with N representing theamount of stacked transistors, a decoder to thermometer-codehelps to reduce the amount of control bits. In the presentedtest-chip one RFFE register is mapped to a parallel to ther-mometercode decoder to address 16 transistors. In fact only 4bits are required to adjust the required frequency. The state N-1represents the ”all-ON” state, which is in series configurationa through mode. Finally all N transistors require its own levelshifter to control each transistor. The main difference to a usualRF switch is, that the level shifter drives only one transistor.for less capacitances variation between states, it would bepossible to stack double transistors for the same amount ofcontrol bits, thus, offering two times less capacitances but finercapacitances steps.

V. MEASUREMENT RESULTS

Fig. 5 shows the test board. The chip was measured inseries configuration using a flip-chip package. All states weresweeped to obtain all capacitance values. Finally, capacitancevalues and Q factors extracted.

Fig. 5. Flip-chip mounted capacitance tuner used for the measurement.

Fig. 6 shows the adjustable capacitances. In the given test-chip, the capacitance can be tuned between 0.2 pF and 3 pF. Bylooking at the curve of capacitance versus steps, it appears thatthe curve follows as expected, the COFF of a single NMOSover the ratio of all OFF transistors. Thus, for double sizedtransistors, one could even reach higher capacitances.The first half states could be definitely useful for high fre-quencies due to their fine steps. This is an advantage of thistopology compared with the capacitance bank in Fig. 3 whichis limited by his overall COFF .

The corresponding Q factor is shown in Fig. 7 for 900 MHzand 1.8 GHz. The Through mode related with the test chipshows an insertion loss of 0.2 dB at 900 MHz and 0.27 dB at1.8 GHz.

0 0.2 0.4 0.6 0.8

1 1.2 1.4 1.6 1.8

2 2.2 2.4 2.6 2.8

3 3.2 3.4

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14

Capacitance [pF

]

State

TRC1

Fig. 6. Adjustable capacitance values vs. logic state.

0

10

20

30

40

50

60

70

80

90

100

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14

Q facto

r

State

Q at 900MHzQ at 1800MHz

Fig. 7. Measured Q factor vs logic state.

To evaluate the linearity of the device, the harmonicsgeneration measurement setup in Fig. 8 is used. A constantwave signal is generated in pulse mode with 50 % duty cycleand 577 Hz pulse width and amplified using a power amplifier(PA). To ensure no damage or harmonics or other spurs due tooutput mismatch, an isolator is placed at the PA output. Also anadditional low pass filter at input and high pass filter at outputare placed respectively to filter out the potential 2nd and 3rdharmonics generated by the DUT from the input and isolatethe fundamental input signal from the spectrum analyser toobtain the required dynamic range. As a capacitor can be usedin different combinations, two configurations have to be tested.One would be the series configuration, here using the bypassmode and the other the shunt configuration, setting the deviceto minimum capacitance. In shunt configuration, usually thehigh RF voltage is seen by the device.

The Fig. 9 and the Fig. 10 presents the 2nd and 3nd har-monic generation vs. input power of the test chip in ON-modeand OFF-mode respectively in parallel and series configurationat 824 MHz.

Addtionally, the MIM-cap free design provides excellent

50

W

Spectrum

AnalyserDUT

Off Mode

On Mode

DUT

DUT

Fig. 8. Harmonic measurement Setup of the DUT.

-110

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

0

20 22 24 26 28 30 32 34 36 38

Harm

onic

level [d

Bm

]

Pin [dBm] 824MHz

H2 [dBm] state 0 parallelH3 [dBm] state 0 parallel

Fig. 9. 2nd and 3rd generated harmonics versus input power in parallel onOFF-mode position at 824 MHz.

-110

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

0

20 22 24 26 28 30 32 34 36 38

Harm

onic

level [d

Bm

]

Pin [dBm] 824MHz

H2 [dBm] state 15 seriesH3 [dBm] state 15 series

Fig. 10. 2nd and 3rd generated harmonics versus input power in series onON-mode position at 824 MHz.

ESD behavior. This is proved using Transmission Line Pulse(TLP) measurements. The structure can handle more than 2 kVof ESD discharge according to the human body model.

VI. TECHNOLOGY COMPARISONS

Recent Works in specialized technologies like BariumStrontium Titanat (BST) [5] and MEMS [6] show interestingresults as variable capacitors. Whereas CMOS switch based

circuits are inherently digital devices, BST is by nature avaractor. Thinking of digital interfaces, varactors imply theneed on Digital Analog Converters (DAC) and thus haveall their drawbacks. MEMS are found in a lot of differentconfigurations and types. To compare BST, typical MEMSand this approach some key figures are summarized in theTable. I. The major advantage of a CMOS capacitance bank isthat the tuning range can easily be extended, and that a digitaldevice as shown here is not impacted by temperature, analogcontrol voltages and has no limitations in switching cylces. Aswell switching times are by far better than MEMS or BST.However, in terms of losses, MEMs present higher qualityfactor at 1 GHz, but suffer from all mechanic disadvantagessuch as limited switching cycles or microphony effects. BSTvaractors have always inherent linearity problems due to theirvaractor nature and feature a very low tuning range. On topBSTs can not be integrated today into silicon and require anexternal controller consuming 10 times more current than othersolutions [7]. Regarding MEMS, a high voltage is requiredto commutate the switches and improve the switching timebetween maximum and minimum states [8].

TABLE I. COMPARISON BETWEEN DIFFERENT TECHNOLOGIES OFTUNABLE CAPACITANCES

Type BST Varactor[5] MEMS [6] This WorkCurrent consumption ∼1 mA ∼100µA 110µA

Value (pF) 0.3-1.2 0.13-1.27 0.2-3Tuning Range 4 10 15

Q factor(Max) @1 GHz 90 160 85Logic Control External integrated integrated

Switching time (µs) 70 >10 [8] <2

VII. CONCLUSION

A novel method of tunable capacitance is presented onthis paper. It shows a concept based on stacked transistorsusing drain source capacitance in order to generate a tunablecapacitor. The capacitance can be changed from 0.2 pF until3.0 pF with a low loss bypass mode of 0.2 dB at 900 MHz. and0.27 dB at 1800 MHz. The structure has a Q factor of up to 90at 900 MHz, while not requiring any high Q MIM capacitance.

REFERENCES

[1] MIPI Alliance, “RF Front-End Specifications,”http://www.mipi.org/specifications/rf-front-end.

[2] R. Novak, “IWPC Tunable Components and Platform Architectures forSmartphone,” Presentation at IWPC 2012, November 2012.

[3] F. Pan and T. Samaddar, Charge Pump Circuit Design. New York, USA:McGraw-Hill, 2006.

[4] R. Whatley, T. Ranta, and D. Kelly, “CMOS Based Tunable MatchingNetworks for Cellular Handset Applications,” Proceedings of the Inter-nation Microwave Symposium 2011, 2011.

[5] “BST passive tunable integrated circuit,” ON semiconductors,http://www.onsemi.com/pub link/Collateral/TCP-3012H-D.PDF.

[6] D. DeReus et al., “Tunable capacitor series/shunt design for integratedtunable wireless front end applications,” MEMS, 2011 IEEE 24th Inter-national Conference, pp. 805–808, Jan. 2011.

[7] “Passive tunable integrated circuit control IC,” ON semiconductors,http://www.onsemi.com/pub link/Collateral/TCC-103-D.PDF.

[8] A. Tazzoli et al., “Electrostatic discharge and cycling effects on ohmicand capacitive rf-mems switches,” IEEE Transactions on Device andMaterials Reliabiliy, pp. 429–437, 2007.