Lecture 15

A Manual Processor Part Two

Hardware Lecture 15 Slide 1

The Manual Processor Data Path Diagram

Last lecture we designed the hardware blocks for amanual processor:

Hardware Lecture 15 Slide 2

The Manual Processor Data Path Diagram

Blocks A, B, IR and Res are simple registers with eightbits:

Block C is a one bit register, ie a D-Q flip-flop

Hardware Lecture 15 Slide 3

The Manual Processor Data Path Diagram

The boxes marked MUX are multiplexers - which can bethought of as switches.

The multiplexer selecting the input to register C is asingle switch:

The multiplexer selecting the inputs to A and RES haveeight single switches with a common control line.

Hardware Lecture 15 Slide 4

The Manual Processor Data Path Diagram

The box marked ALU is the arithmetic and logic unitwhich is a combinational circuit.

Select 000 001 010 011 100 101 110 111Function 0 B-A A-B A plus B A xor B A+B A.B -1

Hardware Lecture 15 Slide 5

The Manual Processor Data Path Diagram

The box marked shifter is also a purely combinationalcircuit providing seven different shifts:

F[2] F[1] F[0] Shift Carry Function0 0 0 unchanged0 0 1 left rotate left0 1 0 left 0 arithmetic left shift0 1 1 left Cin left shift with carry1 0 0 right rotate right1 0 1 right 0 logical right shift1 1 0 right Input[7] arithmetic right shift1 1 1 right Cin shift right with carry

NB: In this simple processor we are not using the Cin ofthe shifter. It will be set to 0.

Hardware Lecture 15 Slide 6

The Manual Processor Controller

The next step is to design the controller.

This is a circuit which makes the processor go throughthe correct steps to execute an instruction.

It is of course a synchronous sequential circuit.

Before we can design it we need to look at how theinstructions are represented

Hardware Lecture 15 Slide 7

Instruction Format

The Instruction Register IR

The multiplexers are controlled from bits 0, 1 and 2 ofthe instruction register:

S/A Selects the input to the A register0 selects shifter output, 1 selects Data Input.

S/C Selects the input to the “Carry in” of the ALU:0 selects logic 1, 1 selects C-out

S/R Selects the input to the RES register0 selects the shifter, 1 selects ALU

Hardware Lecture 15 Slide 8

Instruction Format

The Instruction Register IR

F/ALU-SHIFTER, bits 6,5,and 4 of the register determinethe functions of the arithmetic circuits:

For the ALU:

000 001 010 011 100 101 110 1110 B-A A-B A plus B A xor B A+B A.B -1

Hardware Lecture 15 Slide 9

Instruction Format

The Instruction Register IR

F/ALU-SHIFTER, bits 6,5,and 4 of the register determinethe functions of the arithmetic circuits:

For the Shifter:

000 - No shift001 - Rotate Left

etc.

Hardware Lecture 15 Slide 10

Instruction Format

The Instruction Register IR

Bits 3 and 7 are unused.

They are reserved for future enhancements.

Hardware Lecture 15 Slide 11

Control Unit Functions

The controller must provide the necessary steps toexecute an instruction.

Hardware Lecture 15 Slide 12

The Execution Cycle

An instruction will take five steps to execute as follows:

1. Load the IR register.

2. Load the A register

3. Load the B and the C registers

4. Load the IR register

5. Load the RES and the C registers

We will assume that the Data Input lines will hold thecorrect byte at each step. They will be externallyprogrammed.

Hardware Lecture 15 Slide 13

The Execution Cycle

To implement the execution cycle we need a five statesynchronous sequential circuit.

Hardware Lecture 15 Slide 14

Programming the Manual Processor

The execution cycle implicitlydefines the format of the pro-gramme.

At each of the five executionsteps the correct data will beplaced on the Data Input linesby an external program.

We will see how this is donenext lecture.

Hardware Lecture 15 Slide 15

The Execute Cycle

We now look at the execute cycle in more detail

Hardware Lecture 15 Slide 16

The Execute Cycle

Execution Step 1: The Instruction register (IR) is loadedfrom the Data In lines

Hardware Lecture 15 Slide 17

The Execute Cycle

Execution Step 2: Register A is loaded - for example fromthe Data In lines

Hardware Lecture 15 Slide 18

The Execute Cycle

Execution Step 3: Registers B and C are loaded

Hardware Lecture 15 Slide 19

The Execute Cycle

Execution Step 4: The Instruction register (IR) is loadedfrom the Data In lines

Hardware Lecture 15 Slide 20

The Execute Cycle

Execution Step 5: registers RES and C are loaded

Hardware Lecture 15 Slide 21

The Execute Cycle

Execution Step 1 (again): The Instruction register (IR) isloaded from the Data In lines

Hardware Lecture 15 Slide 22

The Execute Cycle

Execution Step 2 (again): Register A is loaded - forexample from the arithmetic result of the ALU

Hardware Lecture 15 Slide 23

The Execute Cycle

The cycle continues in the same way while the processoris being operated, taking data and instructions from theData In lines and putting the results on the Data Outlines.

The design of the control unit which implements thiscycle follows our (now very familiar) methodology.

Hardware Lecture 15 Slide 24

The Output Logic

We choose a stateassignment that wehope will minimisethe output logic.

Q2Q1Q0 State Output Signal000 0 none001 1 ClkIR100 2 ClkA010 3 ClkB, ClkC101 4 ClkIR110 5 ClkC, ClkRES

Hardware Lecture 15 Slide 25

The State Transition table

Operate State Now Q2Q1Q0 Next State D2 D1 D00 0 000 0 0 0 00 1 001 0 0 0 00 2 100 0 0 0 00 3 010 0 0 0 00 4 101 0 0 0 00 5 110 0 0 0 00 6 011 × × × ×0 7 111 × × × ×1 0 000 1 0 0 11 1 001 2 1 0 01 2 100 3 0 1 01 3 010 4 1 0 11 4 101 5 1 1 01 5 110 1 0 0 11 6 011 × × × ×1 7 111 × × × ×

Hardware Lecture 15 Slide 26

The State Transition Minimised Equations

Hardware Lecture 15 Slide 27

Checking the “don’t cares”

Operate State Now Q2Q1Q0 Next State D2 D1 D0

0 6 011 0 0 0 00 7 111 0 0 0 01 6 011 4 1 0 11 7 111 4 1 0 1

Thus, if the OPERATE input is at logical 0 the systemdrops into the IDLE state immediately and the processoris ready to start working properly.

It would make sense to ensure that this is the case whenwe switch the processor on.

Hardware Lecture 15 Slide 28

The Output Logic Again

The output logic is to provide a clock edge (for example afalling clock edge) to the registers that are to be loaded ateach step.

We can do this by gating the system clock which is timingeach step of the execution. For example, for register A:

This arrangement would mean that the controller stateregister and the processor registers change on the sameclock edge - a race hazard occurs!

Hardware Lecture 15 Slide 29

The Output Logic Again

To make sure the circuit operates correctly we make thestate register change on the falling edge of the clock andthe processor registers change on the next rising edge ofthe clock.

Using a NAND gate does the trick:

Hardware Lecture 15 Slide 30

Executing a program

We now look at what happens when we execute aprogram that finds the mean of two numbers (A+B)/2.This will take two execute cycles.

Compute (A+B)/2

0 Set the OPERATE input to 0 The processor is put into theIDLE state.

1 Set the Data In lines tox000xxx1 and the OPERATEinput to 1

The instruction x000xxx1 isloaded in the IR, after which theALU output and Cout are set to 0and the Sel A multiplexer selectsthe Data In lines.

2 Set the Data In lines to Num-ber A

IR0=1 and so the Data In linesare loaded into register A.

3 Set the Data In lines to Num-ber B

The Data In lines are loaded intoregister B and 0 is loaded intoregister C.

Hardware Lecture 15 Slide 31

Executing a program

Compute (A+B)/2

4 Set the Data In lines tox011x11x

The instruction x011x11x isloaded in the IR, after which theALU output is set to A plus B andthe Sel RES multiplexer selectsthe ALU output. The Sel C multi-plexer selects the C register mak-ing Cin=0.

5 - The intermediate result ”A plusB” is loaded into the RES regis-ter, the C bit indicates whetherthere has been an overflow.

Hardware Lecture 15 Slide 32

Executing a program

The Second Execute Cycle

1 Set the Data In lines tox011x110

The instruction x011x110 isloaded in the IR, after which theALU output remains as (A plus B)and the Sel A and Sel RES mul-tiplexers selects the result of theALU.

2 - The ALU output (A plus B) isloaded into register A.

3 - Register B is loaded with what-ever happens to be on the DataIn lines - it isn’t being used now.C is loaded with the ALU/Coutagain.

Hardware Lecture 15 Slide 33

Executing a program

Compute (A+B)/2

4 Set the Data In lines tox110x0xx

The instruction x110x0xx isloaded in the IR, after which theshifter function is set to Arith-metic Right Shift and the Sel RESmultiplexer selects the shifteroutput.

5 - The final result (A plus B)/2 isloaded into the RES register. Thecarry out is not needed for thisinstruction. It will in fact be 0.

Set Operate=0 to put theprocessor in the idle state

Hardware Lecture 15 Slide 34

At last:

We have succeeded in executing two simple programinstructions!

We’ll take a look at how to get the instructions and datafrom memory and how to store the results next time.

Hardware Lecture 15 Slide 35