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MANGO GREEN
RMD
8
Ashish Syal
34
129-01-2016_11:36
152500905
PROJECT
SCHEMATIC
DATE/TIME
PAGE
SITE
LEAD ENGINEER
REV SCH REV PCB
1 2 3 4 5 6 7 8 9 10 11
A
B
C
D
E
F
G
H
I
J
OF
This document contains information which
is proprietary to Sierra Wireless Inc. and is
licensed pursuant to Creative Commons
Attribution 4.0 International License.
Copyright (C) 2016
SHEET 2 CONNECTORS
SHEET 3 RF, VBACKUP,USB
SHEET 4 RESET,JTAG,uC prog,control
SHEET 5 AUDIO (ANALOG & PCM)
SHEET 6 CONNECTORS & Headers
SHEET 7 UART, LEDs, ADC,Level Shifter
SHEET 8 UIMs & SD CARD
SHEET 9 GPIO, SPI,UART, SDIO,PCM Expanders
SHEET 10 IOT connectors,Sensors
SHEET 11 USB, Ethernet expansion
SHEET 1 TABLE OF CONTENTS
SHEET 14 5V boost, 3V3 buck, 1V8 Buck
REFERENCE1600643 PCA, MANGOH1401063 PCB, MANGOH
MangoH Green Platform
MIC_CTIA
MIC_OMTP
Variants descriptionDNI = Do Not InstallUFL_M_RF = Add U.FL conn. on Main CF3 (do not define SMA_RF)SMA_RF = Add SMA conn. on Main CF3 (do not define UFL_M_RF)MIC_OMTP = OMTP headphones config (do not define MIC_CTIA)MIC_CTIA = CTIA/AHJ headphones config (do not define MIC_OMTP)
SMA_RF
SHEET 15 Arduino connection
SHEET 13 Battery Charger
SHEET 12 PSU Front end, 3.7V DCDCI2C address list08h = 3503 USB hub3Eh = I/O expander 13Fh = I/O expander 255h = Battery gauge6Ah = Accelerometer sensor6Bh = Buck+batt charger70h = I/O expander 371h = I2C Hub
UFL_M_RF
DNI
Project Variants
1600643
N
Y
N
N
Y
MANGO GREEN
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Ashish Syal
See P1
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152500905
PROJECT
SCHEMATIC
DATE/TIME
PAGE
SITE
LEAD ENGINEER
REV SCH REV PCB
1 2 3 4 5 6 7 8 9 10 11
A
B
C
D
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H
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J
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This document contains information which
is proprietary to Sierra Wireless Inc. and is
licensed pursuant to Creative Commons
Attribution 4.0 International License.
Copyright (C) 2016
VBATT_BB
DNI
CN2011
0R222
12pF
C23
6
0R220
VBATT_BB
VGPIO
SW200
PTS810 SJK 250 SMTR LFS
43
21
UIM1_VCC
0R225
DNI
R24
2
2.2K 1%
0R
229
VBATT_RF
VBATT_BB
UIM2_VCC
TP210TESTPOINT_0650_RND_0350H
0R227
VBATT_RF
VCC_3V7
VCC_2V95
TP211TESTPOINT_0650_RND_0350H
TP212TESTPOINT_0650_RND_0350H
DNI
CN2021
TP213TESTPOINT_0650_RND_0350H
VGPIO
C23
7
12pF
DNI
CN2031
VGPIO
R287
1005%
DNI
C20
3
12pF
DNI
C20
2
12pF
DNI
C20
1
12pF
VCC_1V8
1.5K
R214 LED GREEN
D200
DNI
C20
6
12pF
DNI
C20
5
12pF
DNI
C20
4
12pF
100n
F
C28
8
R200 0
DNIR210 0R211 0 DNIR212 0 DNI
10K
R28
6
1%
R201 0
R202 0
R203 0
DNIR260 0
DNI
C20
8
12pF
DNI C20
7
12pF
J200
G20G19
G10G9G8G7G6G5G4G3G2G1
G18G17G16G15G14G13G12G11
234233232231230229228227226225224223222221220219218217216215214213212211
202201200199198197196195194193192191190189188187186185184183182181180179178177176175174173172171
210209208207206205204203
171
172
173
174
175
176
177
178
198
199
200
201
202
203
204
179
197
218
219
220
221
222
205
180
196
217
230
231
232
223
206
181
195
216
229
234
233
224
207
182
194
215
228
227
226
225
208
183
193
214
213
212
211
210
209
184
192
191
190
189
188
187
186
185
GND SLUGS
TP215
TP216
TP217
TP218
R236 0
DNI
R24
3
2.2K 1%
R237 0
TP219
TP220 TP222
TP221
J200
244243
235
242241240239238237236 RESET
TCKTDOTMSTRSTTDIRTCK
GND_SNS
PS_HOLDMDM_PWR_SW_ON
JTAG
21
70
67 68
6261
37394051 50 48 47
69
1
66656463
605958575655545352
49 46 45 44 43 42 3841 36 35 34
333231302928272625242322
2019
1498765432 11 12 13 1615 17 1810G
PIO
2
SP
KR
_PS
PK
R_N
HS
IC_S
TR
BU
SB
_VB
US
US
B_D
PU
SB
_DN
RE
SE
T_I
N_N
UA
RT
1_R
IU
AR
T1_
RT
SU
AR
T1_
CT
SU
AR
T1_
TX
UA
RT
1_R
XU
AR
T1_
DT
RU
AR
T1_
DC
DU
AR
T1_
DS
R
HS
IC_D
AT
A
MIC_PMIC_N
SYSTEM_CLKSLEEP_CLK
ADC1ADC0
UIM1_VCCUIM1_CLKUIM1_DATUIM1_RST
GND1RF_DIV
GND2PCM_OUTP
CM
_IN
PC
M_S
YN
CP
CM
_CLK
GP
IO8
RF
_GP
S
DR
_SY
NC
EX
T_G
PS
_LN
A_E
NG
PIO
13V
GP
IOG
PIO
6
RF
_MA
IN
SPI1_MISOSPI1_CLKSPI1_MOSIUIM2_VCCUIM2_DATUIM2_RSTUIM2_CLKPWR_ON_NTXON
VBAT_BBUIM1_DETUIM2_DETI2C1_DAT
I2C
1_C
LK
TP
1G
ND
4
GN
D5
SP
I1_M
RD
Y
GP
IO7
GN
D6
GN
D7
BAT_RTC
GND
VBAT_RF
GND
GNDGND
J200
170
167
166165164163162161160159158157156155154153152151150149148147146145
143
142
141
140
139
136
135
134
133
132
131
130
129
128
125
124
123
122
121
120
169
168
118117116115114113
111110109108107106105104103102101100999897
959493929190898887868584838281807978777675747372
144
119
96
71
UART2_TX
US
B_I
DS
PI2
_CLK
SP
I2_M
OS
IS
PI2
_MIS
OS
PI2
_CS
0
UART2_RXUART2_RTSUART2_CTS
GPIO34GPIO35GPIO36GPIO37GPIO32GPIO33
WWAN_LED_NADC2ADC3
GPIO42WAKE_ON_WWAN
GND5
GND6
GN
D9
GN
D10
GN
D11
GN
D12
GPIO21GPIO22GPIO23GPIO24W_DISABLE_NSAFE_PWR_REMOVEANT_CTL_0ANT_CTL_1ANT_CTL_2ANT_CTL_3VBAT_RFVBAT_BBGPIO25RESERVEDSD_CMDSD_CLKSD_D3SD_D2SD_D1SD_D0
RESERVEDRESERVED
RESERVED
NO
PIN
NO
PIN
NO
PIN
NO
PIN
NO PIN
GNDGND
GNDGND
RE
SE
RV
ED
RESERVED
DNI
POST TERMINAL STRIP
CN200
21
GND
UART1_RTSUART1_CTS
RF_DIV
HSIC_DATAHSIC_STRB 50_OHM
USB_D-USB_D+
SPKR_PSPKR_N
PCM_OUT
PCM_OUT
BAT_RTC
PCM_SYNC
UIM2_RST
2G_TX_ON
JTAG_RTCK
UIM1_RESETUIM1_DATAUIM1_CLK
MIC_P
JTAG_RESET
UART1_DTR
PCM_IN
PCM_CLK
MIC_N
GPIO3
TP1_BOOT
TP1_BOOT
SD_CMDSD_CLK
SD_D1SD_D2
SD_D0
PSHOLD
32K_CLK
SD_D3
LED
PWR_IND
UART2_TXUART2_RX
UART2_RTS
UART2_CTS
SPI2_MISO
SPI2_CLK
SPI2_MOSI
SYSTEM_CLK
PPS
RF_GPS
W_DISABLE_N
W_DISABLE_N
UIM2_DAT
UIM2_CLK
SPI1_MOSISPI1_CLKSPI1_MISO
SPI1_MRDY
SPI1_MRDY
GPIO1/I2C1_CLK
GPIO5/I2C1_DATA
LowPower_RESET
GPIO_SCF3_RESET
JTAG_TDIJTAG_TRSTJTAG_TMSJTAG_TDOJTAG_TCK
SPI2_MRDY
RF_MAIN
PWR_ON
GPIO4
GPIOEXP_INT2
GPIOEXP_INT1
ADC0
Correct_insertion
ADC2Battery_detect
IOT0_GPIO1
IOT0_GPIO2
IOT0_GPIO3
IOT1_GPIO4
IOT1_GPIO1
IOT1_GPIO1
IOT1_GPIO2
IOT1_GPIO3
IOT2_GPIO4
IOT2_GPIO1
IOT2_GPIO1
IOT2_GPIO2
IOT2_GPIO2
IOT2_GPIO3
IOT2_GPIO3
IOT0_GPIO4
final_GPIO5/I2C1_DATA
final_GPIO5/I2C1_DATA
final_GPIO1/I2C1_CLK
final_GPIO1/I2C1_CLK
USB_ID
RESET_IN
GPIO_Lowpower2GPIO_Lowpower1
WAKE_ON_WWAN
UART1_RI
UART1_DCDUART1_DSR
GPIO31/SWD_DIOGPIO20/SWD_CLK
UART1_TX_HL_WPUART1_RX_HL_WP
MDM_Power_SW_ON
connect_to_AV_CF3
connect_to_AV_CF3
ADC1
ADC3
ANT_CTL_0ANT_CTL_1ANT_CTL_2 connect_to_AV
INNER RING
OUTER RING
GROUND SLUG
Mounting Holes
JTAG
1
Mounting holes can be disconnected from GND
MANGO GREEN
CTO Office
See P1
Ashish Syal
See P1
327-01-2016_10:22
152500905
PROJECT
SCHEMATIC
DATE/TIME
PAGE
SITE
LEAD ENGINEER
REV SCH REV PCB
1 2 3 4 5 6 7 8 9 10 11
A
B
C
D
E
F
G
H
I
J
OF
This document contains information which
is proprietary to Sierra Wireless Inc. and is
licensed pursuant to Creative Commons
Attribution 4.0 International License.
Copyright (C) 2016
CN310
32
1
D31
7
0.05
pF
DNI
D311
4
5
3
6
21 D-
D+
VBUS
ID
NC GND
USB_VBUS
D30
3
0.05
pF
DNI
VBUS_EXT
D326
0H
32
41
D30
9
0.05
pF
DNI
5%30
0R
306
5%10K
R30
9
5%30
0R
308
DN
I
PO
ST
TE
RM
INA
L S
TR
IP
CN
320
21
CN304
UFL_M_RF
32
1
5%30
0R
307
15pF
C303
VBUS_EXT
D330
4
5
3
6
21 D-
D+
VBUS
ID
NC GND
0H
D347
32
41
CN311
10 9 8 7 6
54321VBUS
D-D+ID
GND
CASE GND
R32
5
470
1%
SMA_RF
R303
0
SMA_RF
R305
0
UFL_M_RF
R301
0
UFL_M_RF
R300
0
UFL_M_RF
R304
0 UFL_M_RF
CN306
32
1
10uF
C33
8
CN307
UFL_M_RF
32
1
51K
R318
5%
U301
FPF2164
6
75
1432 VIN VOUT
FLAGB ISET
GND1 GND2
ON
U300
3
4
5
2
61 NC1 VCC
A
NC2
Y
GND
CN309
32
1
CN308
32
1
D31
5
0.05
pF
DNI
D31
6
0.05
pF
DNI
USB_VBUS
D310
VCC_5V0
VGPIO
DNI
51K
R33
9
5%
C34
0
10uF
1.5m
F
C34
7 DNI
1.5m
F
C34
6
TP301
CN327
6 5
4321VBUS
D-D+
GND
CASE GND
USB_VBUS
SMA_RF
R302
0
SMA_RF
CN303
SMA
54321
VCC_1V8
R315
22
DNI
D30
4
0.05
pF
SMA_RF
CN305
SMA
5432
1
SMA_RF
CN302
SMA
5432
1
R321
0
R317
22
C15
85
22pF
5%R38
9
51K
VGPIO
0
R320
DNI
DNI
R322
0
VCC_5V0L300
47nH
CN330
USB CONN 9 8 7 6
54321VBUS
D-D+ID
GND
CASE GND
D334
4
5
3
6
21 D-
D+
VBUS
ID
NC GND
VBUS_PC
VBUS_PC
VCC_3V3
TP300
GND
GND
GND
GND
RF_DIV
USB_D-USB_D+
BAT_RTC
RF_GPS
S_RF_DIV
S_RF_MAIN
RF_MAIN
USB7_D+USB7_D-
S_RF_GPS
USB_CN_D-USB_CN_D+
USB_ID
USB_ID
USB7_CN_D-
USB7_CN_D+
USBD-_ARD
USBD+_ARDUSBD+_ARD_CN
USBD-_ARD_CN
USB CONN
VBACKUP/DISCHARGE
RTC Backup Battery
Replace with FPF2163 if Autorestart is required
Active Antenna Supply
USB OTG SECONDARY CF3 Socket
MAIN CF3 Socket
USB HOST
USB Arduino Programming
Main Antenna
Diversity
GPS
DiversityInput is made high for system stability
SMA - MAIN ANT
Main Antenna
GPS
SMA - DIV ANT
SMA - GPS ANT
MANGO GREEN
CTO Office
See P1
Ashish Syal
See P1
426-01-2016_14:46
152500905
PROJECT
SCHEMATIC
DATE/TIME
PAGE
SITE
LEAD ENGINEER
REV SCH REV PCB
1 2 3 4 5 6 7 8 9 10 11
A
B
C
D
E
F
G
H
I
J
OF
This document contains information which
is proprietary to Sierra Wireless Inc. and is
licensed pursuant to Creative Commons
Attribution 4.0 International License.
Copyright (C) 2016
R41
810
K5%
VCC_1V8
D40
0
0.05
pF
DNI
SW400
4321
VCC_1V8
100n
F
C40
9
VCC_1V8
R43
0
10K
1%
100n
F
C40
5
DNI
CN400
SFMC-105-02-L-D-TR
975312
468
10
U400
3V
534
12 IN RESETNCGND CD
VCC_1V8
SW401
1-1571983-1
54321 16
15
1098
76
14131211
DNI
10K
R42
5
DNI
10K
R42
7
DNI
R40
6
47K
C406
100nF
100nF
C404
VCC_1V8
VCC_1V8
VCC_1V8
DNI
R40
7
47K
DNI
R40
3
47K
47K
R40
8
U1101
253 4
61 VCC_A VCC_BBA
OE GND
U404
4
32
61 A VCC
B
GND
Y
VCC_1V8
DNI
R40
5
47K
VCC_1V8
VCC_1V8
R41
3
47K
VCC_1V8
5%10
KR
417
SFMC-110-02-L-D-TR
975312
468
10
191715131112
14161820
DNI
CN401
VGPIO
100n
F
C40
8
5%10
KR
419
5%10
KR
421
5%10
KR
423
5%10
KR
416
0R450
R42
6
10K
VCC_3V3
U406
4
32
61 A VCC
B
GND
Y
0R
422
C402
100nF
R11
04
47K
R409
3301%
R410
3301%
R411
3301%
R414
3301%
00% DNI
R402
VCC_1V8
U405
4
32
61 A VCC
B
GND
Y
U403
4
32
61 A VCC
B
GND
Y
47K
R40
4
VCC_1V8
VCC_1V8
VCC_1V8
VCC_1V8
VCC_1V8
U401
4
32
61 A VCC
B
GND
Y
47K
R41
2
5%10
KR
420
R42
40
C40
0
100n
F
VCC_3V7
R400
0
VCC_1V8
0R
415
0R
429
47K
R43
5
47K
R43
7
47K
R43
6
R401
5%100
U402
4
32
61 A VCC
B
GND
Y
C401
100nF
C403
100nF
C407
100nF
JTAG_RTCK
JTAG_RESET
CARD2_DETECT
TP1_BOOT
PSHOLD
W_DISABLE_N
RESET_IOT0
RESET_IOT1
LowPower_RESETSystem_reset
System_reset
System_reset
System_reset
System_reset
System_reset System_reset
GPIO_SCF3_RESET
GPIO_IOT0_RESET
GPIO_IOT2_RESETRESET_IOT2 RESET_SCF3
GPIO_IOT1_RESET
JTAG_TDIJTAG_TRST
JTAG_TMS
JTAG_TDO
JTAG_TCK
PWR_ON
S_PWR_ON
DCDC_shutdown
LDO_PG
WP2Arduino_reset
RESET_IN
RESET_IN
RESET_IN
GPIO31/SWD_DIOGPIO20/SWD_CLK
ATmega_reset_GPIO
System_reset_3V3
MDM_Power_SW_ON
UART_CTRL
JTAG
(SWD_DAT)
uC DEBUG
OPHW Platform RESET
SYSTEM RESET
RESET_IOT1
RESET_IOT0
RESET_IOT2 RESET_Secondary CF3
CONTRL SWITCH
(SWD_CLK)
RESET if LDO output to CF3 is not valid
R403 = ON , R404 = DNI --> System_reset is High during startup and when LowPowerReset = HiZR403 = DNI , R404 = ON --> System_reset is Low during startup and when LowPowerReset = HiZ
0R56010
K
R51
0
0%0
R50
4
MICBIAS
C51
9
4.7u
F0%0
R502
MICBIAS
4.7u
F
C52
5
4.7u
F
C52
0
4.7u
F
C52
7
VC
C_1
V8
VCC_3V3
TP550
100p
F
C50
7
100p
F
C51
0
R501
2.2K1%
4.7u
F
C52
1
47nH
L500
R50
0
1K 1%
R503 20K1%
MIC_OMTP
L513
0H
0H
L501
U500
TS3A44159RSVR
79
35
151
1113
2
8
46
16
12
14
10 V+
IN1_2
COM1
COM2
IN3_4 COM3
COM4
GND
NC1NO1
NC2NO2
NC3NO3
NC4NO4
0H
L504
100pF
C503
C51
222
pF
VCC_3V7
100p
F
C50
8
MIC_CTIA0H
L512
MIC_CTIA0H
L506
VCC_3V7L510 22nH
L509 22nH
L508 22nH
L507 22nH
C51
810
0pF
C51
710
0pF
C51
610
0pF
C51
510
0pF
100p
F
C50
9
CN500
3.5MM AUDIO JACK
612345
100p
F
C50
5
100pF
C502
0H
L505
MIC_CTIA
R50
5
0
0H
L503
MANGO GREEN
CTO Office
See P1
Ashish Syal
See P1
525-01-2016_15:48
152500905
PROJECT
SCHEMATIC
DATE/TIME
PAGE
SITE
LEAD ENGINEER
REV SCH REV PCB
1 2 3 4 5 6 7 8 9 10 11
A
B
C
D
E
F
G
H
I
J
OF
This document contains information which
is proprietary to Sierra Wireless Inc. and is
licensed pursuant to Creative Commons
Attribution 4.0 International License.
Copyright (C) 2016
Q500
NPN
3
4
5
100p
F
C50
6
MIC_CTIA
C51
422
pF
22pF
C51
3
C51
122
pF
100n
F
C50
1
C50
0
22pF
C52
8
2.2u
F
C52
2
100n
F
C523
1uF
MIC_OMTP
L502
0H
C526
1uF
0R561
WM8944BECS/R
U501
E4 A4A3
D4
C2
A5D5
B2B1A2
A1B5E2
E1
D1D3
D2
B4B3
E5
C1C4C3
E3C5 CS/GPIO1 DCVDDSDASCLKCIFMODE
VBINAUXIN1/DMICDAT
LRCLK
DACDATBCLK
MCLK
DBVDDLDOVDDSPKVDD
LINEOUTSPKOUTNSPKOUTP
VBOUTMICBIAS
GND
VBREFR
VMIDCLDOVOUTADCDAT
L511
0H
100n
F
C52
4
MIC_OMTP
R52
0
0
100p
F
C53
0 MIC_OMTP
SPKR_P
SPKR_N
MIC_P
MIC_N
SYSTEM_CLK
GPIO1/I2C1_CLKGPIO5/I2C1_DATA
SPKR_N_SIG
SP
KR
_N_S
IG
SPK-_SIG
SPK-_SIG
SPKP_P_SIG
SPKP_P_SIG
SPK+_SIG
SPK+_SIG
SPK+
SPK+
MIC_N_SIG
MIC_N_SIG
MIC_P_SIG
MIC_P_SIG
MIC-
MIC-
M-
M-
M-
M+
M+
M+
SP+
SP+
SPK-
SPK-
MIC-_SIG
MIC-_SIG
MIC+_SIG
MIC+_SIG
SP-
SP-
PCM_ANALOG_SELECT
PCM_ANALOG
PCM_ANALOG
PCM_SYNC_Codec
PCM_OUT_CODECPCM_CLK_CODECPCM_IN_CODEC
MIC+
MIC+
L = ANALOGH = PCM
Audio Codec
Audio Source SelectionShare footprint
Share footprint
Changed original power config
I2C address 00011010bI2C address 1Ah
VCC_ARD
DNI0R628
VBATT_BB_Secondary
VBATT_RF_Secondary
MANGO GREEN
CTO Office
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See P1
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152500905
PROJECT
SCHEMATIC
DATE/TIME
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SITE
LEAD ENGINEER
REV SCH REV PCB
1 2 3 4 5 6 7 8 9 10 11
A
B
C
D
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OF
This document contains information which
is proprietary to Sierra Wireless Inc. and is
licensed pursuant to Creative Commons
Attribution 4.0 International License.
Copyright (C) 2016
VBATT_BB_Secondary
S_VGPIO
TP611
J601
3900283
D1/TX
connect_to_AV_CF3
VCC_3V7
R61
210
K
VCC_ARD
0R627 DNIDNI0R626
VCC_1V8
DNI
CN600
SFMC-110-02-L-D-TR
97531
6810
1917151311 12
14161820
42
VBATT_RF_Secondary
D0/RX
0DNI
R625
VBATT_BB_Secondary
TP613
S_UIM1_VCC
TP612
TP617
TP609
TP615TP614
TP604TP608
TP603
TP610
TP601
TP600
TP607
TP606TP602
TP616
TP605
U600
9
6
11
4
10
5
3
1
12
7
2
VCC1
GND1
8
GND2
VCC2
VCC_1V8
DNIR610 0
DNI
R611 0
C613
100nF
C611
100nF
100nF
C610 VCC_1V8
DNI
SFMC-110-02-L-D-TR
CN601
97531
810
1917151311 12
14161820
642
DNI
SFMC-110-02-L-D-TR
CN602
97531
6810
1917151311 12
14161820
42
U601
46
532 7
81 VCCA VCCBB1A1
A2EN
B2GND
DNI
J600
244243
235
242241240239238237236 RESET
TCKTDOTMSTRSTTDIRTCK
GND_SNS
PS_HOLDMDM_PWR_SW_ON
JTAG
DNI
J600
G20G19
G10G9G8G7G6G5G4G3G2G1
G18G17G16G15G14G13G12G11
234233232231230229228227226225224223222221220219218217216215214213212211
202201200199198197196195194193192191190189188187186185184183182181180179178177176175174173172171
210209208207206205204203
171
172
173
174
175
176
177
178
198
199
200
201
202
203
204
179
197
218
219
220
221
222
205
180
196
217
230
231
232
223
206
181
195
216
229
234
233
224
207
182
194
215
228
227
226
225
208
183
193
214
213
212
211
210
209
184
192
191
190
189
188
187
186
185
GND SLUGS
DNI
J600
21
70
67 68
6261
37394051 50 48 47
69
1
66656463
605958575655545352
49 46 45 44 43 42 3841 36 35 34
333231302928272625242322
2019
1498765432 11 12 13 1615 17 1810G
PIO
2
SP
KR
_PS
PK
R_N
HS
IC_S
TR
BU
SB
_VB
US
US
B_D
PU
SB
_DN
RE
SE
T_I
N_N
UA
RT
1_R
IU
AR
T1_
RT
SU
AR
T1_
CT
SU
AR
T1_
TX
UA
RT
1_R
XU
AR
T1_
DT
RU
AR
T1_
DC
DU
AR
T1_
DS
R
HS
IC_D
AT
AMIC_PMIC_N
SYSTEM_CLKSLEEP_CLK
ADC1ADC0
UIM1_VCCUIM1_CLKUIM1_DATUIM1_RST
GND1RF_DIV
GND2PCM_OUTP
CM
_IN
PC
M_S
YN
CP
CM
_CLK
GP
IO8
RF
_GP
S
DR
_SY
NC
EX
T_G
PS
_LN
A_E
NG
PIO
13V
GP
IOG
PIO
6
RF
_MA
IN
SPI1_MISOSPI1_CLKSPI1_MOSIUIM2_VCCUIM2_DATUIM2_RSTUIM2_CLKPWR_ON_NTXON
VBAT_BBUIM1_DETUIM2_DETI2C1_DAT
I2C
1_C
LK
TP
1G
ND
4
GN
D5
SP
I1_M
RD
Y
GP
IO7
GN
D6
GN
D7
BAT_RTC
GND
VBAT_RF
GND
GNDGND
DNI
J600
170
167
166165164163162161160159158157156155154153152151150149148147146145
143
142
141
140
139
136
135
134
133
132
131
130
129
128
125
124
123
122
121
120
169
168
118117116115114113
111110109108107106105104103102101100999897
959493929190898887868584838281807978777675747372
144
119
96
71
UART2_TX
US
B_I
DS
PI2
_CLK
SP
I2_M
OS
IS
PI2
_MIS
OS
PI2
_CS
0
UART2_RXUART2_RTSUART2_CTS
GPIO34GPIO35GPIO36GPIO37GPIO32GPIO33
WWAN_LED_NADC2ADC3
GPIO42WAKE_ON_WWAN
GND5
GND6
GN
D9
GN
D10
GN
D11
GN
D12
GPIO21GPIO22GPIO23GPIO24W_DISABLE_NSAFE_PWR_REMOVEANT_CTL_0ANT_CTL_1ANT_CTL_2ANT_CTL_3VBAT_RFVBAT_BBGPIO25RESERVEDSD_CMDSD_CLKSD_D3SD_D2SD_D1SD_D0
RESERVEDRESERVED
RESERVED
NO
PIN
NO
PIN
NO
PIN
NO
PIN
NO PIN
GNDGND
GNDGND
RE
SE
RV
ED
RESERVED
TP618
GND
GND
UART1_RTSUART1_CTS
UART1_RX
UART1_RX
PCM_OUTPCM_SYNC
2G_TX_ON
UART1_DTR
PCM_INPCM_CLK
GPIO3
UART1_TX
UART1_TX
SD_CMDSD_CLK
SD_D1SD_D2
SD_D0
32K_CLK
SD_D3
PWR_IND
UART2_TXUART2_RX
UART2_RTSUART2_CTS
SPI2_MISOSPI2_CLKSPI2_MOSI
SYSTEM_CLK
PPS
W_DISABLE_N
S_RF_DIV
S_RF_MAIN
GPIO1/I2C1_CLKGPIO5/I2C1_DATA
S_I2C1_DAT
S_I2C1_CLK
S_GPIO2
S_GPIO6
LowPower_RESET
GPIO_IOT2_RESET
RESET_SCF3
GPIO_IOT1_RESET
SPI2_MRDY
PWR_ON
S_2G_TX_ON
S_PPSS_EXT_LNA_GPS_EN
S_PCM_CLKS_PCM_SYNCS_PCM_IN
S_PCM_OUT
S_UART1_DSRS_UART1_DCDS_UART1_DTRS_UART1_RXS_UART1_TXS_UART1_CTSS_UART1_RTSS_UART1_RI
GPIO4
S_GPIO3
S_UIM1_CLKS_UIM1_DATAS_UIM1_RESET
VCC_1V8
USB2_D+USB2_D-
GPIOEXP_INT2
S_PWR_ON
S_Correct_insertion
D1/TXD0/RX
S_RF_GPS
IOT0_GPIO1IOT0_GPIO2IOT0_GPIO3
IOT1_GPIO4
IOT1_GPIO1IOT1_GPIO2
IOT1_GPIO3
IOT2_GPIO4
IOT2_GPIO1
IOT2_GPIO2IOT2_GPIO3
IOT0_GPIO4
RESET_IN
GPIO_Lowpower2
GPIO_Lowpower1
WAKE_ON_WWAN
UART1_RI
UART1_DCDUART1_DSR
UART1_TX_HL_WP
UART1_RX_HL_WP
UART1_RX_Arduino
UART1_RX_Arduino
UART1_TX_Arduino
UART1_TX_Arduino
ANT_CTL_0
ANT_CTL_1
ANT_CTL_2
UART_CTRL
Additional Hardware PinsJ601 is CF3 socket essential that ovelap J600
Secondary LGA SOCKET
HL to ATmega through UART.
default to WP
C70
1
100n
F
MANGO GREEN
CTO Office
See P1
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See P1
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152500905
PROJECT
SCHEMATIC
DATE/TIME
PAGE
SITE
LEAD ENGINEER
REV SCH REV PCB
1 2 3 4 5 6 7 8 9 10 11
A
B
C
D
E
F
G
H
I
J
OF
This document contains information which
is proprietary to Sierra Wireless Inc. and is
licensed pursuant to Creative Commons
Attribution 4.0 International License.
Copyright (C) 2016
C70
0
10nF
300
R780
C715
1uF
VCC_1V8
47K
R72
5
VCC_1V8
CN700
DSUB
1110
9
8
5
4
3
27
61
GND
U700
RS-232
18
1015
817
2014
916
1213
165
73
411
19 2C1+VCC
VLC1-
V+V-
C2+C2-
READY
T1INT2IN
R1INR2IN
FORCEONFORCEOFF
T1OUTT2OUT
R1OUTR2OUT
GND
RS
232
TT
L
R718
1.5K
R719
1.5K
D703
LED GREEN
D702
LED GREEN
D705
LED GREEN
C70
4
100n
F
D704
LED GREEN
U702
SN74LVC8T245
13
23
1211 2
14151617181920
2210
321
241 VCCA VCCB1
B1A1A24
A35
A46
A57
A68
A79
A8OE
B2B3B4B5B6B7B8
DIRGND1GND2
VCCB2
GND3
D707
LED GREEN
D706
LED GREEN
C71
0
100n
F
C71
2
100n
F
10K
R702
VCC_3V7
R715
1.5K
VCC_1V8
100n
F
C74
2
D760
VCC_1V8
U704
LSM6DS3
10
11
32
11413
76
12
94
58
VDDVDD_IO
INT1INT2
CS
GND_1GND_2
SCLSDA
SDO/SA0
SDxSCx
NC
OCS
C71
7
100n
F
C71
6
100n
F
R723 10KVCC_1V8
R724 10K
VCC_1V8
100n
F
C74
3
1uFC7141uFC784
1uFC785
VCC_3V7
10nF
C70
5100n
F
C70
3
R76
0
2.2K
R76
1
2.2K
R76
2
2.2K
R76
3
2.2K
R76
5
2.2K
R76
4
2.2K
R76
7
2.2K
R76
6
2.2K
R76
8
2.2K
R76
9
2.2K
R77
0
2.2K
R77
1
2.2K
R77
3
2.2K
R77
2
2.2K
R77
5
2.2K
R77
4
2.2K
VCC_1V8
VCC_1V8
R714
1.5K
R72
7
47K
VCC_1V8
R716
1.5K
R717
1.5K
U701
TCA9548ARGER
1617
1415
1213
1011
78
56
34
12
259
2019
182322
24
21VCC
RESET_n
A0A1A2
SCLSDA
GNDEP
SC0SD0
SC1SD1
SC2SD2
SC3SD3
SC4SD4
SC5SD5
SC6SD6
SC7SD7
GND
RS232_TXD
RS232_RXD
2G_TX_ON
RS232_CTS
W_DISABLE_N GPIO1/I2C1_CLK
GPIO1/I2C1_CLK
GPIO5/I2C1_DATA
GPIO5/I2C1_DATA
UART2_TX_dbg
UART2_RX_dbgUART2_CTS_dbg
UART2_RTS_dbg
System_reset
S_2G_TX_ON
RS232_Enable
SENSOR_INT2SENSOR_INT1
LED_ON
IOT0_SCLIOT0_SDA
IOT1_SDAIOT1_SCL
IOT2_SDAIOT2_SCL
Expanion1_I2C_CLK
Expansion2_I2C_CLKExpansion2_I2C_DATA
Hub_I2C_CLKHub_I2C_DATA
charger_I2C_DATAcharger_I2C_CLK
Expansion3_I2C_CLKExpansion3_I2C_DATA
Expansion1_I2C_DATA
RS232_RTS
connect_to_AV_LEDLED_CARD_DETECT_IOT0LED_CARD_DETECT_IOT1LED_CARD_DETECT_IOT2
UART (MAX 1MBPS)
LEDs
I2C Address = 1110001b
Serial Port DB9 Female
Pin 2 = RXD_DTE = Mango OUTPin 3 = TXD_DTE = Mango IN
Pin 8 = CTS_DTE = Mango OUTPin 7 = RTS_DTE = Mango IN
Port is in DCE configuration
default ON
I2C Address = 1101010b
ACCELEROMETER AND GYROSCOPE
I2C Address = 6Ah
DNIR835 0
DNI
5%10K
R82
0
R82
3
100K
1%
VCC_3V7
VCC_2V95
CN801
10
C3C2C1
9
C7C6C5 GND
VPPI/O
SW_A
VCCRSTCLK
SW_B
VCC_2V95
DNI
C80
2
4.7u
F
VCC_3V3
1%1K
R80
3
C81
1
100n
F
CARD2_VCC
Second_CARD2_VCC
U880
1173
15
1395
128416
1
6102
14VCC
SELNC
GND
VSIM1
VSIMRSTCLKDAT
RST1CLK1DAT1
VSIM2RST2CLK2DAT2
VCC_3V7
S_UIM1_VCC
0R814
DNI
MANGO GREEN
CTO Office
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See P1
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PROJECT
SCHEMATIC
DATE/TIME
PAGE
SITE
LEAD ENGINEER
REV SCH REV PCB
1 2 3 4 5 6 7 8 9 10 11
A
B
C
D
E
F
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H
I
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This document contains information which
is proprietary to Sierra Wireless Inc. and is
licensed pursuant to Creative Commons
Attribution 4.0 International License.
Copyright (C) 2016
DNIR813 0
C80
8
1uF
C80
6
1uF
2.95VU830
52
3
14 VIN VOUT
CEGND
SLUG
VCC_2V95
DNI
R816 0
Second_CARD2_VCC
DNI
R81
2
100K
1%
C80
1
100n
F
UIM2_VCC
UIM1_VCC
CARD1_VCC
CN802
G8
G7
G6
G5
G4
G3
G2
G1GND
GND_2
GND_3
GND_4
GND_5
GND_6
GND_7
GND_8
VCC_3V7
DNI
C81
0
4.7u
F
U802
117315
1395
1284
16
1
6102
14 VCC
SELNCGND
VSIM1
VSIMRSTCLKDAT
RST1CLK1DAT1
VSIM2RST2CLK2DAT2
C80
0
100n
F
R801 0
R810 0
R811 0
R818 0
R821 0
R822 0
R80
2
10K
5%
VCC_3V7
0R834
DNI
DNI
U801
eSIM MODULE
7
5913
4
62
8 VCC
NC1CLK
NC2DATAGNDSLUG NC3
RESET
GND
R81
7
15K
DNI
CARD2_VCC
VCC_1V8
VCC_1V8
R804
335%
DNI
C80
4
1nF
DNI
C81
2
1nF
5%10K
R837
D1202
1.6pF
765
4
3
8
21IO1
IO2
VBUS
IO3
GND
IO4IO5IO6
VCC_2V95
DNI
R80
0
15K
5%
DNI
1%1K
R81
9
VCC_3V7
GND
CN802
T2
T1
T8
T7
T6
S/W
T3
T5
T4VDD
CLK
CMD
CARD_DETECT
VSS
DAT0
DAT1
DAT2
CD/DAT3
CN802
S8
S7
S3
S2
S5
S4
S6
S1VCC
VPP
RESERVED
GND
RST
CLK
I/O
RESERVED_2
100n
FC
809
C807
22pF
47K
R80
6
47K
R80
7
47K
R80
8
47K
R80
9
C80
3
100n
F
47K
R80
5
U803
1173
15
1395
128416
1
6102
14VCC
SELNC
GND
VSIM1
VSIMRSTCLKDAT
RST1CLK1DAT1
VSIM2RST2CLK2DAT2
100n
F
C80
5
VCC_3V7
CARD1_VCC
CARD2_VCC
R836 0
D80
0
0.5p
F
64
5
31 D80
1
0.5p
F
64
5
31
5%10K
R83
3
UIM2_PWM_SELECT
UIM2_M2_S_SELECT
DNI
R81
5
10K
5%
CARD2_CLK
CARD2_CLK
CARD2_CLK
UIM2_RST
UIM1_RESET
UIM1_DATAUIM1_CLK
GPIO3
CARD2_DETECT
CARD2_DETECT
CARD2_RST
CARD2_RSTCARD2_RST
CARD2_DATA
CARD2_DATA
CARD2_DATA
CARD2_DATA
CARD1_CLK
CARD1_CLK
CARD1_RESET
CARD1_RESET
CARD1_DATA
CARD1_DATA
CARD1_DATA
UIM2_DATUIM2_CLK
SD_CLK_CARD
SD_D0_CARDSD_D1_CARDSD_D2_CARD
SD_CMD_CARD
Second_CARD2_RST
Second_CARD2_RST
Second_CARD2_CLK
Second_CARD2_CLK
Second_CARD2_DATA
Second_CARD2_DATA
GPIO4
S_GPIO3
S_UIM1_CLKS_UIM1_DATA
S_UIM1_RESET
UIM2_PWM_SELECT
SD_D3_CARD
IOT0_GPIO1
UIM2_M2_S_SELECT
UIM1_DETECT
UIM2
SD CONNECTOR
R834 IN FOR HL8 FAST SIM
UIM2_DETECT
SIM SELECT
UIM1
SWITCHING, OTHERWISE LEAVE OPEN
ESIM
SIM SELECT
SD detect
100nF
C903
R96
5
47K
DNI
47K
R96
6
VCC_1V8
DNI
R96
7
47K
100nF
C904
100nF
C907
100nF
C908
100nF
C900
100nF
C901
100nF
C905
R96
8
47K
100nF
C910
0R
912
R91
30
DN
I
R96
2
10K
5%
VCC_1V8
VCC_1V8
R94
7
47K
DNI
R94
8
47K
VCC_1V8
POST TERMINAL STRIP
CN902
21
5%10K
R96
1VCC_2V95
NPN
Q9603
2
1
R94
9
47K
TP905
VCC_2V95
POST TERMINAL STRIP
CN900
21
VC
C_1
V8
U910
TS3A5018RSVR
6
2116
15
13
14V+
EN!
IN
NC1NO1COM1
NC23
GND
NO2 4
COM25
NC39
NO38
COM37
NC412
NO411
COM410
C922
100nF
TP906
R989 0
U903
SX1509IULTRTR
29
9
222120191615141318
876521
28274
317
2610
2425
23
11
12VDDM
OSCIO
NRESET
SCLSDA
ADDR1ADDR0
GNDGND_2
VCC1I/O_0I/O_1I/O_2I/O_3I/O_4I/O_5I/O_6I/O_7
VCC2I/O_8I/O_9
I/O_10I/O_11I/O_12I/O_13I/O_14I/O_15
NINT
SLUG
U906
SX1509IULTRTR
29
9
222120191615141318
28274
317
2610
2425
23
11
12VDDM
OSCIO
NRESET
SCLSDA
ADDR1ADDR0
GNDGND_2
VCC1I/O_0I/O_1I/O_2
1
I/O_32
I/O_45
I/O_56
I/O_67
I/O_78
VCC2I/O_8I/O_9
I/O_10I/O_11I/O_12I/O_13I/O_14I/O_15
NINT
SLUG
VCC_1V8
VCC_1V8
VCC_1V8VCC_1V8
R90
1
10K
DNI
R95
0
47K
47K
R95
1VCC_1V8
47K
R95
2
1%10K
R903
VCC_1V8
VCC_1V8
1%10K
R906VCC_1V8
U900
TS3A5018RSVR
101112
789
54
6
3
2116
15
13
14V+
EN!
IN
NC1NO1COM1
NC2
GND
NO2COM2
NC3NO3
COM3
NC4NO4
COM4
U901
TS3A5018RSVR
101112
789
54
6
3
2116
15
13
14V+
EN!
IN
NC1NO1COM1
NC2
GND
NO2COM2
NC3NO3
COM3
NC4NO4
COM4
VC
C_1
V8
VC
C_1
V8
System_reset
DNI
47K
R95
3
U904
TS3A5018RSVR
101112
789
54
6
3
2116
15
13
14V+
EN!
IN
NC1NO1COM1
NC2
GND
NO2COM2
NC3NO3
COM3
NC4NO4
COM4
VC
C_1
V8
VCC_1V8 VCC_1V8
U907
TXS02612ZQSR
C3
E5A5
E4A4
E3A3
E2B3
D4C5
D5B5
D3
A2D2C1
B1A1E1D1
C4B4C2
VCCAVCCB0VCCB1
DAT0ADAT1ADAT2ADAT3A
CMDACLKASEL
GND
DAT0B0DAT0B1
DAT1B0DAT1B1
DAT2B0DAT2B1
DAT3B0DAT3B1
CMDB0CMDB1
CLKB0CLKB1
GND_2SD_CLK_CARD
SD_CMD_CARD
SD_D3_CARD
SD_D2_CARD
SD_D1_CARD
SD_D0_CARD
SD_CLK_WIFI
SD_CMD_WIFI
SD_D3_WIFI
SD_D2_WIFI
SD_D1_WIFI
SD_D0_WIFI
VCC_1V8
1%10K
R907
47K
R75
0
47K
R74
9
VCC_1V8
VCC_1V8 VCC_1V8
R75
1
47K
VCC_1V8
TP901TP902TP903
TP904
TP900
VCC_1V8
VCC_1V8
VCC_1V8
SX1509IULTRTR
U909
29
9
222120191615141318
876521
2827
4
317
2610
2425
23
11
12VDDM
OSCIO
NRESET
SCLSDA
ADDR1ADDR0
GNDGND_2
VCC1I/O_0I/O_1I/O_2I/O_3I/O_4I/O_5I/O_6I/O_7
VCC2I/O_8I/O_9
I/O_10I/O_11I/O_12I/O_13I/O_14I/O_15
NINT
SLUG
C912
100nF
C911
100nF
VCC_1V8
47K
R94
6
VCC_1V8
47K
R94
5
VCC_1V8
VCC_3V3
R90
0
10K
MANGO GREEN
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1 2 3 4 5 6 7 8 9 10 11
A
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This document contains information which
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licensed pursuant to Creative Commons
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Copyright (C) 2016
UART1_RTS
UART1_CTS
UART1_RX
PCM_OUT
PCM_SYNC
PCM_IN
PCM_CLK
UART1_TX
SD_CMDSD_CLK
SD_D1SD_D2
SD_D0
SD_D3
UART2_TX
UART2_RX
UART2_RTS
UART2_CTS
SPI1_MOSI
SPI1_CLK
SPI1_MISO
SPI1_MRDY
SPI_EXP1_IN
SPI_EXP1_IN
UART2_TX_IOT2UART2_TX_dbg
UART2_RX_IOT2UART2_RX_dbg
UART2_CTS_IOT2UART2_CTS_dbg
UART2_RTS_IOT2UART2_RTS_dbg
SPI1_MOSI_IOT1
SPI1_MISO_IOT1SPI1_MISO_IOT0
SPI1_CLK_IOT1SPI1_CLK_IOT0
SPI1_MOSI_IOT0
SPI1_MRDY_IOT1SPI1_MRDY_IOT0
SD_D0_WIFI
SD_D1_WIFI
SD_D2_WIFI
SD_D3_WIFI
SD_CMD_WIFI
SD_CLK_CARD
SD_D0_CARD
SD_D1_CARD
SD_D2_CARD
SD_CMD_CARD
SD_CLK_WIFI
System_resetSystem_resetSystem_reset GPIO_SCF3_RESET
GPIO_IOT0_RESET
GPIO_IOT2_RESETGPIO_IOT1_RESET
PCM_ANALOG_SELECT
GPIOEXP_INT2
GPIOEXP_INT3
GPIOEXP_INT3
GPIOEXP_INT1
GPIOEXP_INT1
RS232_Enable
SENSOR_INT2
UIM2_PWM_SELECT
BattChrgr_PG_NBattGauge_GPIO
SD_D3_CARD
BattChrgr_INT_N
HUB_CONNECTUSB_HUB_INTn
ARDUINO_RESET_Level shift
Battery_detect
CARD_DETECT_IOT0
CARD_DETECT_IOT0
CARD_DETECT_IOT1
CARD_DETECT_IOT1
CARD_DETECT_IOT2
CARD_DETECT_IOT2
UART_EXP1_ENn
UART_EXP1_ENn
UART_EXP1_IN
UART_EXP1_IN
UART_EXP2_IN
UART_EXP2_IN
SDIO_SEL
SDIO_SELSPI_EXP1_ENn
SPI_EXP1_ENn
SENSOR_INT1
LED_ON
Expanion1_I2C_CLKExpansion2_I2C_CLKExpansion2_I2C_DATA Expansion3_I2C_CLK
Expansion3_I2C_DATA
Expansion1_I2C_DATA
SDIO_SEL_LVLSDIO_SEL_LVL
Board_rev_res2
Board_rev_res2
Board_rev_res1
Board_rev_res1
UART1_TX_IOT0UART1_TX_IOT1
UART1_RX_IOT0UART1_RX_IOT1
UART1_CTS_IOT0
UART1_RTS_IOT0UART1_RTS_IOT1
UART1_CTS_IOT1
UART_EXP2_ENn
UART_EXP2_ENn
PCM_EXP1_ENn
PCM_EXP1_ENn
PCM_EXP1_SEL
PCM_EXP1_SEL
PCM_SYNC_Codec
PCM_OUT_CODEC
PCM_CLK_CODEC
PCM_IN_IOTPCM_IN_CODEC
PCM_CLK_IOT
PCM_OUT_IOT
PCM_SYNC_IOT
ATmega_reset_GPIO
ARD_FTDI
connect_to_AV_LEDLED_CARD_DETECT_IOT0LED_CARD_DETECT_IOT1LED_CARD_DETECT_IOT2
UIM2_M2_S_SELECTconnect_to_AV
I2C Address = 1110000bI2C Address = 70h
PCM Expansion #1
SPI Expansion
SDIO Expansion
GPIO Expander#2
UART Expansion #1
Default config = PCM to internal Codec
UART Expansion
UART Expansion #2
I2C Address = 0111110bI2C Address = 0111111b
GPIO Expander#1 GPIO Expander#3
SD voltage select to IoT0
I2C Address = 3EhI2C Address = 3Fh
VCC_1V8
C10
20
4.7u
F
C10
30
4.7u
F
C10
23
10uF
C10
22
10uF
VBUS_IOT0
VCC_3V3VCC_1V8
VCC_1V8
C10
33
10uF
VBUS_IOT1
VCC_1V8
VCC_1V8
VCC_3V3
C10
32
10uF
C10
42
10uF
VCC_3V3
VBUS_IOT2
C10
43
10uF
VCC_1V8C
1040
4.7u
F
C10
35
47uF
C10
36
47uF
C10
37
47uF
CN1001
2110819-1
20212223242526272829303132
3435363738
19181716151413121110987654321
PIN_1PIN_2PIN_3PIN_4PIN_5PIN_6PIN_7PIN_8PIN_9PIN_10PIN_11PIN_12PIN_13PIN_14PIN_15PIN_16PIN_17PIN_18PIN_19
PIN_38PIN_37PIN_36PIN_35PIN_34PIN_33
33
PIN_32PIN_31PIN_30PIN_29PIN_28PIN_27PIN_26PIN_25PIN_24PIN_23PIN_22PIN_21PIN_20
CN1000
2110819-1
20212223242526272829303132333435363738
19181716151413121110987654321
PIN_1PIN_2PIN_3PIN_4PIN_5PIN_6PIN_7PIN_8PIN_9PIN_10PIN_11PIN_12PIN_13PIN_14PIN_15PIN_16PIN_17PIN_18PIN_19
PIN_38PIN_37PIN_36PIN_35PIN_34PIN_33PIN_32PIN_31PIN_30PIN_29PIN_28PIN_27PIN_26PIN_25PIN_24PIN_23PIN_22PIN_21PIN_20
CN1002
2110819-1
20212223242526272829303132333435363738
19181716151413121110987654321
PIN_1PIN_2PIN_3PIN_4PIN_5PIN_6PIN_7PIN_8PIN_9PIN_10PIN_11PIN_12PIN_13PIN_14PIN_15PIN_16PIN_17PIN_18PIN_19
PIN_38PIN_37PIN_36PIN_35PIN_34PIN_33PIN_32PIN_31PIN_30PIN_29PIN_28PIN_27PIN_26PIN_25PIN_24PIN_23PIN_22PIN_21PIN_20
0R1001
0R1002
0R1003
VBUS_IOT0
VCC_3V3
VBUS_IOT1
VCC_3V3
VBUS_IOT2
VCC_3V3
RT
1000
220K
5%TR
1056
62K
1%
VGPIO
DNI
J1000
DNI
J1001
DNI
J1003
DNI
J1002
DNI
J1005
DNI
J1004
MANGO GREEN
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Copyright (C) 2016
GND
SPI2_MISOSPI2_CLK
SPI2_MOSI
PPS
PPS
PPS
USB6_D+USB6_D-
USB5_D+USB5_D-
USB4_D+USB4_D-
UART2_TX_IOT2UART2_RX_IOT2UART2_CTS_IOT2UART2_RTS_IOT2
SPI1_MOSI_IOT1SPI1_MISO_IOT1
SPI1_MISO_IOT0
SPI1_CLK_IOT1
SPI1_CLK_IOT0
SPI1_MOSI_IOT0
SPI1_MRDY_IOT1
SPI1_MRDY_IOT0
SD_D0_WIFISD_D1_WIFISD_D2_WIFISD_D3_WIFISD_CMD_WIFI
RESET_IOT0
RESET_IOT1
SD_CLK_WIFI
RESET_IOT2
SPI2_MRDY
ADC0
ADC2
CARD_DETECT_IOT0
CARD_DETECT_IOT1
CARD_DETECT_IOT2
IOT0_GPIO1IOT0_GPIO2IOT0_GPIO3
IOT1_GPIO4
IOT1_GPIO1IOT1_GPIO2IOT1_GPIO3
IOT2_GPIO4
IOT2_GPIO1IOT2_GPIO2IOT2_GPIO3
IOT0_GPIO4
IOT0_SCLIOT0_SDA
IOT1_SDAIOT1_SCL
IOT2_SDAIOT2_SCL
UART1_TX_IOT0
UART1_TX_IOT1
UART1_RX_IOT0
UART1_RX_IOT1
UART1_CTS_IOT0UART1_RTS_IOT0
UART1_RTS_IOT1UART1_CTS_IOT1
PCM_IN_IOT
PCM_CLK_IOT
PCM_OUT_IOTPCM_SYNC_IOT
ADC1
ADC3
IOT#0
IOT#1
IOT#2
IOT#0
IOT#1
IOT#2
On Board Thermistor
U1103
LAN9514
45
44
4342373635222120
5655
5352
232425
67
5859
65
645754514910
5
3231302928
60
61
12
47403413
41
50
26
18
17
16
14
63
11
6248
3815
4639332719
VDD33IOVDD33IO_2VDD33IO_3VDD33IO_4VDD33IO_5
VDD18COREVDD18CORE_2
VDD18ETHPLLVDD18USBPLL
VBUS_DET
USBRBIAS
PRTCTL2
PRTCLT3
PRTCLTL4
PRTCTL5
EEDI
EXRES
AUTOMDIX_EN
TEST1TEST2TEST3TEST4
nRESET
XI
XO
nTRSTTMSTDITDOTCK
VDD33AVDD33A_2VDD33A_3VDD33A_4VDD33A_5VDD33A_6VDD33A_7
VSS_FLAG
USBDP0USBDM0
USBDP22
USBDM21
USBDP34
USBDM33
USBDP4USBDM4
USBDP59
USBDM58
EEDOEECS
EECLK
RXPRXN
TXPTXN
nFDX_LED/GPPIO0nLNKA_LED/GPIO1
nSPD_LED/GPIO2GPIO3GPIO4GPIO5GPIO6GPIO7
CLK24_EN
CLK24_OUT
Power
Upstream
Downstream
EEPROM
Ethernet
GPIO + Misc
Clocks
JTAG
C11
10
22pF
VCC_3V3
VCC_1V8CORE
VCC_1V8ETHPLL
VCC_1V8USBPLL
VCC_3V3
U1100
IC2026
6
5
8
7
4
3
2
1ENA
FLGA
FLGB
ENB
IN
OUTA
OUTB
GND
R1115
10K1%
CN1100
1413
1112
109
8
7
653
241
TD+TD_CTTD-
RD+RD_CTRD-
NC
GND_1
LED1_ALED1_C
LED2_ALED2_C
GND_2GND_3
ETH_GND
0H
L1100
R1130
12K 1%
R110912K 1%
VCC_5V0
C1106
1uF
R1106825
1%
VBUS_IOT1VBUS_IOT0VBUS_EXTVBUS_IOT2
C1124
1uF
VCC_5V0
PRTCTL5
PRTCTL4
U1104
IC2026
6
5
8
7
4
3
2
1ENA
FLGA
FLGB
ENB
IN
OUTA
OUTB
GND
DNI
1%10K
R11
21
R1100620
R1102620
OSC1100
26MEGHz
42
31 OE OUT
GN
DV
CC
VD
D_3
V3B
YP
1%10K
R11
22
DNI
1%10K
R11
18
DNI
1%10K
R11
17
R1101620
C11
08
100n
F
VCC_3V3
2Kbit SERIAL EEPROM
U11026
2
1
3 DI
DO
GNDCLK4
VCC
CS5
DNI
100n
F
C11
37
R1129 330
R1107
12.4K1%
1%10K
R1110
1%10K
R11
08
VCC_3V3
VCC_3V3
Y1100
25MEGHz42
1 3
VCC_3V3
VCC_3V3AA
C11
03
4.7u
F
100n
F
C11
09
R1105
1MEG1%
C11
11
100n
F
C11
13
100n
F
C11
15
100n
F
C11
04
100n
F
C11
18
100n
F
C11
20
100n
F
C11
00
100n
F
C11
01
100n
F
U1105
USB3503A
C3
D3
A2
A4
D1C1
D2C2
B1A1
E1E2
B4C4
D4E4
C5
B5
A5
E3
D5E5
B3
B2
A3
VD
D_C
OR
E_R
EG
VB
ATREFCLK
SCLSDA
RESET_N
VDD33_BYP_2
HUB_CONNECT
INT_N
REF_SEL0REF_SEL1
PORT_PWROCS_N
DATASTROBE
USBDN1_DPUSBDN1_DM
USBDN2_DPUSBDN2_DM
USBDN3_DPUSBDN3_DM
RBIAS
VDD33_BYP
VDD12_BYP
VSS
100n
F
C11
22
4.7u
F
C11
19
0H
L1101
VCC_3V3VCC_3V3AA
VCC_1V8USBPLL VCC_1V8ETHPLLVCC_1V8CORE
VCC_3V3
C11
31
4.7u
F
VCC_1V8
C11
29
4.7u
F
4.7u
F
C11
34 C11
36
4.7u
F
1%10K
R11
19
VCC_1V8
1%10K
R11
14
1%10K
R11
16
100n
F
C11
32
VC
C_3
V3
100n
F
C11
05
DNI
C11
26
15pF
C11
28
15pF
DNI
TP1100
TESTPOINT_5P_0100_RND_0127CC
54321
VCC_3V3
R11
25
49.9
1%
R11
26
49.9
1%
R11
27
49.9
1%
C11
33
22nF
VCC_3V3AA
C11
30
15pF
DNI
C11
25
15pF
DNI
R1128 330
DNI
R1133
20m5%
MANGO GREEN
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REV SCH REV PCB
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A
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This document contains information which
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Copyright (C) 2016
4.7u
F
C11
21
1%10K
R11
20
100n
F
C11
27
100n
F
C11
35
C11
17
22pF
1%10K
R11
11
1%10K
R11
12
1%10K
R11
13
R11
24
49.9
1%
C11
02
100n
F
C11
12
100n
F
C11
07
100n
F
C11
14
100n
F
C11
16
100n
F
4.7u
F
C11
23
1%10K
R1103
C11
39
10uF
C11
41
100n
F
C11
60
100n
F
100n
F
C11
42
R11
31
10 1%
L1112
0H
C11
40
10uF
GND
HSIC_DATAHSIC_STRB
PRTCTL2
PRTCTL2
nLNKA_LED_GPIO1
nLNKA_LED_GPIO1
nSPDA_LED_GPIO2
nSPDA_LED_GPIO2
USB6_D+USB6_D-
USB5_D+USB5_D-
USB4_D+USB4_D-
TXP
TXP
TXN
TXN
RXP
RXP
RXN
RXN
System_reset
PRTCTL3
PRTCTL3
PRTCTL4
PRTCTL4
PRTCTL5
PRTCTL5
USB2_D+USB2_D-
USB7_D+USB7_D-
EEDO
EEDO
EECLK
EECLK
USB3_D+
USB3_D+USB3_D-
USB3_D-
EECS
EECS
EEDI
EEDI
USB1_D+USB1_D-
HUB_CONNECT
USB_HUB_INTn
VCC_3V3
Hub_I2C_CLKHub_I2C_DATA
System_reset_3V3
USB 3503
LAN9514
Power Filter
USB Downstream Power
I2C address: 00001000b
ETHERNET JACK
Place 49.9R near LAN9514Place 10R near transformer
TP for IN Circuit Programming
This could be a zero ohm, a cap or and inductor
I2C address: 08h
REGN_BATT
CN1200
FC681465P
3
2
1
C12
07
22uF
D1210R1285
300
0%0
R1223
C12
08
10uF
V_BATT
PW
R_G
ND
_BQ
PWR_GND_BQ
47K
R12
12
VCC_3V7
1uF
C12
14
R1229
1MEG1%
DNI
USB_VBUS
DNI
0R1228
CN1202
B2B-PH-K-S
21
CN1203
POST TERMINAL STRIP
21
CN1204
POST TERMINAL STRIP
321
V_SYS_BATT
DNIR12
07
10K
1%
1%10K
R12
17
5%100K
R12
16
PW
R_G
ND
_BQ
V_SYS_BATT
R12
15
15K
1%
V_SYS_BATT
V_SYS_BATT
D12
01
C12
09
47uF
V_BATT
R12
21
10K
1%
PWR_GND_BQ
100n
F
C12
06
PWR_GND_BQ
V_IN
3.3uH
L1201
L1200
0H
R12
18
150
1%
300
R12
11
VCC_3V7
REGN_BATTC1204
47nF
R12
06
10K
1%V_SYS_BATT
DNI
1%10K
R12
05
DNIR12
03
10K
1%
U1200
BQ24192IRGER
2518
1211
10
1413
1615
22
21
2019
17
29
87
56
4
3
23
241 VBUS_1
VBUS_2
PMID
PG_n
STAT
SDASCL
INTOTG
CE_nPSEL
PGND_1
SW_1SW_2
BTST
REGN
SYS_1SYS_2
BAT_1BAT_2
ILIM
TS1TS2
PGND_2PGND_3
PWR_GND_BQ
1%10K
R12
04
1%10K
R12
02
MANGO GREEN
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REV SCH REV PCB
1 2 3 4 5 6 7 8 9 10 11
A
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This document contains information which
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licensed pursuant to Creative Commons
Attribution 4.0 International License.
Copyright (C) 2016
R12
20
5.23
K1%
R12
19
30.1
K1%
C12
05
4.7u
F
R12
10
10K
1%
REGN_BATT
1%10K
R12
08
1%10K
R12
14
REGN_BATT
C12
02
220n
F
C12
03
220n
F
Q1200MOSFET P-CHANNEL
B2C2 B1C1 A2
A1
G
SD
DNI
33R985
DNI
R1213
00%
C12
00
10uF
Q1201
NPN
6
1
2
U1201
BQ27621YZFR-G1A
B2C1
B3
C3C2
B1
A1
A2
A3SCL
SDA
GPOUT
BIN
BAT_1BAT_2
VDD
VSS_2VSS_1
D12
00
SM
AJ2
0CA
V_BATT
PWR_GND_BQ
VGPIO
V_BATT 1%10K
R12
09
C12
13
470n
F
DNI
R1222 10K
R1224 10KVGPIO
DNI
1uF
C12
41
TP1200
TP1201
TP1202TP1203
C12
15
220n
F
C12
10
1uF
PWR_GND_BQPWR_GND_BQPWR_GND_BQ
GPIO1/I2C1_CLK
GPIO5/I2C1_DATA
BattChrgr_PG_N
STAT_BATT
V_IN
BattGauge_GPIO
BattChrgr_INT_N
Battery_detect
charger_I2C_DATAcharger_I2C_CLK
TEMP_SENS
I2C address 6BH
* For High Reliability systems use the
together using Pin 25 as connection pointConnect PWR_GND_BQ and Main ground
measured to monitor total * Voltage on ILIM can be
V > 20V
PCB layout note
WD feature of BQ24292i
PSU Front End and 3.7V DC/DC converter
MAX OPERATIVE INPUT VOLTAGE = 17V
Imax= 3.8A
input current on device
Default value 2.2uH
Place as close as possible
(ABSOLUTE MAX INPUT VOLTAGE = 20V)
I_lim_max = 3.5A
I2C address 55H
Notes:
MIN OPERATIVE INPUT VOLTAGE = 5V (3.9V with BATT)
Ideal battery should have a 103-AT thermistor insideIf using battery with no thermistor then short Pin1 and Pin2 of CN1203
I2C address 1010101bI2C address 1010101b
U1301
TPS62091RGTR
17
156
345
16
21
14
9
87
13
10
1112
PVIN_1PVIN_2
AVIN
EN
CPCN
SS
PGND_1
SW_1SW_2
VOS
FBPG
FREQ
AGNDPGND_2
SLUG
R1324
00%
100n
F
C13
21
0H
L1306
100n
F
C13
17
0H
L1307
VCC_3V3
5%51K
R1303
R13
13
365K
1%
VCC_3V3R1336
51K5%
DNI
5%
R13
06
10K
51K
R1302
5%
DNIFPF2164
U1303
6
75
1432 VIN VOUT
FLAGB ISET
GND1 GND2
ON
100n
F
C13
13
C13
07
10nF
DNI
DNI
R1318
51K5%
U1302
SC195ULTRT
5
6
4
7
8
1
2
3 CTL0
CTL1
CTL2
CTL3
IN
OUT
LX
GND
47uF
C13
05
VCC_3V7U1300
TPS61230DRCR
11
875
43
9
6
21
10VIN
SW_1SW_2
SS
EN
VOUT_1VOUT_2
PGFB
HSY
GND
C13
03
47uF
C13
01
100n
F
C13
04
100n
F
C13
06
10nF
L1302
1uH
C13
15
47uF
C13
16
47uF
100n
F
C13
12
100n
F
C13
10
L1303
0H
47uF
C13
14
VCC_3V7
5%10K
R1308
R1309
5%10K
5%10K
R1310
5%10K
R1311
1uH
L1305
10uF
C13
20
VCC_1V8
100n
F
C13
24C13
22
100n
F
L1308
0H
VCC_5V0
R13
07
1ME
G1%
R13
14
91K
1%
VCC_3V7
C13
18
47uF
L1300
0H
C13
00
100n
F
C13
02
100n
F
C13
23
100n
F
100n
F
C13
191%499K
R13
15
C13
26
100n
F
C1309
10nF
C13
11
10nF
1uH
L1304
0%0
R13
12
DNI
R1319
51K5%
DNI
1%1M
EG
R13
05
R1326
00%
DNI
R13
25
182
1%
DNI51K5%
R1320
DNI
U1304
FPF2164
6
75
1432 VIN VOUT
FLAGB ISET
GND1 GND2
ON
VCC_3V3
DNI
R1321
51K5%
R1327
00%
DNI
R13
28
182
1%
100n
F
C13
25
DNI
R1322
51K5%
DNI
U1305
FPF2164
6
75
1432 VIN VOUT
FLAGB ISET
GND1 GND2
ON
DNI
R1323
51K5%
DNI
R13
29
182
1% C13
27
100n
F
DNI
10nF
C13
08
MANGO GREEN
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PROJECT
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DATE/TIME
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SITE
LEAD ENGINEER
REV SCH REV PCB
1 2 3 4 5 6 7 8 9 10 11
A
B
C
D
E
F
G
H
I
J
OF
This document contains information which
is proprietary to Sierra Wireless Inc. and is
licensed pursuant to Creative Commons
Attribution 4.0 International License.
Copyright (C) 2016
L1301
0H
DNI
C13
30
100n
F
TP1300
TP1301
TP1302
TP1303
TP1304
TP1305
PG_3V3
DCDC_shutdown
ENA_1V8
ENA_5V
Replace with FPF2163 if Autorestart is required
Current Limit = 1.5A typ
Current Limit = 1.5A typ
Replace with FPF2163 if Autorestart is required
Current Limit = 1.5A typ
Replace with FPF2163 if Autorestart is required
5V boost, 3V3 and 1V8 Buck
0H
L1402
100n
F
C14
15
0H
L1403
100n
F
C14
19
L1405
0H
L1404
0HR
1417
1.5K 1%
DNI
C14
20
100n
F
DNI
C14
21
100n
F
DNI
C14
22
100n
F
100n
F
C14
25
DNI
L1401
0H
TP1401
TP1400
100n
F
C14
26
DNI
100n
F
C14
24
DNI
10uF
C14
02
TPS7A7300
U1400
21188
12
32
4
20191
5
13
14
171615 IN_1
IN_2IN_3
EN
SS
50mV100mV
6
200mV7
400mV9
800mV10
1.6V11
OUT_1OUT_2OUT_3
PG
SNSFB
NC
GND_1GND_2GND_3
C14
01
100n
F
100n
F
C14
00
VCC_3V7
C14
07
47nF DNI
R1406
33K1%
VCC_CF3_FILT
C14
14
100n
F
C14
08
100n
F
C14
13
47uF
1%220K
R1404
Q1303NPN
32
1
220K
R14
12
1%1%33
K
R14
13
00%
R1408
DNI
R1407
DNI0%0
VBATT_MAIN_Supply
U1455
C1C2B1B2A1A2 VIN1 VOUT1
VIN2 VOUT2ON GND
R1405
51K5%
DNI
C14
17
1.5m
F
1.5m
F
C14
16
DNI
R1415
100K
30%
2
31
1%
DNIR14
14
33K
R14
16
33K
1%
DNI
VCC_CF3_FILT
C14
18
100n
F
VCC_CF3_FILT
1%220K
R1419
VBATT_Secondary
NPNQ1304
32
1
U1505
C1C2B1B2A1A2 VIN1 VOUT1
VIN2 VOUT2ON GND
5%
R1421
51K
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This document contains information which
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licensed pursuant to Creative Commons
Attribution 4.0 International License.
Copyright (C) 2016
VBATT_Secondary
VBATT_BB_Secondary
VBATT_RF_Secondary
C14
11
100n
F
47uF
C14
09
C14
12
100n
F
47uF
C14
10
VBATT_MAIN_Supply
100n
F
C14
06
47uF
C14
04
VBATT_BB
VBATT_RF
100n
F
C14
05
47uF
C14
03
DNI
U1420
LMP8645
254 1
63 +IN V+VOUT-IN
RG V-
DNI
R14
18
100m
1%
DNI
100K
R14
20
1%
DNI
R14
22
100K
1%
TP1406
TP1405DNI
R14
24
10K
1%
DNI
R1423
10K1%
TP1408
TP
1411
TP
1409
100n
F
C14
23
DNI
TP1407
TP1402
TP1410
TP1404
TP1403
R14
01
1.5K 1%
GND
EN_LDO
Correct_insertion
S_Correct_insertion
LDO_PG
Bigger Size
Bigger Size
CF3 LDO
Vout = 3.8V
1%1MEG
R1535
33R150033R1501
SW1500
PUSH BUTTON
21
43
R1578 0
C15
11
22pF
R1543
0
DNIR1537
0
R1575
1.5K
R15
41
DNI
1%10K
DNI0R1532
SSW-106-01-F-S
CN1502
54321
6
VCC_ARDVCC_5V0
VCC_3V3
C15
03
1uF
C15
02
1uF
IO13
VCC_ARDVCC_ARD
R1528 0
DNI
R1526 0
1uF
C15
00
VCC_5V0
VCC_ARD
R1560
1005%
100n
F
C15
20
C15
21
10uF
D40
1
0.05
pF
DNI
R1538
0
VCC_ARD
VCC_ARD
VCC_5V0
VCC_1V8
VCC_ARD
Y1500
16MEGHz42
1 3
D1501
C15
82
1uF
C15
84
1uF
C15
80
100n
F
C15
10
22pF
D1500
IO13IO12
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A
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This document contains information which
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Copyright (C) 2016
R1561
1.5K
A4A5
R1531
0
IO11IO10
CN1503
SSW-108-01-F-S
54321
876
1nF
C15
05
33R1509
VCC_5V0VCC_3V3
33R1520R1519 33R1518 33
33R1521
VCC_ARD
VCC_ARD
R1511 33
VCC_ARD
R15
65
1%10K
R1512 33
R1515 33
L150
5
0H
U1515
B1C2D1 A1
A2D2C1 B2VCCBVCCA
A1 B1B2A2
OE GND
R1514 33R1513 33
R1505 33
SSW-108-01-F-S
CN1500
54321
876
R1510 33
33R1516
CN1501
SSW-110-01-F-S
54321
109876
33R1506
33R1504
R1507 33
33R150333R1502 IO9
IO8
D3/SCLD2/SDA
VCC_ARD
MOSI
5%20m
R1542
VCC_ARD
VCC_ARD
A4A5
A1A0
A2A3
D6
D4TXLED
D1/TXD0/RX
IO12
D2/SDAD3/SCL
U1500
ATmega32U4-MU
45
363738394041
133
2726222521201918
3231
12302928111098
43352315
5
347
6
2
42
13
1617
4424
3414 VCC_1
VCC_2
AVCC_1AVCC_2
XTAL1XTAL2
RESET_n
AREF
UVCC
UCAP
VBUSD+D-
UGND
GND_1GND_2GND_3GND_4
PB0PB1PB2PB3PB4PB5PB6PB7
PC6PC7
PD0PD1PD2PD3PD4PD5PD6PD7
PE2PE6
PF0PF1PF4PF5PF6PF7
GND_5
D5
IO11IO10
IO8IO9
MISOMOSISCKRXLED/SS
D7
100
R15
63
DNI33
R1540
10K1%
R1522
CN1504
TSW-103-07-G-D
531 2
46
VCC_5V0
R15
44
1%10K
DNI
100n
F
C35
0
R1530
0
DNI
C33
3
100n
F
4.7u
F
C33
4
R1539
0
U1506
FT230XQ-R
1451112
416215
17133
9
8
110 VCC
VCCIO
3V3OUT
USBDM7
USBDP6
RESET_n
GND1GND2GND3
TXDRXD
RTS_nCTS_n
CBUS0CBUS1CBUS2CBUS3
VCC_3V3
ARDUINO_RESET
ARDUINO_RESET
ARDUINO_RESET
ARDUINO_RESET
VCC_5V0
USB1_D+USB1_D-
D7
D7
TXLED
TXLED
D4D4
D1/TX
D1/TX
D1/TX
D0/RX
D0/RX
D0/RX
D5
D5
A0
A0
A1
A1
A2
A2
A3
A3
A4
A4
A5
A5
UGND
AREF
AREF
AREF
XTAL2
XTAL2
XTAL1
XTAL1
ARDUINO_RESET_Level shiftWP2Arduino_reset
RXLED/SS
RXLED/SS
USBD-_ARDUSBD+_ARD
WP2Arduino_reset_level
WP2Arduino_reset_level
D6
D6
D2/SDAD2/SDA
D2/SDA
D3/SCL
D3/SCL
D3/SCL
IO9
IO9
IO8
IO8
MISO
MISO
MOSI
MOSI
SCK
SCK
ARD_FTDI
IO13
IO13
IO12
IO12
IO11
IO11
IO10
IO10
If powered by 5V populate R1531 and R1539
Arduino RESET
ARDUINO Voltage Select
If powered by 3.3V populate R1530, R1532, R1539 and C350If VCC=5V and VCCIO = 3.3V populate R1530, R1531, R1539 and C350 - (remove R1532)
Power
ADC
Default to 5V
IOL
IOH
Arduino ConnectorARDUINO_RESET: Need to connect: use level shifter
ICSP
Make sure to line up Arduino connector orientation properly
Match reset to how it is done on Leonardo
Self powered mode
