1280 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 45, NO. 6, JUNE 1998

A Low Thermal Budget Self-AlignedTi Silicide Technology Using Germanium

Implantation for Thin-Film SOI MOSFET’sPing Liu, Member, IEEE,Tommy C. Hsiao,Member, IEEE,and Jason C. S. Woo,Senior Member, IEEE

Abstract—In this paper, a titanium salicide technology with avery low thermal annealing temperature using germanium im-plantation for thin film SOI MOSFET’s is investigated in detail.Ti silicide formation on the amorphous silicon generated by ger-manium implantation is studied. Compared to the conventionalTi salicide process, the Ti silicidation temperature is significantlylowered and the silicide depth is well controlled through thepre-amorphized layer. Therefore, the potential problems of thesalicide process for SOI MOSFET’s such as lateral voids, dopantsegregation, thermal agglomeration, and increase of resistance onnarrow gate are suppressed by germanium implantation. Withthe Ge pre-amorphization salicide process, a very low silicidecontact resistance is obtained and sub-0.25-�m SOI MOSFET’sare fabricated with good device characteristics.

Index Terms—CMOS, silicide, SOI.

I. INTRODUCTION

T HIN-FILM silicon-on-insulator (SOI) technology ispromising for low-power and high-speed ULSI’s

application because of its low threshold voltage operationand reduced source/drain capacitances [1]–[5]. However,high source/drain series resistance may degrade the deviceperformance by dramatically reducing drive current. Theproblem becomes more severe as SOI films get thinner [6],[7]. In bulk and SOI MOSFET’s, the self-aligned silicide(salicide) has been applied for the reduction of both the gateand the source/drain parasitic resistances [8]–[13]. However,salicide technology faces challenges when the gate is scaledinto the deep sub-micrometer regime. For example, Ti salicidesuffers from the difficulty of phase transformation from C49-TiSi to the low resistivity C54-TiSi, which gives high sheetresistance on the gate silicide. For the SOI MOSFET’s, dueto the limited supply of Si for the silicidation, voids canform at the interface of silicided and unsilicided source/drainregions, resulting in an extremely high contact resistance andeven a failure of electrical contact [8]. In the worst case,full silicidation of SOI films to the buried oxide will greatly

Manuscript received June 30, 1997; revised October 22, 1997. The reviewof this paper was arranged by Editor D. P. Verret.

P. Liu was with the Department of Electrical Engineering, University ofCalifornia, Los Angeles, CA 90095 USA. He is now with Integrated DeviceTechnology, Sunnyvale, CA 94088 USA.

T. C. Hsiao was with the Department of Electrical Engineering, Universityof California, Los Angeles, CA 90095 USA. He is now with Advanced MicroDevices, Inc., Santa Clara, CA 95054 USA.

J. C. S. Woo is with the Department of Electrical Engineering, Universityof California, Los Angeles, CA 90095 USA.

Publisher Item Identifier S 0018-9383(98)03669-7.

increase the possibility of lateral void formation because thereis no vertical Si supply from the bottom and a large amountof Si has to diffuse a certain distance to react with the metal[14]. Dopant segregation from the doped Si in the source/draininto the silicide also affects the silicide contact resistance. Asmooth silicide/silicon interface with a high carrier density isnecessary for a good ohmic contact. Recently we proposeda novel germanium pre-amorphization salicide technology tocontrol the silicide depth and alleviate floating body effect ofthin film SOI MOSFET’s [15], [16]. In this paper, we presenta detailed study on solid phase reaction of Ti with Ge pre-amorphized Si and the process development of a low thermalbudget depth-controlled Ti salicide technology for thin filmSOI MOSFET’s.

II. EXPERIMENTS

Both lightly p-type doped bulk Si (100) and SOI/SIMOX(Separation by IMplantation of OXygen) wafers were usedin this study. By thinning oxidation of SIMOX wafers, SOIwafers with thickness below 100 nm and good uniformitywere achieved. Ge pre-amorphization was carried out withthe dose in the range from to cm atenergies from 20 to 100 keV to produce different amorphousdepths in Si prior to Ti deposition. The projected ranges ofGe implants were calculated by the TRIM program [17].Titanium was deposited by sputtering in a base vacuumof Torr. The temperature of the rapid thermalprocessing (RTP) for Ti silicide formation was varied from400 to 1000 C Two-step anneals were performed with aselective etch with HSO H O to form the salicide. Thesalicide process was characterized by four-point probe sheetresistance, cross-sectional transimission electron microscopy(TEM), X-ray diffraction (XRD), and Alpha-step profilometer.The spreading resistance probe (SRP) technique was used tocharacterize the carrier concentration in SOI films. In additionto silicide formation study, fully depleted MOSFET’s werefabricated using a Ge pre-amorphization process on 82-nmSOI wafers. Fig. 1 outlines the key steps for the Ge pre-amorphization Ti salicide process flow.

III. RESULTS AND DISCUSSION

Fig. 2 shows the temperature dependence of the sheetresistance of Ti silicides which are formed on both single-crystalline Si and Ge pre-amorphized Si by RTP at tem-

0018–9383/98$10.00 1998 IEEE

LIU et al.: LOW THERMAL BUDGET SELF-ALIGNED Ti SILICIDE TECHNOLOGY 1281

Fig. 1. The schematic Ge pre-amorphization Ti salicide process flow.

Fig. 2. Sheet resistance of Ti on Si with and without Ge implant versusannealing temperature. The Ge dose is1� 10

15 cm�2, and the anneal timeis 1 min.

peratures ranging from 400 to 900C Compared to thecrystalline Si, the amorphous Si produced by Ge implant startsto react with Ti to form silicide at a lower temperature, dueto substantially reduced silicide formation energy. With thisresult, Ge implantation was then applied to SOI wafers. TheGe implant energy was accordingly chosen so that approxi-mately 60–70% of the Si film would be amorphized. Fig. 3compares the silicide formation by two-step RTP with andwithout Ge preamorphization on both 50- and 100-nm SOIwafers with different Ge implant energies. The first step RTPwas performed at 450C This is much lower than that ofconventional Ti silicide processes which typically has the firststep RTP performed at 600–650C [18]. The result in Fig. 3shows that wafers with Ge implant have a much lower sheetresistance than those without Ge implant after the second RTP.An X-ray diffraction spectrum was used to confirm that C-54phase transformation was completed for TiSifilm formedwith Ge implant, as shown in Fig. 4. By using Ge implantto preamorphize the Si film, C54 TiSifilm with low sheetresistance can be achieved with a low thermal budget.

Previous experiments clearly showed that the silicide resis-tance would increase when the SOI films were fully silicideddue to the formation of metal-rich silicides [10]. A largeamount of voids were generated when the SOI film was fully

Fig. 3. Two-step anneals of Ti on thin film SOI with and without Ge implant(S.E.: selective etch). First step anneal: 450�C, 4 min. Second step anneal:800 �C, 1 min. The Ge implant dose is1 � 15 cm�2

:

Fig. 4. X-ray diffraction spectrum of the TiSi2 film formed by Gepre-amorphization. The sample went through the first step anneal at 450�Cfor 4 min and the second step anneal at 800�C, 1 min.

consumed for silicide reaction. In order to obtain optimizedpartially salicided source/drain for thin SOI devices, the energyof Ge implantation has been carefully chosen to assure thatthe TiSi is only formed within the amorphous layer, withsilicon remaining underneath the silicide after the silicidation.Fig. 5 shows the measured amorphous depth produced by theGe implantation versus the implant energy for the dose of

cm The amorphous depth was measured by thetapered groove profilometer (TGP) technique [19] and was alsoconfirmed by X-TEM. The Ge dose was chosen to be highenough to produce an amorphous layer. The control of silicidedepth through Ge pre-amorphization is demonstrated in Fig. 6[16]. 50-nm SOI and 100-nm SOI wafers were pre-amorphizedby Ge implant at 20 and 40 keV to produce approximately 30-and 60-nm amorphous depths, respectively. This was followedby the deposition of thin (20 nm for 50-nm SOI and 32 nmfor 100-nm SOI) and very thick (80 nm) Ti films. An 80-nmtitanium film is more than enough to consume all the Si filmsby a conventional Ti silicide process with first step RTP at600–650 C However, Fig. 6 shows that the sheet resistance

1282 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 45, NO. 6, JUNE 1998

Fig. 5. The depth of Si amorphous layer versus the energy of Ge implant.The Ge implant dose is1 � 15 cm�2:

Fig. 6. Two-step anneals of Ti films of different thickness on thin film SOIwith Ge pre-amorphization. First step anneal: 450�C, 3 min. Second stepanneal: 750�C, 1 min.

of the 80-nm Ti film is comparable to that of the thinner Ti filmafter the second RTP at 750C for 60 s. This suggests that Tionly reacts with the amorphous Si at the first low temperatureRTP. The remaining unreacted Ti has been stripped by theselective etch. As a result, the final silicide depth on thinfilm SOI is controlled by the amorphous layer instead of bythe thickness of deposited metal. Ge pre-amorphization makesthe source/drain resistance less susceptible to the variationof deposited metal thickness, thus the demand for silicideuniformity can be achieved.

The dependence of silicide formation on the anneal tem-perature is shown in Fig. 7. A 50 nm Ti film was depositedon Si wafers implanted with cm Ge at 80 keV.The first step anneal was performed at three different lowtemperatures (450, 475, and 500C for various intervals oftime, and the second anneal was done by a RTP at 750C for60 s for all samples. Fig. 7 shows that the sheet resistancesof the three samples reach their minimum values with theincrease of the anneal time. The corresponding silicide depths

Fig. 7. Dependence of silicide depth on first step anneal temperature. Allsamples went through second step anneal at 750�C after first step anneal andselective etch. The time for the first step anneal is 3 min.

Fig. 8. The silicide depth after two-step anneal versus the first step annealtemperature.

Fig. 9. The depth of silicides formed by 500 and 800�C anneals versus thedepth of amorphous layers generated by Ge implant. The Ge implant doseis 1 � 10

15 cm�2:

LIU et al.: LOW THERMAL BUDGET SELF-ALIGNED Ti SILICIDE TECHNOLOGY 1283

Fig. 10. Interface roughness between silicide and Si with and without Ge pre-amorphization.

after two-step RTP are also shown in this figure. It is clearthat, for different low temperatures of the first step anneal,silicide growth tends to saturate at different depths withinthe amorphous layer in a short period of time. This stronglysuggests that the silicide process can be well controlled by theamorphous layer and the low temperature annealing. To ensurethat Ti only reacts with amorphous Si layers, the temperatureof the first step RTP has to be chosen carefully. Fig. 8 showsthe final silicide thickness versus the first anneal temperaturefor the samples with 50 nm Ti deposited on Ge implanted(60 keV) Si. When the first anneal temperature is greater than500 C, Ti not only reacts with the amorphous Si but alsostarts to react with the crystalline Si underneath. The silicidedepth is controlled within the amorphous layer when the firstanneal was performed in the temperature range of 450 to500 C Fig. 9 shows the Ti silicide depth after the processversus the depth of the amorphous layer generated by differentGe implant energies (20–100 keV). All samples started with50 nm Ti and received first step RTP at 500C and secondRTP at 800 C, both for 60 s. The depth of the amorphous layerfor different Ge implant energies can be obtained from Fig. 5.It was found in Fig. 9 that the depth of silicide annealed atlow temperature increased with the depth of amorphous layer,indicating that the final silicide depth can be well controlled bythe depth of the amorphous layer, in other words, by choosinga proper Ge implant energy.

The alpha-step profilometer was used to scan the inter-face roughness after the silicide was stripped off by dilutedhydrofluoric acid, as shown in Fig. 10. It can be observedthat the interface between the silicide and the underlyingSi with Ge pre-amorphization is much smoother than thatwithout Ge pre-amorphization. TEM pictures give a moredetailed morphological image of the silicide interface. Fig. 11shows cross-sectional TEM micrographs of 32-nm Ti on Geimplanted 100-nm SOI after the first step anneal at 450Cand after selective etch plus second step anneal at 750C,respectively. As a sequence of the first step anneal at lowtemperature, it can be seen in Fig. 11(a) that Ti has alreadyreacted with Si to form the silicide (it can be a mixtureof metal-rich and C49 phases) with a flat interface betweensilicide and the remaining Si. The dislocation loops can be

clearly observed in Fig. 11(a) which were induced by the Geimplantation and subsequent silicide anneal. It indicates thatrecrystallization from the interface of amorphous layer withunderlying crystalline Si occurs during silicide reaction evenat low temperature anneal. This result strongly suggests thatsolid phase epitaxial (SPE) regrowth of the amorphous Si isenhanced by the silicidation on top of Si which facilitates themovement of Si atoms during the interaction of the metal andthe silicon. After the second anneal, the silicide film maintainsa flat interface and a good uniformity as shown in Fig. 11(b). Ahigh resolution cross-sectional TEM was performed to look atthe interface between the silicide and the SOI film, as shown inFig. 12. It further confirms that the silicide interface on Ge pre-amorphized SOI is very sharp, indicating that a well-controlleduniform silicide film on ultrathin SOI can be manufacturedthrough this pre-amorphization process.

Ge pre-amorphization salicide experiments were also carriedout on heavily doped SOI wafers. Heavily arsenic implantedSOI wafers were activated by furnace annealing (850C,30 min), followed by a Ge implantation to amorphize thesurface layer. It was found that Ge pre-amorphization sub-stantially lowers the silicide anneal temperature on arsenicdoped SOI wafers as it does on undoped SOI wafers. Fig. 13shows the carrier concentration profiles of the 150 nm SOIsample before and after silicidation measured by SRP. The flatregion of concentration in Fig. 13 corresponds to the buriedoxide layer. The profile of carrier concentration before Geimplant is also plotted as a reference. After Ge implantation,an amorphous layer is formed in the SOI surface regionwhere the carrier concentration is much decreased. Withsilicide formation by low temperature anneal at 450C, thecarrier concentration increases to a level similar to that beforeGe implant. A large amount of dopant has already beenactivated even at low temperature anneal because solid phaseepitaxial regrowth occurs underneath the silicide. This resultis consistent with the cross-sectional TEM result in Fig. 11(a).Large amounts of arsenic atoms stay in the remaining Si layerof SOI after silicide reaction with a high carrier concentrationat the interface, which is required for a low ohmic contact. Themeasured contact resistance between the silicide and silicon is

-cm

1284 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 45, NO. 6, JUNE 1998

(a) (b)

Fig. 11. Cross-sectional TEM micrographs of Ti on Ge pre-amorphized SOI (a) after first step anneal at low temperature (450�C) and (b) after selectiveetch and second step anneal at 800�C:

Fig. 12. The high resolution cross-sectional TEM micrograph of TiSi2 on SOI with Ge preamorphization.

A four point probe sheet resistance test structure wasused to test the polysilicon line width dependence of silicidesheet resistance. Polysilicon was doped by arsenic implantand subsequently annealed for 30 min at 900C Afterthat, some doped polysilicon received cm Geimplant at 40 keV. Fig. 14 shows the sheet resistance ofsilicide on polycrystalline Si lines versus the line width from3 m down to 0.2 m The results show that using the Gepre-amorphization salicide process, a low Ti silicide sheet re-sistance of 5.8 sq was achieved on a 0.2-m polyline. Onthe other hand, Ti silicide formed by the conventional salicide

process without Ge pre-implant has a high sheet resistance20 sq It is predicted that this Ge pre-amorphization

salicide technology is applicable for deep submicron devices.Fig. 15 shows the output characteristics of a 0.22-m

transistor with Ge pre-amorphization salicide process. Thetransistors previously fabricated with the conventional salicideprocess shows degraded drive current due to high source/drainresistances [16]. Fig. 16 shows the subthreshold characteris-tics of the transistor in Fig. 15. The low leakage current at

V indicates that there is no bridging effect betweensource/drain and gate, and Ge preamorphization salicide does

LIU et al.: LOW THERMAL BUDGET SELF-ALIGNED Ti SILICIDE TECHNOLOGY 1285

Fig. 13. Profiles of carrier concentration measured by SRP before and aftersilicidation on Ge implanted SOI. SOI thickness is 150 nm.

Fig. 14. Sheet resistance of silicide on polysilicon lines versus the line width.The conventional Ti salicide was performed by the the first step RTP at 620�Cfor 1 min and the second step RTP at 850�C for 1 min.

not induce an increase of junction leakage at high drainbias. Pre-amorphization using Si implantation has previouslybeen used for Ti salicide process on bulk CMOS devicesfabrication to obtain low sheet resistance of TiSi2 on narrowpolycrystalline Si gate [20], [21]. However, in this work Gepre-amorphization is used to significantly lower the salicideformation temperature in the SOI MOSFET’s. As a result,lateral voids in the source/drain and dopant segregation to thesilicide from the doped Si region are suppressed during thelowered temperature of the thermal cycle.

IV. CONCLUSION

A Ge pre-amorphization Ti salicide process with a low ther-mal budget has been developed for thin film SOI MOSFET’s.The formation energy for silicide is substantially reducedby Ge pre-amorphization which introduces a much lowertemperature for the solid phase reaction for silicide. A welldepth-controlled thin silicide film can be achieved by theoptimization of the Ge implantation, anneal temperature, and

Fig. 15. OutputI�V characteristics of the NMOS transistor with Ge pre-amorphization salicide process.We�=Le� = 8:2=0:22 �m; Tox = 7 nm,TSi = 82 nm; NA = 1015 cm�3, andTTi = 32 nm. The Ge implant:40 keV, 1 � 15 cm�2:

Fig. 16. Subthreshold characteristics for the NMOS transistor in Fig. 15.

anneal time. A very sharp silicide interface without agglomer-ation has been obtained with Ge implant. Low silicide contactresistance indicates the dopant segregation to silicide has beensuppressed by Ge pre-amorphization and low silicide reactiontemperature. Good device performance as well as low sheetresistance on fine polysilicon lines indicates this technology isscalable to the deep submicron regime.

ACKNOWLEDGMENT

The authors would like to thank Dr. N. Zhu and C. Hwangfor their technical assistance during this work.

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Ping Liu (M’95) was born in China on July 6, 1965. He received the B.S.,M.S., and Ph.D. degrees in electrical engineering from Fudan University,Shanghai, China, in 1986, 1989, and 1992, respectively.

Currently, he is working on CMOS process integration at Integrated DeviceTechnology, Inc., Santa Clara, CA. From 1992 to 1994, he was with theShanghai Institute of Metallurgy, the Chinese Academy of Sciences, workingin the area of ion implantation and SOI technology. From March 1994 untilSeptember 1994, he was a Visiting Scholar at the University of Surrey, Surrey,U.K., where he worked on salicide and SOI technologies. From November1994 to October 1997, he was a Research Associate at the Universityof California, Los Angeles, where he was involved in shallow junctiontechnology, salicide technology, and process integreation for the thin-filmSOI CMOS devices.

Tommy C. Hsiao (S’92–M’98) received the B.S. degree in electrical engi-neering from National Taiwan University, Taipei, Taiwan, R.O.C., in 1987,and the M.S. and Ph.D. degrees in electrical engineering from the Universityof California, Los Angeles, in 1993 and 1997, respectively.

Currently, he is a Senior Process Integration Engineer at Advanced MicroDevices, Inc., Sunnyvale, CA, where he is involved in the research and devel-opment of state-of-the-art flash memory process technology. From November1994 to March 1997, he conducted his research at Stanford NanofabricationFacility (SNF), Stanford, CA, focusing on process development and integra-tion issues associated with SOI CMOS devices in submicrometer regimes.His research interests are in the modeling and characterization of SOI CMOSdevices.

Jason C. S. Woo(S’83–M’87–SM’97) received the B.A.Sc. (Hons) degree inengineering science from the University of Toronto, Toronto, Ont., Canada, in1981, and the M.S. and Ph.D. degrees in electrical engineering from StanfordUniversity, Standford, CA, in 1982 and 1987, respectively.

In 1987, he joined the Department of Electrical Engineering, the Universityof California, Los Angeles, where he is currently a Professor. His researchinterests are in the physics and technology of novel device and devicemodeling and he has authored or coauthored over 90 papers in technicaljournals and refereed conference proceedings in these areas.

Dr. Woo served on the IEEE IEDM Program Committee from 1989 to 1990,1994 to 1996, and was the Publicity Vice Chairman in 1992 and the PublicityChairman in 1993. He has been the Workshop Chairman and a TechnicalCommittee Member of the VLSI Technology Symposium since 1992. He hasserved on the committee for the IEEE SOI Conference since 1995. He receiveda Faculty Development Award from IBM in 1987 through 1989.