A Light-Weight C/C++ Based Tool for Hardware Verification

Alexander Kamkinkamkin@ispras.ru

CTestBench

Institute for System Programming of the Russian Academy of Sciences http://hardware.ispras.ru

East-West Design and Test Symposium, St. Petersburg, September 17-20, 2010 2 of 24

Variety of tools for hardware verification

Simulation-based verification Methods and approaches

Co-simulation, CRV, ABV, CDV, etc

Languages and tools SystemC, SystemVerilog, CTESK, etc

Formal methods-based verification Methods and approaches

Model checking, automated theorem proving, etc

Languages and tools SMV, SPIN, HOL, PVS, etc

East-West Design and Test Symposium, St. Petersburg, September 17-20, 2010 3 of 24

Verification engineer’s professional skills

Programming skills Languages (C/C++, Perl, Shell, etc) Tools (compilers, debuggers, IDEs, etc)

Hardware verification skills Languages (SystemVerilog, OpenVera, PSL, etc) Methods (AVM, OVM, UniTESK, etc)

Hardware design skills Languages (Verilog, VHDL, SystemC, etc) Simulators (ModelSim, VCS, etc), PLI (VPI, DPI, etc)

Mathematical background Discrete mathematics, mathematical logic, etc

East-West Design and Test Symposium, St. Petersburg, September 17-20, 2010 4 of 24

“As simple as possible but not simpler”

Shortening a VE’s learning curve Simple and clear conception of a method Minimum of constructs in a tool’s core Well-known programming languages Well-known development environments

Extending the tool facilities by easy integration FSM-based test generators Test parallelization mechanisms Web-based test management system Specialized libraries for test generation

East-West Design and Test Symposium, St. Petersburg, September 17-20, 2010 5 of 24

Why C/C++?

Easy learning Ideal for teaching young specialists All verification engineers know C/C++

Integration with simulators and tools VPI (Verilog Procedural Interface) DPI (Direct Programming Interface)

Code reuse Golden (reference) models in a verification environment Modules of a cross-development simulation environment

Efficiency Shortening test execution time Shortening simulation time

East-West Design and Test Symposium, St. Petersburg, September 17-20, 2010 6 of 24

CTestBench architecture

Core

Core

Modelingcore

Testingcore

Libraries

External tools

Test generation tools

Rep

ort

gene

ratio

n t

ools

Test m

anagement to

ols

Com

ponentsGen

erat

ors

Examples

East-West Design and Test Symposium, St. Petersburg, September 17-20, 2010 7 of 24

CTestBench modeling core

Model

void cycle()void reset()

Interface

void start()void stop()

Message

void getField()void setField()

MyInterface

void start()void stop()

MyMessage

void getField()void setField()

MyModel

void operation1()void operation2()

extends extends extends

uses

East-West Design and Test Symposium, St. Petersburg, September 17-20, 2010 8 of 24

CTestBench operation description

void MyModel::MyOperation(Process &process,

Interface &iface, Message &message)

{

start(); // Starting the operation

// Setting input signals

for(...)

{

... // Performing some action

cycle(); // Emulating a cycle

check(...); // Checking some condition

}

stop(); // Stopping the operation

}

East-West Design and Test Symposium, St. Petersburg, September 17-20, 2010 9 of 24

CTestBench testing core

Test

void run()void start()void delay()

MyMediator

void read()void write()void sync()

MyTest

void run()

extends extends

contains

MyModel

void operation1()void operation2()

East-West Design and Test Symposium, St. Petersburg, September 17-20, 2010 10 of 24

CTestBench test casevoid MyTest::run()

{

start();

for(...)

{

Message msg1, msg2;

...

// Starting two operations in parallel

start(MyOperation1, model.iface1, msg1);

start(MyOperation2, model.iface2, msg2);

// Emulating 10 cycles

delay(10);

}

stop();

}

East-West Design and Test Symposium, St. Petersburg, September 17-20, 2010 11 of 24

Synchronization with an RTL model

MyMediator

void read()void write()void sync()

extends

MyModel

void operation1()void operation2()

read

write

sync

East-West Design and Test Symposium, St. Petersburg, September 17-20, 2010 12 of 24

Testbench development process

Development of a reference model Interfaces, operations, data types, etc

Debugging of a reference model Simple test cases

Synchronization with an RTL model Synchronization functions

Development of a test generators Complex test cases

East-West Design and Test Symposium, St. Petersburg, September 17-20, 2010 13 of 24

Beyond the core

FSM-based test generators

Constraint-driven randomization

Verilog code analyzers

Test parallelization engine

Test management system

Report generators

East-West Design and Test Symposium, St. Petersburg, September 17-20, 2010 14 of 24

Experience

Translation lookaside buffer CTESK

Floating point unit CTESK

L2 cache CTESK

Commutator CTESK

Interrupt controller CTESK / CTestBench

Memory access unit CTESK / CTestBench

East-West Design and Test Symposium, St. Petersburg, September 17-20, 2010 15 of 24

Contacts Institute for System Programming of RAS (ISPRAS)

http://www.ispras.ru

Hardware verification R&D @ ISPRAShttp://hardware.ispras.ru

Alexander Kamkinkamkin@ispras.ru

East-West Design and Test Symposium, St. Petersburg, September 17-20, 2010 16 of 24

Thank You!

Questions?