Nuclear Instruments and Methods in Physics Research A324 (1993) 260-262North-Holland

A large CAMAC histogramming memoryM. Brendle and G. LudePhysikalisches Institut der Untuersitht Tübingen, Auf der Morgenstelle 14, D-7400 Tübingen, Germany

Received 23 June 1992

A CAMAC histogramming-memory module with a capacity of 4194304 24-bit words is described. A modified LeCroy-businterface is used for the input data and the CAMACbus for readout . Fast block transfers (avoiding Q test) are supported.

1. Introduction

Often the lack of sufficiently large histogrammingmemories is the reason why two- or more-dimensionalpulse-height data are stored in list-mode memoriesfirst . Only afterwards, in an off-line process, are thesedata converted into histograms. Here we present alarge, yet inexpensive, histogramming memory. We shalluse it as a part of a data acquisition system consistingof ADCs#1 , a multiplex-switch controller [1], a pro-grammable digital router [2,3], one or several his-togramming memories, and a list-mode device#2 .

2. Circuit description

A simplified block diagram of the memory moduleis shown in fig . 1 .

Input data are received by the front-bus interface, amodified LeCroy-but interface#' . The original LeCroyADC but is 16 or 20 bits wide . In order to bypass thelimitations of the bus width, we established a block-transfer mode with a data width of 16 bits . A block islead by a header . Header words differ from followerwords sufficient for a 22-bit histogramming address, a3-bit histogramming-memory by the most-significantbit . So, a two-word "block" is number for distinguish-ing up to eight histogramming-memory modules, andfive spare bits . The latter can be used for additionalreceiver address bits or for additional flags (e.g . flagscontrolling simultaneous storage of data in the his-

#t At this time, we are using model 3512 ADCs by LeCroyCorporation, 700 Chestnut Ridge Road, Chestnut Ridge,NY 10977-6499, but we are developing a fast pulse-heightADC, based on a novel technique .

#2 A fast-readout CAMAC list-mode device is under devel-opment here .

0168-9002/93/$06.00 © 1993 - Elsevier Science Publishers B.V . All rights reserved

NUCLEARINSTRUMENTS& METHODSIN PHYSICSRESEARCH

SectionA

togramming memory and in a list-mode device). Blocktransfers are protected against interrupts by higher-pri-ority senders.

Because of their low cost, the memory is built fromdynamic random-access integrated circuits (DRAMICs) . It consists of four banks, each holding six DRAMICs with a capacity of either 256 k or 1 M 4-bit nibbles.So, by equipping one to four banks with less or moreexpensive memory chips, the total memory capacity canbe varied from 256 k to 4 M 24-bit words.

The memory control circuit contains the refreshclock, an access arbiter, and the timing control circuit .The arbiter grants access requests by the front-businterface, the refresh clock, and the CAMAC interfaceon the basis of rotating priorities. The address multi-plexer selects either the front-bus-defined or the CA-MAC-defined memory address, and it switches be-tween row and column addresses.

On a front-bus request, the memory word addressedby the input address is read, incremented, and writtenback into the same location . This is done in a singleread/modify/write memory cycle.

Designing a CAMAC interface for a multiportmemory is difficult for the following reasons: there isno early strobe indicating valid address and functionsignals ; read data must be valid at a rather early timewithin a CAMAC read cycle; it is impossible to prolonga CAMAC read cycle if the memory is busy servicing acompeting requester [4] . A conventional solution to thelatter problem consists in invalidating the Q responsein case of access failures . Of course, the Q responsemust be tested after every read access - a time-con-suming procedure. In order to facilitate high-speedblock transfers, we choose another solution :

Access to a single memory cell or to a contiguousblock of memory cells is initiated by writing the mem-ory address into a CAMAC-writable address register,an autoincrement register . Loading this register starts

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Front-Bus Control Lines

M. Brendle, G. Lude / A large CAMAC htstogramming memory

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a memory read access to the location address by theautoincrement address register . The result is stored ina CAMAC-readable data register . Depending on theCAMAC function code, reading of the data registerwill or will not increment the content of the CAMACaddress register . In both cases, a memory read cyclewill be started automatically, bringing the content ofthe old resp . new location into the data register . Front-bus-initiated read/modify/write cycles consume 300ns each, and CAMAC-initiated read cycles and refreshcycles, 220 ns each . Apparently, the sum is much lessthan the minimum CAMAC cycle period . Therefore,even at the highest readout speed and the highestinput data rate, the data read are always valid. Simi-larly, using two other CAMAC function codes, thelocation addressed by the address register can becleared with or without the prior incrementation of theaddress register. Clearing is done by writing the con-tent of the zero register in the addressed memorylocation . In order to make optimal use of the data-pre-fetch feature, the CAMAC crate controller shouldsupport "Ignore-Q" repeat-mode block transfers .

Not only does the CAMAC interface facilitate sin-gle-location read, block read, single-location clear, andblock clear operations, but also disabling and enablingfront-bus accesses .

The histogramming memory occupies a single two-layer printed board. The component cost of a maxi-mum-capacity module amounts to less than 1000 $.

M. Brendle, G . Lude / A large CAMAC histogramming memory

3. Performance

For testing the front-but speed, input data weregenerated by one of our front-end processors [2] . Up to400000 double words/s could be processed. Our CA-MAC crate was controlled by a crate controller KineticSystems Model 3922-Zia, connected by an interfacecard Kinetic Systems Model 2926-Zla to an IBM-ATcompatible no-name PC with a 16-MHz 80286 CPU.The speed of clearing and reading the histogrammingmemory was limited by those devices only . We couldachieve a read-out speed of 48000 words/s when thePC-interface was polled for data, but only 35 000words/s using DMA. Clearing is possible with a speedof 100000 words/s using the interface-polling method .We are convinced that, by designing a better cratecontroller and interface, the read-out rate might beincreased by a factor of 5 at least.

The histogramming memory consumes only 1 .3 A at+6 V.

References

[1] M. Brendle and K. Schmidt, Nucl . Instr. and Meth . A302(1991) 339.

[2] M. Brendle, M. Ermer, P. Grabmayr, J. Kotz and A.Mondry, Nucl. Instr. and Meth . A302 (1991) 342.

[3] M. Brendle and G. Lude, An advanced preprocessor formultiparameter experiments, to be published.

[4] CAMAC, Amodular instrumentation system for data han-dling, EURATOM report EUR 4100 e.