A High Frequency CMOS Low Noise Amplifier Design for Cellular

ApplicationsApplications

Hatim Bukhari Joshua Duncan and Jonathan WilsonHatim Bukhari, Joshua Duncan, and Jonathan Wilson

EECS 413 – Professor Wentzloff

December 3 2007December 3, 2007

Motivation for LNAMotivation for LNA• LNAs offer good compromise between noise performance and g p p

high gain amplification

• Cellular technology (both basestation and handset) require LNAs to:

• Increase connection range (for a given SNR)

• Reduce dropped calls

I bl ki f• Improve blocking performance

• Improve call performance and connection quality

• Demand for size, cost, and complexity reductions motivate integration of LNA into CMOS technologyg gy

LNA System Block DiagramLNA System Block Diagram• Design consists of:

• Band‐gap reference current source

• Cascoded common source gain stage with input matching

l d ff l• Single input to differential output converter

• Operates in EGSM cellular band for uplink from handsets to• Operates in EGSM cellular band for uplink from handsets to basestation (880 – 915 MHz)

Band‐gap Reference Current Source Operation

• Cascoded self‐biasing network produces supply insensitive currentscurrents

• Differences in current densities• Differences in current densities across parasitic pnps produce gate bias voltage on M13 with g gtunable temperature coefficient

• Ratio of resistance of M12 and M9 cancels temperature dependence of output current

Current Source Performance• Current source provides near temperature independence over all

realistic temperaturesp

• Cascoded output mirroring provides higher output impedance for

162 58Output Current from Current Source vs Temperature

p g p g p pbiasing networks and tail current

162.54

162.56

162.58

current

162.48

162.5

162.52

ut C

urre

nt (

uA)

162 42

162.44

162.46

Out

pu

-20 0 20 40 60 80162.4

162.42

Temperature (C)

LNA Block Operation and MatchingLNA Block Operation and Matching

• Cascoded NFETs provide: ωt =gm/(Cgs + Cgd)p– Increased unilaterality for

input/output isolation

ωt gm/(Cgs Cgd)

– Reduced Miller mulitplied Cgd,which increases unity gain frequency ωt

• Input capacitor acts as dc blocking capacitor and is implemented off‐chip

Cascoding decreases Cgd increases ωt Decreases Noise Factor!

LNA Block Operation and MatchingLNA Block Operation and Matching

• L2 and L3 used to match input impedance to 50Ω with:

• Z = sL + 1/(sC ) + (g L )/C• Zin = sLs + 1/(sCgs) + (gmLs)/Cgs

• Drain inductor used to increase match bandwidth and filter output

• Width of NFETs were optimized for power constrained noise performance using:

• Wopt = 1/(3ωLCoxRs) Noise Figure = 2.8dBGain = 18.9dB

Single Input to Differential Output Converter Operation

• Composed of differential amplifier with LNA output p papplied to M1 and ac ground applied to M2

• A dc biasing network was designed to match the dc bias points of M1 and M2

• Cascoded mirror makes tail current source more ideal

Overall LNA System LayoutOverall LNA System LayoutCurrent Source

Diff AmpLayout Area: 0.2672 mm2

LNACurrent Source

Diff Amp

LNA

LNA

Gate Inductor Source Degenerative

Drain Inductor

Degenerative Inductor

Overall LNA System Performance0

S11 and S12 vs Frequency 4m

V) mA)

System Output & Current Source Variations vs Temperature

Overall LNA System Performance

30

-20

-10

ters

(dB

) S11S12

6-4 -2 0 2

4

t Var

iatio

n (m

e Var

iatio

n (m

VoltageC t c

-50

-40

-30

S Pa

ram

et

-12-10-8 -6

stem

Out

put

rrent

Sou

rce Current

Gain vs FrequencyNoise Figure and Minimum Noise Figure

820 840 860 880 900 920 940 960 980 100 -60

Frequency (MHz)

-40 -20 0 20 40 60 80Temperature (C)

Sys

Cur

3434.234.434.6

B)

Gain

4 5

4.55

4.6

4.65

re (d

B)

NFminNF

cc

3333.233.433.633.8

Gai

n (d

4.35

4.4

4.45

4.5

Noi

se F

igur

800 820 840 860 880 900 920 940 960 980 100 Frequency (MHz)

800 820 840 860 880 900 920 940 960 980 100

4.3

Frequency (MHz)

LNA System SpecificationsLNA System SpecificationsSpecification Value UnitsSpecification Value Units

Power Consumption 25.74 mWMax Gain in Passband (A ) 34 55 dBMax Gain in Passband (Av) 34.55 dBGain Ripple over Passband 0.08 dBMaximum System Noise Figure in Passband 4.366 dBy gMaximum S11 in Passband -11.61 dB-10dB Bandwidth for S11 65.0 MHzM i S i P b d 57 97 dBMaximum S12 in Passband -57.97 dB

Current Source Output Temperature Variation 150.82 nA

System Differential Output Voltage Temperature Variation 14.768 mV

O ll L A 0 2672 2Overall Layout Area 0.2672 mm2

DRC and LVS Clean Final Design yes n/a

Conclusions and Further ConsiderationsConclusions and Further Considerations

• CMOS LNA design meets all performance specs• LNA could find great use in cellular applications

• LNA system meets most 2σ process corner specs, but exceeds ±0 5dB gain ripple in the passband for a few corner sims±0.5dB gain ripple in the passband for a few corner sims

• Unimportant since VGAs in baseband circuitry can adjust for the small variation

• Did not consider an output match for our system• Acceptable since most wireless receiver LNAs drive on‐chip components such as a

FET gate in a mixer stage, making a 50Ω output match superfluous

AcknowledgementsAcknowledgementsWe would like to sincerely thank Professor Wentzloff and Danial Ehyaie for their patience,

guidance, and enthusiasm over the course of this project and this semester.