A High-Efficiency, Wide Workload Range, Digital Off-Time Modulation (DOTM) DC-DC Converter With Asynchronous Power Saving Technique

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 21, NO. 1, JANUARY 2013 67

A High-Efficiency, Wide Workload Range, DigitalOff-Time Modulation (DOTM) DC-DC ConverterWith Asynchronous Power Saving Technique

Po-Hsiang Lan, Tsung-Ju Yang, and Po-Chiun Huang, Member, IEEE

Abstract—Conventionally forwideworkload range applications,to keep good stability and high efficiency, a switching converterwith multi-mode operation is necessary. With the advanced dig-ital signal processing, this work presents an asynchronous digitalcontroller with dynamic power saving technique to achieve highpower efficiency. The regulation is based on the off-time modula-tion, in which an adaptive resolution adjustment is proposed for theextension toward light-loaded range. The DC-DC converter is fab-ricated in a 0.18- m CMOS process. The input voltage is from 2.7to 3.6 V and the regulated output is 1.8 V. The switching frequencyis from 44 kHz to 1.65 MHz and the maximum output ripple is 20mV with a 10- F capacitor and a 2.2- H inductor. The power ef-ficiency is higher than 91% for the workload range from 3 to 400mA.

Index Terms—DC-DC step-down converter, digital off-timemodulation (DOTM), pulse-frequency modulation (PFM),pulse-width modulation (PWM), switching mode power supply(SMPS).

I. INTRODUCTION

T HE wide-loaded and highly-efficient switching modepower supply (SMPS) has gained increased attention

in the field of power management [1]–[3]. It is worth notingthat the switching loss dominates the conduction loss as loaddemand is sufficiently low, which propels the developmentof dual-mode control scheme for the past decade [4], [5].However, a drawback of dual-mode converter is that withoutexplicit monitoring of output current, performance deteriora-tion is located between pulse-width modulation (PWM) andpulse-frequency modulation (PFM) as shown by the shadowarea in Fig. 1. Consequently, a tri-mode converter is configuredsubsequently to operate over the wide workload range of in-terest with efficient power conversion. To achieve the previousgoal, the dithering skip modulation (DSM) is introduced torandomly reduce the switching activity based on the load cur-rent [2], [6], depicted as the curve III in Fig. 1. However, eitherdual-mode or tri-mode converter inevitably adopts additionalsensor and monitor in response to the load demand, limiting

Manuscript received June 06, 2011; revised September 13, 2011; acceptedNovember 10, 2011. Date of publication December 20, 2011; date of currentversion December 19, 2012.The authors are with the Department of Electrical Engineering, National

Tsing Hua University, Hsinchu 300, Taiwan (e-mail: [email protected]).Color versions of one or more of the figures in this paper are available online

at http://ieeexplore.ieee.org.Digital Object Identifier 10.1109/TVLSI.2011.2177481

Fig. 1. Comparison of conversion efficiency among four modulation schemesover the wide workload range.

the efficacy of multi-mode controller in switching regulatorapplications.Taking into account the specified requirements discussed

above, another technique named as off-time modulation is usedby varying the clock frequency according to the computationload (curve IV). The amount of energy consumption only needsto be as high as required to satisfy the desired circuit perfor-mance. To further enhance the power efficiency, we proposetwo adaptive techniques based on the off-time modulationscheme in this work. The feasibility of digital off-time modu-lation (DOTM) with the proposed asynchronous power savingcontroller (APSC) and the adaptive resolution controller (ARC)has been demonstrated whose power conversion efficiency iscomparable to or higher than standard PFM operation overlight-loaded range.This paper is organized as follows. Section II illustrates

the architecture of proposed DOTM converter and the evo-lution of the proposed APSC. Section III depicts the circuitimplementation of each sub-block, including the windowedanalog-to-digital converter (ADC) and DOTM. Meanwhile,the limit cycle oscillation is also explored. Section IV analyzesthe linear model according to the mode it operates. The ex-perimental results are demonstrated in Section V, followed byconclusions in Section VI.

II. ARCHITECTURE OF PROPOSED CONVERTER

A. Operation Principle of Proposed DOTM Converter

Fig. 2 shows the block diagram of the proposed digital off-time modulation DC-DC step-down converter. The converteris composed of a power stage and a feedback controller. Thepower stage contains parallel MOSFETs consisting of powerpMOS and nMOS transistors, and an output filter consisting ofan inductor and a filtering capacitor. The regulated output iscompared with the reference voltage in a windowed ADC

1063-8210/$26.00 © 2011 IEEE

68 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 21, NO. 1, JANUARY 2013

Fig. 2. Block diagram of the proposed digitally-controlled off-time modulationDC-DC step-down converter.

for encoding the digital error stream, , followed by a dig-ital signal processor (DSP) with the computation of the propor-tional-integral derivative (PID) algorithm. The output of dig-ital processor, will be delivered through a DOTM to definethe switching period, and subsequently trigger the leadingedge of next conversion phase in an on-time generator to definethe on-time duration . The internal system clock generatedby the DOTM is fed back into the analog power train to con-trol the on-time and off-time duration of power MOSFETs, thusachieving a negative feedback to regulate the output voltage.Meanwhile, this internal clock is also used to provide the timingrequirements the DSP, ADC, and APSC must comply with. TheAPSC governs the windowed ADC and zero current detector(ZCD) after finishing their own duties, so as to further improvethe efficiency over the light-loaded range.

B. Asynchronous Power Saving Controller (APSC)

As the word asynchronous implies that the sub-blocks are notgoverned by a clock circuit or global clock signal, but insteadneed only wait for the signals that indicate completion of in-structions and operations. To this end, the windowed ADC andZCD are deactivated after finishing their duties in each cycleuntil the next clock leading edge is triggered, which is reacti-vated by the system clock as shown in Fig. 3. The chronogramof the windowed ADC and the ZCD, together with the asyn-chronous signals are depicted on the bottom side of Fig. 3. Inwindowed ADC, the comparison between regulated output andreference voltage is executed. The power penalty is diminishedby employing the proposed APSC after evaluating the digitalerror stream. Similarly, the APSC restricts the static current ofcomparator in the ZCD as inductor current ramps to zero beforethe end of each clock cycle. The power reduction of these twopower-hungry sub-blocks goes up by a factor of asindicated in Fig. 3, where and correspondingly denotes thedeactivation duration and switching period. Based on the op-eration of the off-time modulation, the lighter the load currentdrawn by the output, the larger the power reduction factor willbe. As a result, the power conversion efficiency is significantlyimproved over the light-load range.Fig. 4 depicts the power consumption estimation under

different load condition and the efficacy of the proposed APSC.

Fig. 3. Flow chart of APSC and the associated evolution of windowed ADCand zero current detector.

Fig. 4. Estimated power reduction on the feedback controller under differentloads with the proposed APSC. At top there is a comparison of power efficiencyamong three different topologies.

Simulation reveals the relatively obvious difference towardlighter load demand and indicates that there is 51% powersaving compared to the conventional fixed-frequency PWMmodulation. The minimum total power consumption is 0.42mW when load current is 3 mA and the power efficiency ishigher than 91% by adopting the proposed DOTM and APSC.

LAN et al.: HIGH-EFFICIENCY, WIDE WORKLOAD RANGE, DOTM DC-DC CONVERTER 69

III. CIRCUIT IMPLEMENTATION

A. Windowed ADC With Self-Sampling Characterization

ADC is the first block in the digitally-controlled DC-DC buckconverter proceeding with the regulated output. The regulatedoutput is in the vicinity of reference voltage when the system isin the steady state. Therefore, an effective windowed ADC withthe characterization of self-sampling, as depicted in Fig. 5(a), isdeveloped in order to reduce the hardware cost and increase re-liability. is used to control the propagation delay of mea-surement delay-line after comparing the regulated output withthe reference voltage by passing through a stage. Mean-while, conducts the reference delay-line to generate thesampling clock. The sampling clock will trigger the data reg-isters to collect the difference information between regulatedoutput and reference voltage in a digital stream of thermometercode, , as shown in Fig. 5(c). Meanwhile, the sampling clockinforms the APSC whether the evaluation is done or not. Oncethe digital error stream is produced by the self-sampling delayline, all the delay units switches into sleep mode instead, re-ducing the standby current consumption significantly. Simula-tion result shows that the current dissipation is about 10 Awhen the operating switching frequency is 44 kHz.Fig. 5(b) shows the delay unit used in the delay line of the

windowed ADC. As we know, the propagation delay, israther susceptible to process technology and temperature vari-ation. It incurs additional calibration hardware cost and powerpenalty in order to precisely control the ADC resolution [7],which poses the conflicting requirements for a power-efficientdesign with process-insensitive characteristic. In the windowedADC, two identical differential pairs are used to operate it incurrent starved mode to avoid a variety of the ambient varia-tions. Additionally, the reference delay-line inherently trimsthe sampling clock required in the delay-line due to the sameenvironmental variability, thereby making breakthroughs thatenable a more effective power reduction.Analogous to conventional ADC, resolution is one of the

most important parameters being aimed at area minimization.The relation between the resolution and number of delay unitsis given by

(1)

where represents the desired ADC resolution.However, a drawback of self-sampling is that with relativelymonitoring the voltage difference, the circuit performs limitedviewing window in the vicinity of the reference voltage asshown in Fig. 5(d). This characteristic significantly deterioratesthe dynamic performance. To achieve low power operationwhile retaining large viewing window, a nonuniform quantizerproposed in [8] can be employed for the accomplishment of thedesired demand.

B. Digital Off-Time Modulator

In the system where a power converter and a digital controllerform a feedback loop, the digital off-time modulator serves thepurpose of a digital-to-analog converter (DAC). The discrete

Fig. 5. (a) Circuit block diagram of the windowed ADC. (b) The delay unitused in the delay-line of the windowed ADC. (c) The evolution of the windowedADC. (d) The corresponding nonuniform transfer curve of the self-samplingdelay-line ADC.

set of duty ratios and achievable output voltages correspond-ingly is dependent on the modulation resolution. Namely, thereis an undesired oscillation occurs if the resolution is not suffi-ciently high. Fig. 6(a) depicts the 10-bit digital-input off-timemodulator with a hybrid structure and an ARC. It is one of the


Fig. 6. (a) Simplified block diagram of digital off-time modulation. (b) Theschematic of the 4-bit current-starved delay-line with adaptive resolution con-troller and the evolution of the digital modulator.

solutions being targeted at constructing a complete, robust dig-ital block capable of operating at a high switching frequencyand a small silicon area, low power consumption and less com-plexity comparable to the counter based modulator. As opposedto counter-based modulator, only the first 6 bits, aresegmented out of the to perform the comparison, while theremaining last 4 bits characterizes which delay cell is multi-plexed. Only when 10 bits are all in a match will the off-timeduration be determined and the pulse given to deliver to-ward the on-time generator. The on-time duration producedby a feedforward delay-line is preferable over the range in whichthe total losses are minimized, which will be analyzed later. Thesystem clock is therefore generated and fed back into the analogpower train, DSP, ADC, and APSC. Furthermore, the ARC isutilized for the increase of output workload range based on thecode segmentation , as shown in Table I. More details willbe elaborated in the following subsection.Fig. 6(b) shows the schematic of the proposed ARC, which

is composed of four current sources with associated switchescontrolled by the control bits, from DSP. It conducts thedelay-line of the digital modulator in the current-starved mode

TABLE ICODE SEGMENTATION OF THE ARC

for the insusceptibility to the technology variations. The chrono-gram of the digital modulator is illustrated on the bottom ofFig. 6(b). is set to high at the starting of each period. Itis reset until the pulse is propagated to a match with ,which is constructed by six most significant bits in the counterand four least significant bits in the delay line. In this case, code39 is chosen when counting number is 000_010 and the eighthdelay cell, is multiplexed.

C. Resolution of the Digital Modulator ( )

Limit cycle oscillation is the major challenge when digitalcontroller is implemented in the converters [4], [7], [9], [10].As opposed to conventional analog solution, the resolution indigital control loop has a finite quantized value resulting fromthe quantizers—the ADC and digital pulse width modulator(DPWM). As the system fails to regulate the output to theADC zero error bin based on the command conducted bythe DPWM, the perpetual undesirable oscillation within itsneighborhood is generated as the output attempts to reach thereference voltage [11]. Therefore, several techniques such asdelay-line based [12], counter-based, and hybrid DPWM [7],[13] have been proposed to increase the required resolution atthe cost of exponential hardware penalty. Other cost-efficientmethods like dithering [11] and DPWM [9], [14] makebreakthroughs that improve effective DPWM resolution byrandomizing the duty cycle. These approaches, however, su-perimpose significant tradeoff in switching supplies, such thatthe output suffers from the larger voltage ripple that negatesthe original intention on the regulation. For the sake of keepingacceptable high resolution, simultaneously minimizing theoutput ripple, digital off-time modulation provides one possiblesolution being aimed at performance maximization [15].The steady-state limit cycles in DOTM converter is presented

in this section. In mixed-signal system, the solid assurance ofno-limit-cycle oscillation follows from the fact that the reso-lution of the DPWM is smaller than that of the ADC. There-fore, there is a potential advantage in the off-time modulationcontrol mechanism over the light-loaded range of interest. Bysolving the resolution of the digital off-time modulator,is duty-dependent and given by

(2)

where duty ratio is defined as

(3)

and denotes the supply voltage and is the unit delay inthe delay line of the DOTM as shown in Fig. 6(b). Inspection


Fig. 7. Off-time modulation resolution in response to the duty ratio with dif-ferent propagation delay time.

of (2) reveals that the resolution is quadratically proportional tothe duty ratio, implying that such scheme possesses the inherentsuperiority of high resolution over light-loaded range due to thesmall duty ratio. Fig. 7 shows four parabolic curves with fourdifferent propagation delay in the DOTM. The control bits ,shown in 6(b) is employed to adjust the unit propagation delay.When the propagation delay is 3 ns, the maximum accept-able duty ratio is 0.88, allowing the acceptable digital stream

to range from 15 to 1023 when a 10-bit DOTM is imple-mented. Consequently, the longest switching period is 3.4 s,which implies the minimum load demand is 20 mA. On theother hand, the duty ratio is strictly restricted when the propaga-tion delay is 22.19 ns . But the maximum allowableswitching period is greatly extended, which is given by

s (4)

so the minimum load demand is subsequently widen to 3 mA.With the aforementioned discussion, the proposed ARC is in-

troduced to adaptively control the delay time of the digital mod-ulator for being capable of operating over a wider load range forthe converter without the limit cycling. In other words, the dutyratio is segmented according to the digital code as listed inTable I. Take 1023 for example, instead of choosing 3 ns as thepropagation delay , choosing 22.19 ns for a longer switchingperiod and a wider load range is strictly preferred. As a result,ARC exerts its influence on the switching period and minimumload demand as shown in Fig. 8. In this design, four segmentsare based on the digital code .However, the switching period is not continuous between

the codes, since the control bits are switching, making thepiecewise linear function discontinuous. This discontinuity willresult in the missing pulse width, which exercises a negativeinfluence over the corresponding resolution. will bemuch larger than that of the windowed ADC, and therefore pro-vides little assurance to guarantee a no-limit-cycle oscillation.As a result, it is strongly recommended to employ a digital back-ground calibrator to circumvent the output from limit cycle os-cillation.

Fig. 8. Illustration of the influence exerted by the ARC on the switching periodand load demand.

Fig. 9. Block diagram of the proposed digital background calibration and itsevolution when and are and , respectively.

D. Digital Background Calibration

The block diagram of the digital calibrator is depicted inFig. 9 which contains two independent digital off-time mod-ulators ( and ) and a D flip-flop. Thecalibrator is integrated with the field-programmable gate array(FPGA) XC2S50E, which outputs , , ,and for the calibration.Initially, the codes are given on the positions the ARC in-

tends to switch. Set , ,, and , respectively. By comparing the

phase delay between and in the D flip-flop,decreases by one every clock cycle when the detection

is logic high. The chronogram of the digital background cali-bration is shown on the bottom of Fig. 9. The signal, isdetermined by self-sampling with . The de-tection is deactivated until is set to logic low. Therefore,the discontinuity depicted in Fig. 8 is eliminated. Meanwhile,an additional unit on is required to satisfy monotonicity.Take Fig. 9 for example, 67 is chosen instead, guaranteeing theoff-time duration generated by is long enough.


Fig. 10. Schematic of the zero current detector and dead-time controller. Theassociated chronogram is plotted for more details.

E. Zero Current Detector, ZCD

The ZCD for a DC-DC converter is employed for allowingcurrent to pass in one direction in a synchronous rectifier. Theinductor current ramps to zero before the end of each clock cycleas the load current decreases to a certain extent, implying thatthe energy required by the output is light enough to be trans-ferred within a time frame shorter than the whole computa-tion period. Fig. 10 shows the schematic and evolution of thezero current detector and dead-time controller when operatingin DCM. The shadowed part represents themain difference fromthe CCM. The output of the comparator, changes from highto low when the inductor current intersects with zero, forcingthe signal low to turn off the power MOSFETs. Simultane-ously, the is then activated to connect the gate terminal ofthe tail current to input supply instead. As a result, the staticcurrent is restricted and therefore consumes no power. Addition-ally, the activation time varies with the switching period overthe light workload range. Therefore, combined the APSC withthe off-time modulation, the power consumption in the ZCD isreduced significantly.

F. Selection of the Optimal On-Time Duration

The non-idealities of the circuit components in a buck con-verter are not taken account yet. Power loss due to the feedbackcontroller becomes insignificant after utilizing proposed APSCfor low power applications. Both static and dynamic powerlosses occur in any switching regulator. Static power lossesinclude the conduction losses in the wires or PCB traces, aswell as in the series resistance in the switches and inductor.

Fig. 11. Relationship between total losses and on-time duration. The optimalregion ranges between 300 and 400 ns.

Dynamic power losses occur as a result of switching, such asthe charging/discharging of the gate-oxide capacitance of theMOSFETs. The on-time duration is subsequently determinedbased on the total losses on the power MOSFETs and given by[16], [17]

(5)

where

(6)

and

(7)

and , and denote the on-resistance of powerp/nMOS, gate width of power p/nMOS and gate capacitanceper unit width, respectively. Fig. 11 depicts the summation ofthe conduction loss, and the switching loss, in response tothe on-time duration with different load demand. This has cometo the opposite relationship between conduction losses andswitching losses in response to the on-time duration. Namely,the switching loss is dominant over the region in which on-timeduration is short, while conduction loss governs the remainingregion due to larger inductor current ripple, . In this design,the on-time duration is selected as 330 ns for the optimization.

IV. LINEAR MODEL OF THE PROPOSED DOTM CONVERTER

Fig. 12 depicts the linear model of the proposed digitally-con-trolled off-timemodulation DC-DC step-down converter, whichis composed of four parts: equivalent buck converter, ADC,digital off-time modulator, and digital signal compensator.The equivalent buck converter, can be derived by thestate-space description, which is a mathematical model of a


Fig. 12. Linear model of the proposed digitally-controlled off-time modulationDC-DC step-down converter.

physical system as a set of input, output, and state variables re-lated by first-order differential equations. Either the windowedADC or the DOTM contains three parameters, respectively.The first term is their associated equivalent gains, and

in (2), which is a frequency-dependent parameter.The second term is the quantization effect resulting from thequantizers, and [11]. The last term is the delaycaused by the conversion time and sample-and-hold effect [18],correspondingly. Therefore, the open-loop transfer function isarranged by

(8)

Owing to the demand of wide workload range, the amount ofenergy required by the load is small enough to be transferredin a time smaller than whole computation period in some cases.Therefore, the linear model of equivalent buck converter,is divided by continuous conduction mode (CCM) and discon-tinuous conduction mode (DCM). According to the mode thesystem is operating, the digital compensator is required to ad-just properly to guarantee the steadiness.

A. Continuous Conduction Mode

First, CCM is taken into consideration. In the off-time mod-ulation scheme, the system clock generated by the DOTM isnearly fixed. Consequently, the traditional CCM model is usedto analyze the linear behavior. Due to the complex conjugatepoles produced by the power stage, the control-to-output re-sponse can be derived with ESR effect and given by

(9)

After combining with the digital interfaces (the windowedADC and DOTM), the bode plots with and without the com-pensator, are shown in Fig. 13. Inspection of these twoplots tells that the phase margin is 21.3 degree without the com-pensator , which is not a safety margin that ensures properoperation of a closed-loop system. Consequently, an extra com-pensator is required to retrieve the phase delay. This is a com-pensator consisting of one pole and two zeros. The DC gain isimproved by the introduced DC pole, while the complex conju-gate poles are canceled by the introduced two complex conju-gate zeros. The unity-gain bandwidth is 155 kHz and the phase

Fig. 13. Bode plots with (solid line) and without (dashed line) the compensator.

margin is 83.1 degree after compensation. Subsequently, the co-efficients in the digital compensator are computed by the bi-linear transformation and given by [19]–[21]

(10)

B. Discontinuous Conduction Mode

On the contrary, the two-pole control-to-output frequency re-sponse in CCM is reduced to a single-pole response in DCM(filtering capacitor in parallel with the load) and given by

(11)

where and are given in [22]. The system exhibits a singlepole , frequency-dependent characteristic. Accordingly, alook up table is constructed based on the frequency the system isoperating as shown in Table II, where is the system switchingfrequency, and is loop bandwidth after the compensation. Asopposed to the PID algorithm in CCM, PI compensator is appro-priate to provide a stable compensation in DCM, and is thereforegiven by

(12)

where the integral coefficient is designed to be one-eighth of theproportional coefficient for reducing the variables.Fig. 14 shows the root locus in s-domain under different load

demand and operating switching frequency. By selecting a pointalong the root locus that coincides with a desired damping ratio,0.707 the desired parameters, can be calculated and imple-mented in the PI compensator. Take 64.65 mA load demand forexample, is chosen as 22.44. After implementing in the DSP,


TABLE IILOOKUP TABLE OF THE DIGITAL COMPENSATOR AS OPERATING IN DCM

Fig. 14. Root locus in s-domain under different load demand and operatingfrequency.

five bits is employed to represent the decimal fraction, and there-fore rounds down to 22.4375.

Fig. 15. Micrograph of the chip for fabrication and the block diagram of thedigitally-controlled buck converter for the measurement.

V. EXPERIMENTAL RESULTS

This work has been fabricated in a 0.18- m CMOS tech-nology. For the purpose of system reconfigurable capability,the digital signal process was independently implemented bya FPGA as shown in Fig. 15. The micrograph of the chip forfabrication is shown as well. The total area is about 1.34 mm1.34 mm, out of which the feedback controller occupies an areaof 0.16 mm . Three power sources are employed to supply theenergy for the associated circuity independently, thus makingit convenient to calculate the power dissipation of each block.The converter is supplied with input voltage from 2.7 to 3.6 Vand composed of an external passive 2.2- H power inductor andan external 10- F multi-layer ceramic capacitor. The maximumoutput ripple is about 20 mV.

A. Static and Dynamic Performance

The static performance is shown on the bottom side in Fig. 16.The load demands are 400 and 3 mA, respectively. The on-timeduration is 330 ns for each case, while the switching periods are600 ns and 22.64 s, correspondingly. The maximum outputripple is about 20 mV. The load regulation performance with397 mA load step and 3.6 V supply voltage is shown on thetop side of Fig. 16. The maximum output overshoot voltage isabout 160 mV, and the transient recovery time is less than 190s. Inspection of this result tells that when load changes from400 to 3 mA, it is hard to predict the digital stream withoutadditional auxiliary load sensor, making the regulation simplyrely on the PI compensator calculated in Table II. Conversely,the digital stream that the system is about to modulate thepower stage in heavy load (400 mA) is predetermined due to theindependence from the load condition, and is therefore of betterregulating behavior.

B. Digital Background Calibration

Demonstration of the digital background calibration is givenin Fig. 17. With the aids of the ARC and digital background


Fig. 16. Load regulation from DCM (3 mA) to CCM (400 mA) and vice versaand its corresponding static performance. Regulated output is 1.8 V and the loaddemands are 400 and 3 mA, respectively.

Fig. 17. Extended performance after adopting the ARC and the digital back-ground calibration.

calibrator, the digital code is reorganized according to themeasurement results. The horizontal axis represents the codeafter calibration, while the vertical axis is the correspondingswitching period and load demand. The piecewise linear func-tion is monotonically connected when the calibration code isreserved in the FPGA in advance.Fig. 18 shows the limit cycle oscillation with and without the

digital background calibration. For the system without the con-cern of limit cycles, oscillation arises in the condition the ARCintends to switch. In this design, the codes and 256are used to test the oscillating problem. When the calibration isdeactivated, the corresponding resolution, is about 170mV when being supplied with 3.3 V input voltage. It is far more

Fig. 18. Verification of limit cycle oscillations when the digital backgroundcalibrator is activated and deactivated.

Fig. 19. Comparison of the conversion efficiency among different implemen-tation techniques. It is supplied with 3.3 V input voltage and 1.8 V regulatedoutput in this work.

insufficient compared to that of the windowed ADC, making theconverter regulate unsteadily. On the contrary, the output ripplewith digital calibrator is effectively reduced to about one-sixthcompared to that of the converter without the digital calibrator.

C. Power Conversion Efficiency

The static state power conversion efficiency of the converteris shown in Fig. 19 as operating with 3.3 V input voltage and1.8 V regulated output. In this work, a high efficiency over awide load range is achieved by utilizing the proposed APSC


TABLE IIICOMPARISON TABLE WITH PRIOR ARTS

and off-timemodulator. The maximum andminimum efficiencyis about 95 and 91% with 40 and 400 mA load demand, re-spectively. With the consideration of power consumption of theFPGA, the efficiency over the light-loaded range is slightly de-graded since the clock speed of the processor is governed bythe system clock of the DOTM. Table III shows the comparisontable with prior arts. The digitally-controlled DC-DC converteris completed and compared favorably with other strategies interms of efficiency, workload range of interest and regulation.

VI. CONCLUSION

This paper presents a digitally-controlled switching con-verter that integrates several advanced techniques to achievehigh conversion efficiency over a wide load range. Withoutthe multi-mode methodology to reduce the switching loss,an off-time modulation scheme is employed instead. Anasynchronous power saving controller helps to cut down thequiescent current further and an adaptive resolution controllerextends the workable range to light loading condition. All thefunctions have been integrated in the prototype chip and havebeen verified successfully. For a workload range from 3 to 400mA, the power efficiency can be higher than 91%. This workprovides one possible solution to construct a high-efficient, ro-bust point-of-load switching converter without the complicatedsensing circuitry.

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Po-Hsiang Lan received the B.S. degree from theDepartment of Electrical Engineering, NationalTsing Hua University, Hsinchu, Taiwan, in 2006,where he is currently pursuing the Ph.D. degree inelectrical engineering.His research interests include the design skills

of process-insensitive and low power controllerfor DC-DC converter, digital control algorithmand design methodology, on-chip inductor forswitching mode power supplies, and thermal-awarecurrent-sharing power management for 3D-IC

applications.

Tsung-Ju Yang received the B.S. degree from theDepartment of Electrical Engineering, Chung YuanChristian University, Taoyuan, Taiwan, in 2008and the M.S. degree from the Department of Elec-trical Engineering, National Tsing Hua University,Hsinchu, Taiwan, in 2011.He joined the Taiwan Semiconductor Manufac-

turing Company, Hsinchu, Taiwan, in 2011. He isnow an Engineer of the Library and IP ProgramDepartment of the Design Methodology Division.

Po-Chiun Huang (M’01) received the B.S. andPh.D. degrees in electrical engineering from Na-tional Central University, Hsinchu, Taiwan, in 1992and 1998, respectively.During the summers of 1992 and 1996, he was

an Intern with the Computer and CommunicationResearch Laboratory, ITRI, and Lucent Technology,during which time he investigated design techniquesfor optical and RF communication systems. From2000 to 2002, he was with MediaTek Inc., where hewas involved with chipset design for optical storage

products. In 2002, he joined National Tsing Hua University, Hsinchu, Taiwan,where he is currently an Associate Professor. His research interests includemixed-signal circuit designs for communication and power-managementapplications.

Documents

A High-Efficiency, Wide Workload Range, Digital Off-Time Modulation (DOTM) DC-DC Converter With Asynchronous Power Saving Technique