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A fully digital low-power wide-speed-range BPSK demodulatorHan-Hua Liua, Zhao-Hui Wua, Bin Lia & Ming-Jian Zhaoa

a School of Electronic and Information Engineering, South ChinaUniversity of Technology, Guangzhou 510640, P.R. ChinaPublished online: 03 Mar 2014.

To cite this article: Han-Hua Liu, Zhao-Hui Wu, Bin Li & Ming-Jian Zhao (2014) A fully digital low-power wide-speed-range BPSK demodulator, International Journal of Electronics Letters, 2:3,158-165, DOI: 10.1080/21681724.2014.894132

To link to this article: http://dx.doi.org/10.1080/21681724.2014.894132

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A fully digital low-power wide-speed-range BPSK demodulator

Han-Hua Liu, Zhao-Hui Wu, Bin Li* and Ming-Jian Zhao

School of Electronic and Information Engineering, South China University of Technology,Guangzhou 510640, P.R. China

(Received 23 January 2013; accepted 25 January 2014)

A novel binary phase-shift keying (BPSK) demodulator architecture is presented. By usingfully digital and trigger receiving method, the proposed demodulator can work properly ata wide speed range and hence can be applied in different applications such as wirelesscommunications, biological implants and portable facilities, etc. The proposed demodu-lator was implemented by a 0.35-μm complementary metal-oxide-semiconductor (CMOS)process and the chip area is about 0.5 mm2. Measurement results reveal that the proposeddemodulator can successfully demodulate the 100 MHz/10 Mbps BPSK signal which isthe highest performance. While when it is used to demodulate the lowest speed BPSKsignal of 10 MHz/1.0 Mbps, the power consumption is only 319 μw, and the bit error rate(BER) is less than the low test bond (10–9). Measurement results also show that thedesigned demodulator can work at 100% data-rate-to-carrier-frequency (DRCF) ratio withthe frequency up to 25 MHz.

Keywords: binary phase-shift keying (BPSK); fully digital demodulator; wide speedrange demodulator; low-power demodulator; low bit error rate demodulator; trigger-receiving demodulator

1. Introduction

Wireless power deliveries are widely used in biological implants. The system is usuallycomposed of the external transmitter and the implanted receiver. The power deliveredfrom the external transmitter is received by the implanted receiver wirelessly and becomesthe power supply of the implanted devices (Hu & Sawan, 2005). At same time, somecontrolling command data are also transmitted to the implants to control the activities ofthe implants through some kinds of low bit-rate short distance communications, which arealso widely used in portable facilities and wireless communications.

Since the power is delivered wirelessly, the efficiency is limited. Therefore, the powerconsumption of the implanted receivers becomes a crucial factor in these transceiversystems design.

As one kind of digital modulations, the binary phase-shift keying (BPSK) is widely used inwireless systems, such as 802.15.4, global positioning system (GPS) and medical telemetry(Yao, Gao, &Niu, 2013). And since it has fixed signal amplitude and constant carrier frequency,it is more suitable to be applied in the implanted wireless data communications than amplitude-shift keying (ASK) or frequency-shift keying (FSK) (Ghovanloo & Najafi, 2004).

The technology of existing typical BPSK demodulators contains Costas loop (Hu &Sawan, 2005), phase-locked loop (PLL) (Luo & Sonkusale, 2008; Xu, Luo & Sonkusale,2009), nonlinear BPSK demodulation (Zhu & Xu, 2011) and other alternative approaches

*Corresponding author. Email: phlibin@scut.edu.cn

International Journal of Electronics Letters, 2014Vol. 2, No. 3, 158–165, http://dx.doi.org/10.1080/21681724.2014.894132

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(Moon, Yu & Lee, 2009). The Costas loop reported in Hu and Sawan (2005) has a goodperformance and high data transmission rate. One of the drawbacks of this Costas loop isthat it needs a multiplier or Exclusive OR (XOR) type of phase detector (PD) to track thephases of the signals, which will limit the capability of acquisition and tracking range.Other demodulators based on PLL reported in Luo and Sonkusale (2008) and Xu et al.(2009) use digital PLL to obtain low power and use the multilevel load-shift-keying(LSK) to improve the data transmission rate. Nevertheless, the data-transmission rate stillcannot meet some application requirements of high speed and these demodulators havethe same drawback that when the carrier frequency is changed or higher bit rate is needed,the whole circuit should be redesigned.

In recent years, some BPSK demodulators without PLL were studied (Asgarian &Sodagar, 2009a, 2009b, 2010; Nabovati & Maymandi-Nejad, 2010; Nabovatia,Mirbozorgi, Mohammad, Maymandi-Nejad, & Nabovati, 2011; Wang, Yang, & Chiueh,2013). Since fully digital solutions were used, these demodulators can obtain low powerand 100% data-rate-to-carrier-frequency (DRCF) ratio up to a data transmission rate of 16Mbps. However, only simulation results for the demodulators with 100% DRCF ratio andhigh data transmission rate were shown. More experiments are needed to show theeffectiveness of these kinds of demodulators.

This paper presents a new, fully digital solution for the BPSK demodulator with lowpower, simple structure, wide speed range and low bit error rate (BER) performance.

2. Theoretical analysis

The BPSK signal which is received by antenna can be expressed as,

Sbpsk tð Þ ¼ Ab tð Þ cosωct: (1)

where A is the amplitude of received BPSK signal, ωc is the angular frequency of carrier,bðtÞ is the digital base band signal and can be written as,

b tð Þ ¼X1

n¼�1an μ t � nτð Þ � μ t � nþ 1ð Þτ½ �f g: (2)

where τ is the period of the base band signal, {an} is the binary data sequence of {±1}transmitted at a rate of 1=τ bps, μðtÞ is the unit step function, and n is the serial number ofthe base band digital data. Therefore, the range of SbpskðtÞ will be from ‘−A’ to ‘A’.

The demodulation theoretical principle is illustrated in Figure 1. The core process ofthe demodulation is to detect the place where the phase of BPSK signal is changed.

Shifting SbpskðtÞ by half of the carrier’s period Δt ¼ π=ωc, the delayed BPSK signalcan be expressed as

Z –

Δ t ∑Sbpsk (t) Sbpsk (t – Δt) S(t)

+

+

Figure 1. Diagram of the demodulation theory.

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Sbpsk t � Δtð Þ ¼ Ab t � Δtð Þ cos ωct � πð Þ: (3)

Substituting Equation (2) into Equation (3), the delayed BPSK signal becomes as

Sbpsk t � Δtð Þ ¼ �A cos ωctð ÞX1

n¼�1an�1 μ t � nτð Þ � μ t � nτ � τ=2ð Þ½ �f

þan μ t � nτ � τ=2ð Þ � μ t � nτ � τð Þ½ �g: ð4Þ

Adding SbpskðtÞ and Sbpskðt � ΔtÞ will lead to the result of ‘2A’ or ‘−2A’ where there is aphase change, or the result of ‘0’where there is no phase change, the result can be expressed as

S tð Þ ¼ A cos ωctð ÞX1

n¼�1an � an�1ð Þ μ t � nτð Þ � μ t � nτ � τ=2ð Þ½ �: (5)

SðtÞ is a periodic narrow positive or negative pulse signal with the pulse widthΔt ¼ τ=2 and the period T ¼ nτ. For convenience, taking absolute value of SðtÞ, then itcould be expressed as

S tð Þj j ¼ 2AX1

n¼�1an � an�1ð Þ μ t � nτð Þ � μ t � nτ � τ=2ð Þ½ �: (6)

Now, the rising edge of SðtÞj j shows the position where there is a phase change in theBPSK signal. What we should do is to probe the narrow pulse edge and flipping electriclevel to get base band signal.

3. System architecture

3.1. Overall structure

The BPSK demodulator reported here is one part of an implantable wireless neural-signalrecording system. The block diagram of the implanted recording system is shown inFigure 2. Microelectrode array (MEA) gets extracellular neural signal and the front-endcircuits which contain low-noise amplifier, filter and analog-to-digital converter (ADC).After the digital mux and the encoder, the signals are sent outside of implant through thetransmitter. On the other hand, some command signals such as channel selection informa-tion are transmitted into the implant through the inductive wireless power delivery path.Power recovery module in Figure 2 recovers the wireless incoming energy and supplypower for other implant modules, while the receiver module in Figure 2 is used to recoverthe wireless command signals. The demodulator in the receiver is the focus of this work.

3.2. Demodulator architecture

The proposed demodulator shown in Figure 3 is mainly constructed by four D-flip-flops,named as DFF_1, DFF_2, DFF_3 and DFF_4. The wirelessly received modulated BPSKsignal is firstly shaped by a buffer and is sent to the D-port of DFF_1. By controlling the2× carrier frequency clock, DFF_1 will produce a digital BPSK signal S1 which has acertain phase shift related to the original received BPSK signal. With the same 2× carrier

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frequency clock, after S1 goes through DFF_2, another digital BPSK signal S2 with aphase shift of π related to S1 will be produced. Then, the two BPSK signals S1 and S2 areboth put to an exclusive-NOR (XNOR) to detect the phase differences between them. Ifthere is no phase change in the modulated BPSK signal, the phases of S1 and S2 will keepreversal all the time. In this case, the output of XNOR will not change, the DFF_4 willhave no clock, and thus the output data will keep unchangeable. Once there is a phasechange in the modulated BPSK signal, the phases of S1 and S2 will be the same, while theoutput of the XNOR will change and trigger the DFF_4. In this way, these phase-changesinformation in the modulated BPSK signal will be extracted and converted to the sent datainformation by trigger-receiving mode.

In some wireless communication applications, for improving the robust of the system,the differential coding is used for the data transmission. In this case, differential phase-shift keying (DPSK) modulation which combines with differential coding and BPSKmodulation will be used. However, the demodulation process of the DPSK is same as thatof the BPSK. Therefore, the DPSK demodulator will not be described in this paper.

CLR

DFF_1

D

DFF_2

buffer

D SET SET

2X Carrier Freq.Clock

BPSKSignal

SET

CLR

D

DFF_3

D

DFF_4

XNORS3

S1S2

S4

Data

CLR

SET

CLR

Figure 3. The proposed demodulator architecture.

Front-End

LNA Filter ADC

DigitalMux

EncoderBPSK

TransmitterAntenna_t

ChannelSelector

ReceiverPower

recovery

Microelectrode array

Inductive network

Figure 2. Diagram of the implantable neural-signal detector.

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4. Implementation and experiment

The new type of BPSK demodulator was realised successfully by Global Foundries 0.35-μm complementary metal-oxide-semiconductor (CMOS) process with the supply of 3.3 V.The microphotograph of the chip is shown in Figure 4. The core area of the chip is about0.5 mm2.

Ameasurement environment setup to verify the designed demodulator is shown in Figure 5.Figure 5(a) shows the testing board with the designed chip bonded on the board by a chip-on-board package method. Figure 5(b) shows the measurement setup for testing the demodulatorfunctionality. Figure 5(c) shows the measurement setup for testing the BER of the demodulator.The sent base band signal is provided by BERT scope when testing the BER and by fieldprogrammable gate array (FPGA)when testing the functionality. The BPSKmodulating processis accomplished by the FPGA-development kit. The sent data and demodulated signals arerecorded by a Tektronix DPO 2012 digital phosphor oscilloscope and shown in Figures 6 and 7.It is seen from Figure 6 that the designed demodulator can work well at a carrier frequency of100MHz and a transmission data rate of 10Mbps (100MHz/10Mbps). Figure 7 shows that thisdemodulator can also work at 100%DRCF ratio and high data rate up to 25Mbps if the BER isnot required to be so low.

Dff_1 Dff_2 XNOR

Dff_3 Dff_4

Figure 4. Microphotograph of the proposed BPSK demodulator.

(a)

(b) (c)

CarrierGenerator

BPSKModulator

ProposedDemodulator

BasebandGenerator

Oscilloscope

BERT scopeBPSK

ModulatorProposed

Demodulator

CarrierGenerator

Figure 5. Measurement environment of the designed BPSK demodulator; (a) testing board, (b) fortesting the functionality, (c) for testing the BER.

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The BER measurement results of the designed BPSK demodulator with the test periodof 30 min are shown in Figure 8. Figure 8(a) shows that when the demodulator worked at10 MHz carrier frequency and 1.0 Mbps data rate, a good BER performance was obtainedwith a near-errorless BER of less than 10–9, which is the lowest bound of the testinfrastructure. Figure 8(b) and 8(c) shows that when the demodulator worked at 100%DRCF ratio, the BER performances became worse even when the data rate was low to128 Kbps. Performances of the proposed demodulator and comparison with other reportedBPSK demodulators are shown in Table 1. It is seen from Table 1 that relatively lowpower of 319 μw and ultra-low BER are realised under a higher supply voltage of 3.3 Vwhen it is used in the typical demodulation of 10 MHz carrier frequency and 1.0 Mbpsdate rate.

0.1μs

DemodulatedData

Sent Data

Figure 6. Measured waveforms of the proposed BPSK demodulator (100 MHz/10 Mbps).

DemodulatedData

Sent Data

0.04µs

Figure 7. Measured waveforms of the proposed BPSK demodulator (25 MHz/25 Mbps).

(a) (b) (c)

Figure 8. BER test results of the proposed demodulator when it works at (a) 10 MHz/1.0 Mbps,(b) 128 KHz/128 Kbps, (c) 1.0 MHz/1.0 Mbps.

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Table

1.Perform

ancescomparisonwith

repo

rted

BPSK

demod

ulators.

Ref

HuandSaw

an(200

5)Luo

andSon

kusale(200

8)Asgarianetal.(20

10)

Wanget

al.(201

3)

Nabov

atia

and

Maymandi-N

ejad

(201

0)Thiswork

Tech.

0.18

μm0.5μm

0.18

μm0.18

μm0.18

μm0.35

μmSup

ply

1.8V

3.3V

1.8V

1.8V

1.8V

3.3V

Carrier

Freq.(H

z)10

M13

.56M

10M

13.56M

16M

10M/100

MBitrate(bps)

1.12

M20

K10

M13

.56M/0.678

M16

M1.0M/10M

Area

0.19

mm

21.0mm

2NA

NA

NA

0.5mm

2

Pow

er61

0μw

3mw

119μw

191μw

6.3μw

319μw

/3.8

mw

Measured/simulation

Measured

Measured

Sim

ulated

Measured

Sim

ulated

Measured

BER

10E-5

7.58

E-6

NA

<10

–9@0.67

8Mbp

sNA

<10

–9@1.0M

bps

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5. Conclusion

In this paper, a novel fully digital BPSK demodulator which has simple structure andgood performances is presented. A standard 0.35-μm CMOS process was used to realisethe proposed demodulator and the experiment was conducted to verify the effectiveness ofthis novel BPSK demodulator. Measurement results show us that the designed demodu-lator can handle a wide frequency range of BPSK signals from 10 MHz/1.0 Mbps to 100MHz/10 Mbps with BER lower than 10–9, and can also work at 100% DRCF ratio withthe frequency up to 25 MHz, demonstrating that the designed demodulator has a char-acteristic of low power, low BER and wide speed range, and is suitable for using inbiological implants, portable facilities and wireless communications, etc.

FundingThis work was supported by the Natural Science Foundation of China [grant number 60976026].

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