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A FPGA-based Parallel Architecture for Scalable High-Speed Packet Classification. Author: Weirong Jiang, Viktor K. Prasanna Publisher: 2009 20th IEEE International Conference on Application-specific Systems, Architectures and Processors Presenter: Chin-Chung Pan Date: 2009/12/30. Outline. - PowerPoint PPT Presentation
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Author:Weirong Jiang, Viktor K. Prasanna
Publisher:2009 20th IEEE International Conference on Application-specific Systems, Architectures and Processors
Presenter: Chin-Chung Pan
Date: 2009/12/30
OutlineIntroductionArchitecture and AlgorithmsMotivationsArchitecture OverviewQuadtree Search on Single FieldsPartitioning Algorithm
Performance EvaluationAlgorithm EvaluationImplementation Results
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IntroductionMost of those algorithms fall into three categories:decision-tree-based (e.g. HyperCuts)decomposition-based (e.g. BV, cross-producting)partitioning-based (partition the original rule set into multiple
subsets)Based on the idea of the Independent Sets, we propose a
coarse-grained independent sets algorithm to reduce the number of partitions at the cost of increasing the number of linear search. Such extra cost is alleviated by pipelining the search process in hardware.
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Coarse-Grained Independent SetsThe original Independent Sets algorithm requires all the
rules within an independent set must be mutually disjoint on the same field.
We propose a coarse-grained independent sets algorithm to reduce the number of independent sets effectively.
B is a design-time parameter controlling the granularity of the independent sets.
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Motivations(1/2)
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Motivations(2/2)B is a design-time parameter controlling the granularity of
the independent sets.
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Architecture Overview(1/5)
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Architecture Overview(2/5)Each single-field search returns the information
associated with the primitive range that matches the value of the corresponding field of the input packet.
The outputs of the first stage include all information needed by the second stage. The search result from each field contains.
the IDs of the tables to look up. the indices that are used for table lookup.
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Architecture Overview(3/5)For instance, an input packet with SA = 10001000 and
DA = 01110111 will match the primitive ranges SA 011 and DA 010 on SA and DA fields, respectively.
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Architecture Overview(4/5)The information associated with SA 011 will include two
sets of {table ID, index} tuples: {00, 01} and {10, null}. This is because SA 011 is within the “01”th independent interval of the “00”th coarse-grained independent set, as well as within the only primitive range on the SA field of the cross-product table.
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Architecture Overview(5/5)Similarly, the information associated with DA 010 is:
{01, 00} and {10, 01}, since DA 010 is within the “00”th independent interval of the “01”th coarse-grained independent set as well as within the “01”th primitive range on the DA field of the cross-product table.
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Quadtree Search on Single Fields
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Partitioning Algorithm(1/2)
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R1
R2
R3
R4
R5R6
R7R8
R9
R10
SA
DA
R5R6
R7R8
R10
SA000 001 010 011 100 101
001
000
010
011
100
101
Prev Prev Prev CurrCurr Curr
Partitioning Algorithm(2/2)
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R1
R2
R3
R4
R9
SA
DA
000 001 010
000
001
011
100
101
DA
R2
R9
R4
Algorithm Evaluation(1/2)
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Algorithm Evaluation(2/2)
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Implementation Results(1/2)We implemented our design (P = 4,B = 2) that supported
the large rule set ACL_10K using Xilinx ISE 10.1 development tools.
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Implementation Results(2/2)Post place and route results show that the design sustains
90 Gbps throughput for minimum size (40 bytes) packets, which is more than twice the current backbone network link rate.
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