A Fast Block Structure Preserving Model Order Reduction for Inverse Inductance Circuits

A Fast Block Structure Preserving Model Order Reduction for Inverse Inductance Circuits

Hao Yu, Yiyu Shi, Lei HeElectrical Engineering Dept.UCLA

David SmartAnalog Devices Inc.

Partially supported by NSF, SRC and UC-MICRO fundPartially supported by NSF, SRC and UC-MICRO fund

2Challenge to Model Inductance

Cell parasitic capacitanceand well capacitance

Power IO

Load current source thatmodels switching gates Loop inductance?

Where is the return path? Current return paths are not known as a priori

How to stamp a loop inductance together with other devices in the same loop to the circuit matrix?

Partial inductance by PEEC [Rueli:TMTT’74] is one choice for inductive interconnect

c4bump

on diePower grid signal lines

C4 package Power Plane

skin depth

currentreturn

current

3PEEC Model for Interconnect

No need to determine return path But did we really solve the problem?

Partial inductance is associated with every piece of branch current Mutual couplings are everywhere L matrix is dense and not diagonal dominant

A fast simulator needs a sparse stamping of devices Sparsifying L by truncation leads to the loss of stability

Stamping inverse inductance (L-1) element is an alternative solution L-1 is similar to the diagonal dominant capacitance (C) [Devgan:ICCAD’02],

and hence it is easy to sparsify How to stamp it correctly in circuit matrix? How to further reduce it by

model order reduction?

4Inverse Inductance Element Simulation First-order stamping and reduction by modified nodal

analysis (MNA) Directly stamping leads to a non-passive model [Zheng et.al.:ICCAD’02] Double inversion based stamping [Chen,et.al.: ICCAD’03] needs an extra

cost to invert L matrix

Second-order stamping and reduction by nodal analysis (NA) NA-stamping [Sheehan:DAC99, Zheng et.al :ICCAD’02, Su et. al:ICCAD’04]

has singularity at dc, and is not robust to be stamped back for time domain simulation

All above methods did not consider the structure (sparsity and hierarchy), and hence are not efficient for large-scale problem

Primary contributions of our work:1. Vector potential nodal analysis (VNA) represents L-1 in a non-

singular and passive stamping2. Bordered-block-diagonal structured reduction (BVOR) preserves not

only passivity but also sparsity and hierarchy

5Outline

Background of Circuit Stamping VNA Stamping using VPEC (Vector Potential

Equivalent Circuit) model BVOR Method using BBD (Bordered-block-

diagonal) Representation Experimental Results Conclusions

6Modified Nodal Analysis A network is described by two state variables:

nodal voltage and branch current

vn+

Vn-

IbR

0,,

0,

dependentfrequency tindependenfrequency

iTl

l

l

n EB

LC

EEG

iv

x

BI(s)x(s)s

CG

:C:GC)(G

The stamping is not symmetric but passive Check (and full rank)0,0 TCCGG T

The stamping is non-singular State equation is still definite at dc

L is shorted and C is open at dc State matrix is not rank-deficient

especially for because it needs to be factorized many times

0s 0Cs

G

7Stamping of L-Inverse in Circuit Matrix MNA is not passive

Check 0?)(TGG

0

,,0

, 1i

Tl

l

l

n EB

IC

ELEG

Av

x CG

1

1( ) ( ) ( ), ;

: susceptance

i n

Tl l

G sC S x s E I s x vs

S E L E

NA stamping is symmetric, seems to be passive, but is singular Only uses nodal voltages, and it results in a susceptance S for L-1

State equation is indefinite at dc

Both G and S become rank-deficient in NA stamping

0s Ss

sC 1

8

NA

How to Easily Have a Singular Stamping

Why do we need branch current variable for inductance? The inductor is shorted at dc v2 and v3 are not independent anymore

Need a new constraint by adding a new row for i1

1v 3v1i

2v

RgR L

ini

v1 v2 v3 i1 (1/Rg+1/R) (-1/R) (0) (0)

(-1/R) (1/R) (0) 1

(0) (0) (0) -1

(0) (-1) (1) sL

v1

v2

v3

i1

9Outline




10Vector Potential Equivalent Circuit

2 , z

z z zAA J Et

Differential Maxell equation

1 zi i

iA d A

Define branch vector potential (flux) from a volume-integral of above differential equation [Pacelli:ICCAD’02]

^ ^

01 1 11 1,

( )ij iij ii ij

i j

R RL L L

^ ^

^ ^

0

, i ji ii i

j ii ij

A AA Ai vtR R

VPEC circuit equation describes L-1 elements using branch variables (ii, vi)

This leads to the proof that L-1 matrix is diagonal dominant [Yu-He:TCAD’05]

11VNA Stamping Using both branch and nodal variables, VPEC circuit

equation leads to a new circuit stamping for L-1

The resulting VNA state matrix is non-singular and passive

0,,

0, 11

1i

Tl

l

l

n EB

LC

ELELG

Av

x CG

nill vvAi ,

1

1 1 1

,

: ( ) and

l l i l n

n l l n i l n i

L A i A E v

KCL Gv E L A C v E I t L E v L A

12A Circuit Example

a2a1v6v5v4v3v2

1v1p2p1

v6v5v4v3

1

v21v1

p2p1

a2a1v6

-gv5-gv4

-sv3s-gv2

-gv1a2a1v6v5v4v3v2v1

v6v5

-g

g

v4v3v2

g+g dv1v6v5v4v3v2v1

sx-sx

-sxsx s

-s

-sx-s s

sx -s-sx sx

s ssxa 2sxsa 1

cv6v5

cx-cxv4cv3

v2-cxcxv1

a2a1v6v5v4v3v2v1

cv6v5

cx-cxv4cv3

v2-cxcxv1

v6v5v4v3v2v1

g

(a ) (b ) (c )

g+gd

VNA

(b )

g

g

c

xc

c

s

s

xs xs

v 1 v 2 v 3

v 4 v 6v 5

xs-xs-

dg

dg

(a )

g

lc

xc

cl

m

g

v 1 v 2 v 3

v 4 v 5 v 6

i 1

i 2

dg

dg

a2

a1

v6

v5

v4

v3

v2

1v1

p2p1

v6

v5

v4

v3

1

v2

1v1

p2p1

i2

i1

v6

-gv5

-gv4

-1v3

1-gv2

-gv1

i 2i 1v6v5v4v3v2v1

v6

v5

-g

g

v4

v3

v2

g+gdv1

v6v54

1

-1

-1 1

-1 1 lmi2

mli1

cv6

v5

cx-cxv4

cv3

v2

-cxcxv1

i2i1v6v5v4v3v2v1

cv6

v5

cx-cxv4

cv3

v2

-cxcxv1

v6v5v4v3v2v1

g

(a) (b) (c)

g+gd

MNA

NA

cv6v5

cx-cxv4cv3

v2-cxcxv1

v6v5v4v3v2v1

cv6v5

cx-cxv4cv3

v2-cxcxv1

v6v5v4v3v2v1

s- ssx- sxv6-ss- sxsxv5

v4sx- sxs- sv3- sxsx- ssv2

v1v6v5v4v3v2v1

s- ssx- sxv6-ss- sxsxv5

v4sx- sxs- sv3- sxsx- ssv2

v1v6v5v4v3v2v1

v 6v 5v 4v 3

1

v 21v 1

p 2p 1

v 6v 5v 4v 3v 2

1v 1

v6-gv5

-gv4v3

-gv2-gv1

v 6v 5v 4v 3v 2v1

v6v5v4v3

-gv2-gv1

v 6v 5v 4v 3v 2v1

g

g

( a ) ( b )

( c ) ( d )

g+gd

g+gd

13VNA Reduction (VOR) The simple first-order model order reduction such as

PRIMA [Odabasioglu,et.al:TCAD’98] can be applied Find a small dimensioned and orthnormalized matrix V

to reduce the original system size by projection

If V contains the subspace of moments, the reduced system can match the original system

TV

NxNNxN

G G

qxqqxq

VqxNqxN

s

H s

H s0s

14Advantages of VNA Reduction The reduced model is passive

Sufficient conditions for passivity:

VVV

VVV

BL

TT

TT

T

allfor ,0)()3(

allfor ,0)()2(

)1(

CCGG

The VNA reduction can be performed at dc (s0=0), and hence the path tracing algorithm [Odabasioglu,et.al:TCAD’98] can be used for efficient reduction

~

~~ ~

* * 0 0 * * 0 0* * ** * 0 * * 0 0 ( )

0 0 0 0 00 000 00

p p

p p

Ii i I s

su uIx x

TB0 CB 0 G

The reduced model by VNA can be robustly stamped together with active device for time-domain simulation

SAPOR is not robust to be stamped back with active devices

15Outline




16Two Level Decomposition by Branch Tearing

A flat presentation of VNA does not show hierarchy and hence leads to a globalized reduction and simulation It is not efficient for large-scale circuit with inductance Path-tracing [Odabasioglu,et.al:TCAD’98] is only effective for tree-links but not

for general network

X m0X m-1 ,0X 1 0 X 2 0

Y 1 Y 2 Y m -1 Y m

B 1 B 2 B m -1 B m

Z 0 Two-level decomposition of VNA circuit by branch-tearing It results in decomposed blocks Yi

and a global block Z0, and they are interconnected by incident matrix Xi0

The torn branch can be a resistor, a capacitor, or an inductor

A hmetis partition is applied with specified ports for each block

17BBD Representation

1 10 1

2 20 2

0

10 20 0 0

0 0 0 0 00 0 0 0 0

0 0 0 0 0

( ) ( ) ( ) 0 0 0 0m m m

T T Tm

Y X BY X B

Y BY X B

X X X Z

( ) ( )Y s x BI s

The resulting system is in fact a bordered-block-diagonal (BBD) state matrices Each block Yi is described by a set of VNA variables (vn, Al) The global block Z0 is described by a set of torn branch variables (ib)

The BBD stamping is passive

0)2( ,)1( * YYBL T

18BVOR: Localized Reduction BBD representation enables a

localized model order reduction Each block Yi (Gi, Ci, Bi) can be

reduced locally The last block is purely composed by

coupling branches, which is projected by an identity matrix

1

2

1

m

m

QQ

QQ

Q

Reduced model is not only passive but also sparse, and it can be analyzed hierarchically

1,1 1, 1 1,1 1, 1

2,2 2, 1 2,2 2, 1

, , 1 , , 1

1, 1 2, 1 , 1 1, 1 1, 1 2, 1 2, 1 1, 1

0 0 0 00 0 0 0

0 0 0 0

- - - - -

m m

m m

m m m m m m m mT T T T T T

m m m m m m m m m m m

G X G XG X G X

G X G X

X X X G X X X G

G G

Block-diagonal structured projection [Yu-He-Tan:BMAS’05] preserves BBD structure during reduction

19Outline




20Waveform Comparison (1)

Frequency/time domain waveform comparison of full-MNA, SAPOR [Su et.al:ICCAD’04] and VNA reduction (VOR) The reduced models are expanded close to dc (s0 = 10Hz) with order 80 VOR and original are visually identical in both time/frequency domain SAPOR has larger frequency-domain error and can not converge in time-

domain simulation

21Waveform Comparison (2)

Frequency domain waveform in both low and high frequency range The reduced models are expanded at s0 = 1GHz with order 80 VOR is identical to the original in both ranges, But SAPOR has large error in low-frequency range.

22BBD Structure Preserving

BBD (two-level decomposition) representation and reduction of G and C matrices The reduced model has preserved sparsity and BBD structure

23Runtime Scalability Study of BVOR

Compared to SAPOR, BVOR (BBD reduction) is 23X faster to build, 30X faster to simulate, and has 51X smaller error

Compared to VOR, BVOR is 12X faster to build, 30X faster to simulate

24Conclusions and Future Work

Propose a new circuit stamping (VNA) for L-inverse element, which is passive and non-singular

Apply a bordered-block-diagonal (BBD) structured reduction, which enables a localized model order reduction for large scale RCL-1 circuits

We are planning to extend the structured reduction to handle nonlinear system

Documents

A Fast Block Structure Preserving Model Order Reduction for Inverse Inductance Circuits