A digital calibration algorithm for implementing accurate on-chip resistors

Analog Integr Circ Sig Process (2006) 47:259–272DOI 10.1007/s10470-006-5675-6

A digital calibration algorithm for implementing accurate on-chipresistorsAyman A. Fayed · M. Ismail

Received: 1 April 2005 / Accepted: 24 October 2005 / Published online: 3 April 2006C© Springer Science + Business Media, LLC 2006

Abstract A digital calibration algorithm that provides asystematic method for implementing accurate integrated re-sistors without compromising linearity or noise performanceis described. The technique uses a single external resistor as areference to implement multiple, different valued integratedresistors without requiring any accurate reference voltage.The algorithm provides a method to calibrate several on-chip resistors without replicating the calibration circuit, andit can achieve an arbitrary accuracy limited only by the ex-ternal resistor’s accuracy and mismatch errors. Terminationsfor two high speed wire line transceivers are implemented us-ing the algorithm and simulations and measurements resultsshow adequate performance across process, temperature, andsupply voltage.

Keywords Calibration . Circuit tuning . Resistive circuits .

Adaptive codes . CMOS integrated circuits . Transmissionline . Digital communication

1. Introduction

Accurate resistors are a fundamental building block in manyanalog IC designs. Numerous applications in the area of ana-log signal processing require accurate resistors to achieve the

A. A. Fayed (�)Texas Instruments Inc., 12500 TI Blvd., MS 8729,Dallas, Texas 75243, USAe-mail: [email protected]

M. IsmailAnalog VLSI Laboratory, Department of Electrical Engineering,The Ohio State University,2015 Neil Ave., Columbus, OH 43210, USAe-mail: [email protected]

desired performance. Accurate integrated filters, oscillators,and transmission line terminations for high speed wire linetransceivers are just few examples of systems that couldrequire highly accurate resistors for adequate performance.Off-chip discrete resistors are highly accurate (around 1%),but they limit the achievable integration level, imply highercost, and are limited by the number of pins that can be used toconnect them to the internal circuitry. In addition to the costand pin count, parasitic elements such as bond-wire capac-itance and inductance introduced to the path to the off-chipresistor significantly degrade the accuracy as well as speed.

On-chip resistors are an attractive alternative due to theircheaper cost and the higher integration levels that could beachieved. Yet, the limited control over the accuracy of theirabsolute value—especially in digital CMOS processes—could potentially degrade the performance of the whole sys-tem. Most processes achieve only ± 25% control over theaccuracy of the absolute values of on-chip resistors. This facthas been a major obstacle for fully integrating systems thatrequire highly accurate resistors [1].

Many techniques were developed to implement accurateon-chip resistors using automatic tuning techniques [2–5].Some techniques use tunable, purely-active devices (transis-tors) configured to cancel any nonlinearity in the transistorsbehavior [6–12]. Those transistors are placed in a feedbackloop to maintain the resulting resistance at an accurate level.Usually though, since those transistors represent 100% of theimplemented resistance, the accuracy of their gate-to-sourcevoltage is crucial for determining their equivalent resistance,which implies that an on-chip accurate voltage needs to beimplemented (a band-gap). Furthermore, since the transis-tors are used as analog elements (not as digital switches),the tuning process that provides their gate-to-source voltagehas to be done in the analog domain, which has multipledisadvantages. First, there is no simple, power efficient way

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260 Analog Integr Circ Sig Process (2006) 47:259–272

to store analog values, therefore, the analog tuning loop thatprovides the tuning voltage to the transistors (usually theirgate-to-source voltage) has to either be operating at all times,or the result of the tuning process has to be stored on a capac-itor and periodically refreshed. Both alternatives are powerand area inefficient. Second, analog tuning is generally moresusceptible to noise especially when the tuned resistance isimplemented using only transistors. This implies that anynoise glitches on the tuning voltage will have direct impacton the value of the implemented resistance. Third, analogtuning does not generally provide a simple, area efficient wayto tune several, and different valued on-chip resistors inde-pendently. The reason behind that is that it is generally verydifficult to design different valued resistors (implementedusing transistors) such that they all use the same tuning volt-age range, especially if the ratio between those resistors isfractional. Thus, it is very difficult to use the same tuningloop to independently tune all the different resistors on thechip, and in most cases each resistance requires a separatetuning loop, which is an area and power expensive solution.In addition to the disadvantages of analog tuning mentionedabove, using active devices with non-linearity cancellationtechniques still generally suffers from range, linearity, andnoise problems. The range problem evolves from the factthat active transistors need a specific minimum voltage to beturned on, as well as any other range restriction to keep themin a specific operation mode (triode, or saturation), whilethe linearity problem evolves from the fact that non-linearitycancellation techniques are relying on the square-law repre-sentation of the transistor, which has an accuracy limit spe-cially for short channel transistors [13]. On the other hand,since active elements are in direct contact with the substrate,they are relatively more vulnerable to noise coupling fromthe substrate, which limit the noise performance of the im-plemented resistor especially when active devices constitute100% of the resistor.

Some other techniques use a combination of on-chip pas-sive resistors and active devices together to implement therequired resistance [14]. In that case, the active device isusually used to correct for the errors in the on-chip passiveresistor (usually by connecting the active device in paral-lel with the on-chip passive resistor). Since the correctionis still done through the resistive contribution of an activedevice, the total resistance will suffer from range and lin-earity limitations (even though less than the purely activeimplementations). In addition to that, an accurate voltagereference, and analog tuning loops are still needed.

Switched-C techniques are also usually used in the areaof integrated filters to implement the required on-chip resis-tance using ratio between capacitors, but they require clocksand can only operate in discrete-time domain [15].

This paper introduces a digital tuning algorithm forimplementing accurate on-chip resistances using passive

elements. The technique has the advantage of using a singleoff-chip resistor to tune all the required on-chip resistorsautomatically even if they are of different values or scatteredin different areas of the chip. In most analog and mixedsignal ICs, an off chip resistor is usually readily available andis used to generate accurate biasing currents. The proposedtechnique, even though does not have to, can use that sameoff-chip resistor for tuning purposes without disturbingthe biasing current generation process. It could achieve, ifneeded, an arbitrary tight control over on-chip resistors thatwill be limited only by the accuracy of the external resistor,mismatches, and area. The technique does not require anyaccurate voltage references and it implements the requiredresistance using on-chip passive resistors, while using activedevices is limited to digital switching purposes with anegligible contribution to the total resistance and withouthaving to design those switches with large dimensions.This fact reduces the noise introduced to the system andmaintains high linearity, wide range of operation, and highspeed performance. Transmission line terminations for twohigh speed wire line transceivers (480 Mbps, and 1.65 Gbps)that required ± 10% accuracy are implemented using thealgorithm. Simulations and measurements results show ade-quate performance across process, temperature, and supplyvoltage.

2. The proposed calibration technique

Implementing accurate on-chip resistors using active ele-ments with nonlinearity cancellation, or using passive wellor polysilicon resistors requires essentially some sort of anautomatic tuning procedure. The automatic tuning processhas three fundamental steps. The first step is the design ofan electronically tunable element (a tunable resistor in thiscase). The second step is quantifying the drift in the parame-ter of interest (which is the resistance value in this case). Thethird step is generating a tuning signal based on the detecteddrift in the parameter of interest to adjust it back to its desiredvalue. Therefore, a tunable resistor, a method of quantifyingthe drift in the resistance value, and a tuning signal generationmethod need to be developed in order to achieve the tuningprocess.

Most modern mixed-signal ICs essentially have an off-chip resistor and a band-gap reference circuit, where bothare used to generate accurate biasing currents and voltagesneeded by the analog parts of the circuit. The proposed ar-chitecture uses this same off-chip resistor as a referencewithout interfering with the bias current generation process.The proposed technique however does not need the band-gapreference or any kind of an accurate voltage reference. Be-fore the technique is introduced, a discussion of the conceptof “variation range quantization” is presented.

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Analog Integr Circ Sig Process (2006) 47:259–272 261

Fig. 1. The variation rangequantization concept. The rangeof error in the value of on-chipresistors is being divided to nequal regions, with each regionequal to the maximum desirederror

2.1. The variation range quantization concept

The concept of “variation range quantization” is shown inFig. 1. Let’s assume that an on-chip resistor is designed tohave the value Rreq in nominal conditions. Given process andtemperature variations, this value will drift. Let’s define themaximum relative percentage the on-chip resistor value candrift from its nominal value Rreq to be ± DMax%, where DMax

is a function of the process, physical dimensions of the resis-tor, and temperature. It is usually available through processcharacterization. Now, let’s define the maximum relative per-centage variation we desire for the on-chip resistor to driftfrom its nominal value Rreq to be ± CMax%. As shown inFig. 1, the whole ± DMax range can be divided into (n + 1)different regions, where each region is CMax wide except forregion (n/2) which is 2CMax wide. Region (n/2) is essentiallywhere the tuning algorithm needs to place the variation in thevalue of the on-chip resistance. This leads to the followingequation that determines n:

n =(

DMax

CMax− 1

)× 2 (1)

Therefore, what the tuning algorithm should achieve is toalways tune the variation in the resistor value to region (n/2)if the variation in the resistor value falls into any of thedifferent (n + 1) regions in Fig. 1.

2.2. The resistor block

Given the explanation of the “variation range quantization”concept presented earlier, a logical starting point would beimplementing the required resistance using a resistor blockthat is composed of (n + 1) parallel on-chip resistors asshown in Fig. 2 instead of a single resistor, where eachresistor is controlled with a MOS switch that can be turnedon or off using a digital control signal. In Fig. 2, R0 rep-resents the core resistance and its value is close to Rreq,

0R

nR

C(n/2)+1V

(n/2)R

1R

CnV

C1V

C(n/2)V

(n/2)+1R

Fig. 2 The proposed resistor block

while the rest of the resistors are just modulating resistorsthat could be switched on or off to adjust the total resis-tance of the resistance block to be within Rreq ± CMax%.For example, if in nominal conditions the parallel combi-nation of R0 up to Rn/2 is designed to be exactly equal toRreq, then errors due to process variations could be correctedas follows:

If the drift in the resistors values due to process variationsis negative (lower resistors values), then the error can becorrected by switching off some of the parallel resistors R1

up to Rn/2 depending on the amount of the drift. On the otherhand, if the drift is positive (higher resistors values), then theerror could be corrected by switching on some of the parallelresistors R(n/2)+1 up to Rn. Therefore, given the amount oferror in the value of the on-chip resistors that compose the

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resistor block, the digital control signals should assume adigital value to counteract this variation. This resistor blockrepresents the electronically tunable element in the proposedtuning architecture. The next section presents a mathematicalway for determining the number of resistors in the resistorblock, the value of each resistor, and how to develop thecontrol signals.

2.3. The algorithm

To start off, if each variation region in Fig. 1 is assigned toone of the parallel resistors in the resistor block that couldbe switched on or off, we can find adequate values for thoseresistors to guarantee that the total resistance of the resistorblock is within region (n/2). As discussed earlier, the resistoris designed such that in nominal conditions R1 through R(n/2)

are switched on, while R(n/2)+1 through Rn are switched off.Note that R0 is always connected, which is an advantage thatwill be discussed later in details. According to the variationin the values of those resistors, the tuning algorithm shouldeither switch on or off more resistors in parallel to R0 in orderto always place the total resistance of the resistor block to bein region (n/2). The previous discussion implies that:

R0//R1// . . . R(n/2) = Rreq (2)

Note that the resistors names represent their nominal or idealvalues. In order to develop mathematical equations that de-termine the nominal values of the (n + 1) resistors, twoassumptions will be made. First, we will assume that allthe resistors in the resistor block vary in the same wayand also with the same relative magnitude. This assump-tion is well justified since on-chip resistors maintain theirratio very well, which implies that their relative magnitudechange is also the same. In fact on-chip resistors usuallymatch within better than 0.1% given that all of the resis-tors are placed in a very close proximity to each other andalso have close values [1]. Provided that the resistors arelaid out carefully, and are designed to have wide enoughdimensions to minimize under etching effects, i.e. �W/Wand �L/L, this assumption is safe. The second assumptionis that the switch resistance is included into the resistorsvalues and represents a small portion of the total resistanceof each resistor. This is an assumption that is not immedi-ately obvious, specially when the required resistance valueis relatively small, but as will be showed later in this paper,the proposed tuning algorithm makes this assumption valid,which is one of the important advantage of the proposedtechnique, i.e. the non-linearity of the switch resistance hasa very small effect on the linearity of the whole resistorblock.

In order to develop an intuitive methodology for calcu-lating the values of the resistors in the resistor block, let’sstart by assuming that the on-chip resistors in the resistorblock changed from their nominal value by a percentagevalue between (−Dmax)% and ( − DMax + CMax)%, whichis equivalent to region (0) in Fig. 1. Note that ( − DMax +CMax) = − (n/2)CMax. Since this is the worst case nega-tive variation (the smallest value of all the resistors), all theresistors R1 through R(n/2) should be switched off leavingonly R0 connected. Note that using this strategy, R0 doesnot need a switch, which is a very beneficial fact as willbe explained later on. Since in this case only R0 is present,it has to satisfy the following two inequalities to cover itsvariations:

R0(100 − DMax) > (100 − CMax)Rreq (3)

R0

(100 − n

2CMax

)< (100 + CMax)Rreq (4)

Inequality 3 guaranties that if the variation is at the bottomof region (0) (which is (−DMax)%), then the nominal valueof R0 will be high enough to place the total resistance ofthe resistor block (including the variation) at a value higherthan the bottom edge of region (n/2). Inequality 4 guarantiesthat if the variation is at the top of region (0) (which is(−DMax + CMax)%), then the nominal value of R0 will below enough not to place the total resistance of the resistorblock (including the variation) at a value higher than the topedge of region (n/2). Both inequalities guarantee that for anyvariation within (−DMax)% and ( − DMax + CMax)%, thetotal resistance of the resistor block (including the variation)will be always within ± CMax% from the required nominalvalue Rreq. Combining inequalities 3 and 4 into a singleinequality:

100 − CMax

100 − DMaxRreq < R0 <

100 + CMax

100 − n2 CMax

Rreq (5)

Inequality 5 determines the range R0 can nominally take.Now assuming that the on-chip resistors in the resistorblock changed from their nominal value by a percent-age value between (−DMax + CMax)% and (−DMax +2CMax)%, and assuming that in this case both R0 and R1

will be switched on, then following the same logic usedto determine R0, the following inequality can be used todetermine R1:

100 − CMax

100 − n2 CMax

Rreq < R1//R0 <100 + CMax

100 − n−22 CMax

Rreq (6)

solving inequality 6 for R1:

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R0(100 − CMax)Rreq

100(R0 − Rreq) + CMax(Rreq − n

2 R0) < R1

R1 <R0(100 + CMax)Rreq

100(R0 − Rreq) − CMax(Rreq + n−2

2 R0)

(7)

Again, inequality 7 defines a range of values the nominalvalue of R1 can take as a function of R0, while R0 could bedetermined using inequality 5.

If the same methodology is followed (adding more re-sistors in parallel) to calculate the rest of the resistorsvalues, the following set of recursive inequalities can bedetermined:

(100 − CMax)Rreq RTi

100(RTi − Rreq) + CMax(Rreq − ( n2 + 1 − i)RTi )

< Ri

Ri <(100 + CMax)Rreq RTi

100(RTi − Rreq) − CMax(Rreq + ( n2 − i)RTi )

(8)

for i < n2 , and

(100 − CMax)Rreq RTi

100(RTi − Rreq) + CMax(Rreq − ( n2 − i)RTi )

< Ri

Ri <(100 + CMax)Rreq RTi

100(RTi − Rreq) − CMax(Rreq + ( n2 − i − 1)RTi )

(9)

for i > n2 , and

1

R n2

= 1

Rreq− 1

RTn2

for i = n

2(10)

where i is an index that starts from 0 to n in order to calculatethe resistors from R0 up to Rn, and RTi is the total parallelcombination of R0 up to Ri−1, or mathematically:

1

RTi=

k=i−1∑k=0

1

Rkfor i > 1 and

RT0 = ∞ for i > 0 (11)

Note that for the special case when i = 0 and RT0 = ∞ , in-equality 8 will be reduced to Eq. (10). Note also that Eq. (10)is another form of Eq. (2).

2.4. Quantifying the drift

After the mathematical equations that determine the nominalvalues of the resistors in the resistor block have been devel-oped (which represent the first step of the tuning process),a technique to quantify the drift in the resistance value hasto be developed. This drift quantification process representsthe second step of the tuning process. In order to achieve

VDD

VB

M21M

VDD

: 1K

VBr

extR intR

Fig. 3 The proposed circuit for evaluating the drift in the value of theon-chip resistor Rint from the reference resistor Rext

that, the circuit in Fig. 3 could be used. The op-amp copiesa reference voltage VB to an off-chip resistor Rext. The cur-rent generated is then mirrored and injected to an on-chipresistor Rint. Note that the simple current mirror showed inFig. 3 is only conceptual, a high quality current mirror de-signed to minimize the effects of transistor mismatches onthe mirroring ratio K and also has a high output impedanceshould be used. Usually a cascode or a low voltage cascodecurrent mirror is sufficient. The voltage across Rint (VBr)will be:

VBr

VB= Rint

K Rext(12)

Equation (12) shows that the relative percentage change inRint from the factor KRext (which is why Rext is considered thereference) will cause the same relative change in VBr fromVB. Therefore, if Rint is implemented using the same resistortype as in the resistor block and laid out in a close proximityto it, then by comparing VBr to VB, the relative variationin the values of the on-chip resistors in the resistor blockdue to process and temperature variations can be detected.It is worth mentioning that since VBr is being comparedto VB to find the relative change, the absolute value of VB

or its accuracy is of no concern. In fact, it could simplybe just a potential divider from the supply and it does notmatter if it changes with process or temperature. It is worthmentioning though that the topology used in Fig. 3 is usuallyused to generate accurate biasing currents by taping off morecurrent mirrors and using a band-gap circuit to provide VB.Therefore, if the system requires those accurate currents,then the proposed tuning architecture could simply use itfor its purposes without interfering with the biasing currentgeneration process. Otherwise, there is no need to use a bandgap circuit. The factor K as well as Rint could simply beanything desired, but since VBr is being compared to VB, it ismuch easier just to set the ratio in Eq. (12) to be nominallyequal to unity. This implies that the nominal value of Rint

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(its desired ideal value) will be K times Rext. This gives moreflexibility in choosing the value of Rint, for example pickingRint to be double Rext will reduce the power consumption bya factor of two on the expense of doubling the area neededto implement Rint.

2.5. Tuning signal generation

As shown by the “variation range quantization” concept dis-cussed earlier, the state of the switches controlling the resis-tors in the resistor block is determined based on the region inwhich the relative change in the values of the on-chip resis-tors from their nominal value occur. Since the ratio VBr/VB isessentially equal to the relative change in the values of the re-sistors, and using the borders of each variation region shownin Fig. 1, then according to the algorithm presented earlierthe states of the switches can be determined as follows:

If VBr > (1 − n2×100 CMax)VB , then resistor R1 will defi-

nitely be switched on. Let’s call the digital control signal(which is the tuning signal) that controls the switch to beVC1 and let’s assume that it’s active high. This leads to thelogical equation:

VC1 = high if VBr > Vr1 and

VC1 = low if VBr < Vr1 (13)

where Vr1 = (1 − n2×100 CMax)VB . Thus, the digital control

signal VC1 that controls the switch is simply the result ofthe comparison of VBr to the reference voltage Vr1 whichcorresponds to the lower border of region (1) in Fig. 1. Usingthe same steps, the following set of recursive equations thatdetermine the control signals for all the switches as well asthe reference voltages needed for the comparison processwith VBr could be written as:

Vri =(

1 −( n

2 + 1 − i

100

)CMax

)VB for i ≤ n/2 (14)

Vri =(

1 −( n

2 − i

100

)CMax

)VB for i > n/2 (15)

and for i ≤ n/2:

VCi = high if VBr > Vri and

VCi = low if VBr < Vri (16)

while for i > n/2:

VCi = low if VBr < Vri and

VCi = high if VBr > Vri (17)

Fig. 4 The proposed voltage reference generator

where i is an index that starts from 1 to n. Note how innominal conditions, the logic levels of VCi are inverted fori > n/2.

Generating the reference voltages Vri in Eqs. (14) and(15) is essential for the tuning process. As shown by thoseequations, the reference voltages are simply different frac-tions of the reference voltage VB. Thus, the reference volt-age generator shown in Fig. 4 could be used. In Fig. 4,the op-amp forces VB on the series on-chip resistors Rr0

to Rr(n/2), and due to the infinite input impedance of theop-amp, the resulting current will also flow through the re-sistors Rr(n/2+1) to Rr(n). Using Eqs. (14) and (15) thoseresistors values could be found using the following recursiveequation:

Rri =(

1 −( n

2 − i

100

)CMax

)Rrt −

k=i−1∑k=0

Rrk (18)

where i is an index that starts from 0 to n, and Rrt =∑k=n/2k=0 Rrk . Note that Rrt along with VB determine the

amount of current flowing in the potential divider. Note alsothat when i = 0,

∑k=−1k=0 Rrk = 0.

Once the reference voltages are generated using the circuitin Fig. 4, generating the actual control signals representedby Eqs. (16) and (17) becomes just a matter of comparingthe reference voltages with VBr. The control matrix shownin Fig. 5 is a conceptual implementation of Eqs. (16) and(17) in which a stack of n comparators are used to performthe comparison process and generate the control signals ac-cordingly. Note that the control matrix could be physicallyimplemented as in Fig. 5, in which the tuning process willbe done within one comparator delay on the expense of us-ing n comparators, or it could be implemented with a single

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Fig. 5 A conceptual implementation of Eqs. (16) and (17)

BV

Rext

VBr

R int

C(n/2)+1

VC1

VCn

V

C(n/2)V

Dig

ital

Con

trol

Mat

rix

rnRn

Resistor Block

Ref

eren

ce G

ener

ator

Vr1

Vr(n/2)

Vr(n/2)+1

V

R(n/2)+1

R0

R1

R(n/2)

VDD VDD

Fig. 6 The complete calibration architecture

comparator and a state machine where the reference voltagesare successively switched to the input of the comparator andthe results being stored. In this case, die area is saved on theexpense of longer tuning time. Figure 6 shows the completecalibration architecture.

3. Practical advantages and limitations

In this section some practical advantages, accuracy limita-tions, and design considerations of the proposed techniquewill be pointed out.

3.1. Accuracy limitations

Considering the proposed algorithm, it is obvious that theaccuracy of the tuning process is limited by the followingfour factors. The first factor is the accuracy of the referenceoff-chip resistor Rext. The second factor is the ratio VBr/VB

and how accurate it really represents the drift of Rint fromthe reference Rext. The third factor is how close the relativeerror detected in the value of Rint (through the ratio VBr/VB)is to the actual relative error in the values of the resistors inthe resistor block. The fourth factor is the accuracy of the

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comparison process between VBr and the reference voltagesshown in Fig. 4. As will be discussed later, the second andthird factors are really coupled to each other.

As for the first factor, typical off-chip resistors have an ac-curacy of ± 1%, but they are also available with an accuracyof up to ± 0.1% for a significantly higher cost. The accuracyof the off-chip resistor represents the maximum theoreticalaccuracy of the proposed algorithm.

As for the second factor, the current mirror ratio K inEq. (12) defines how accurate the ratio VBr/VB represents thedrift of Rint from Rext. Therefore, it becomes a question ofthe mismatch error in the current mirror. Since the currentbeing mirrored is really a DC current (no speed restriction),the current mirror could be designed with relatively largedimensions to improve matching. By using a cascode struc-ture and with careful layout, the mismatch error could belimited to 1% or less in a digital CMOS process. It is worthmentioning though that if the ratio K is very large, then themismatch error could significantly increase due to the largerarea the mirror transistor will occupy, leading process gradi-ents to dominate the matching. Therefore, the ratio K has tobe carefully chosen for best matching.

As for the third factor, it is again a question of the accuracyof the ratio between Rint and the rest of the resistors in the re-sistor block. Generally, the error in this ratio could be limitedto within ± 0.1% with appropriate layout and sizing of theresistors given that the ratio between Rint and the resistors inthe resistor block is not very large (typically less than 20).Typically though, keeping both the current mirror ratio K andthe ratio between Rint and the resistors in the resistor blocklow is not necessarily achievable simultaneously, especiallyif the required resistance is small (50 � for example). In thiscase a compromise between these two accuracy limitationshas to be reached. In general terms, the mismatch error incurrent mirrors is much more significant with a larger mirror-ing ratio than the mismatch error between resistors with thesame large ratio (provided that the resistors are poly resis-tors). Hence, it is always better from an accuracy perspectiveto keep the mirroring ratio K small and accept a large ratiobetween Rint and the resistors in the resistor block. Havingsaid that, the ± 0.1% error in the ratio between the resis-tors mentioned earlier could be no longer achievable and ahigher error should be expected and accounted for. In orderto improve that error though, Rint and the rest of the resistorsin the resistor block could be implemented using paralleland series combinations of a unit resistor. Ideally, the unitresistance used should be the geometric mean of the largestand smallest resistors, but this implies that all the resistorshave to be an integer multiple of that unit resistor, which isnot possible since the values of the resistors are set by thealgorithm. Therefore, using the unit resistor will imply thatsome of the resistors will have to use fractional resistors inaddition to integer multiple of the unit resistor. To improve

the matching even further, it’s best for the unit resistor not touse minimum width or length in order to minimize the errorsin its absolute value, and consequently minimize mismatcherror between the different resistors. Yet, this has a seriousarea penalty.

As for the fourth factor, there are two elements that de-termine the accuracy of the comparison process. First, theaccuracy of the ratio between the reference voltages shownin Fig. 4 and VB, and how well those ratios really representthe borders of the variation regions shown in Fig. 1. Second,the error in the comparison process between VBr and the ref-erence voltages due to the input offsets of the comparators.As for the first element, it’s again a question of matching be-tween the resistors that compose the circuit shown in Fig. 4.With careful layout and sizing of those resistors, mismatcherror could be limited to ± 0.1% [16]. As for the secondelement, the input offset of the comparators will have no ef-fect on the results of the comparison process unless the ratioVBr/VB is within the input offset of the comparator from theborder lines of the variation regions in Fig. 1. In this case,the error introduced to the tuning process will depend on theratio between the input offset voltage of the comparator andthe reference voltage VB. The input offset voltage could beeasily limited to less than 5 mV with careful layout, and ifVB is chosen to be 1.2 V, then the error could be limited to± 0.4%.

From the previous discussion, the achievable accuracy ofthe proposed algorithm will be limited to the accuracy ofthe off-chip resistor and mismatch errors between similaron-chip elements. So in essence, the proposed algorithmmakes the accuracy issue of on-chip resistors a questionof matching between similar on-chip elements instead of aquestion of absolute values accuracy. The same concept usedto replace resistors in switched capacitors circuits. The majordrawback of the technique though is its relatively larger areaconsumption to achieve good matching between Rint and thedifferent resistors in the resistor block.

3.2. Practical advantages

The proposed technique has multiple practical advantagesthat are worth pointing out. The first advantage of the pro-posed technique is the recursive nature of Eqs. (8) to (10) and(14) to (18). This recursive nature makes the design processvery simple. An excel sheet or a matlab code could sim-ply be developed to calculate those equations. The requiredresistance value Rreq, the maximum variation DMax, the re-quired accuracy CMax, and Rrt could be introduced to theexcel sheet or the matlab code as inputs, and all the resistorsin the resistor block as well as the reference generator couldbe calculated.

The second advantage is that Eqs. (8) to (10) give a rangeof values that each resistor in the resistor block can take

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rather than a specific accurate value. This makes the designvery flexible to inaccuracies and very easy to implement.Normally, the value of each resistor in the resistor blockshould be in the middle of the range specified by Eqs. (8) to(10) in order to achieve the maximum margin possible.

The third advantage is that the modulating resistors R1

through Rn are significantly higher than the core resistor R0.For example, if Rreq = 50 �, DMax = 25%, and CMax = 5%then R0 will be about 65 �, while R1 up to Rn will be in thekilo ohms range, which is much higher than R0. This shouldcome of no surprise since R1 up to Rn are just used to tune thetotal resistance of the resistor block, while R0 is the resistorthat will bear most of the current flowing in the block. Sinceonly R1 up to Rn have switches and not R0, the design of theswitches become really easy due to the resistors relativelyhigh values. Consequently, the switches do not have to bedesigned with large sizes in order to make their resistancerelatively small (switches usually need to have a relativelysmall resistance in order not to affect the linearity of theresistor connected to it). Moreover, not only the switchescan easily be designed to have a small resistance relativeto R1–Rn, but the switches contribution to the actual totalresistance of the resistor block will be even smaller sinceR0 is the main contributor to the total resistance rather thanR1–Rn. This relaxes the design of the switches even furtherand reduces their noise contribution without compromisingthe linearity of the resistor block. Not having to design theswitches to be large will also reduce the capacitive loadingof the switches, which will widen the frequency range theresistor block could be used for. This advantage becomesvery clear taking into account that some techniques use asingle resistor instead of a resistor block, and to achievethe tuning, a bank of resistors is used with each resistorhaving a slightly drifted value from Rreq. Depending on pro-cess variations, only one resistor out of the bank of resistorswill be used. This means that the switch has to be neg-ligible relative to values close to Rreq, which will requiresignificantly larger transistors as opposed to the proposedtechnique. Note that if the switch does not have a relativelynegligible resistance, it will degrade the linearity of the totalresistance and will also increase the variation in the totalresistance with temperature. This clarifies the advantage ofthe proposed technique and also justifies the second assump-tion made during the development of the recursive Eqs. (8)to (10).

The fourth advantage of the proposed technique is that itallows the tuning of several, different valued resistors inde-pendently using the same calibration circuit whether thoseresistors are implemented in a close proximity, or scatteredacross the chip. If the different valued resistors are laid outcarefully and in a close proximity, then simply a single Rint

could be used to tune all the different resistors simultane-ously. This is possible since resistors laid out in a close

proximity usually maintain their ratios to within 0.1%. If theresistor blocks have to be scattered to different locations onthe chip, then there are two options. The first option is todedicate a separate Rint resistor for each individual resistorblock and lay out this dedicated Rint in a close proximity to itscorresponding resistor block. The same control matrix andreference generator could then be used along with a statemachine to perform the calibration of each resistor blocksuccessively. The state machine stores the results of the cal-ibration of each individual resistor block and then providesindependent control voltages for each block. Note that forthis option, even though Rint is replicated, still only a singlecontrol matrix and reference generator are needed, which isa significant area saving.

The second option for calibrating scattered, different val-ued resistors is to use a single Rint resistor for all the resistorblocks, and simply reduce CMax further to account for themismatch between the scattered resistor blocks. This op-tion is preferable since it eliminates the need to replicateRint, which saves even more area on the expense of reduc-ing CMax. Note that reducing CMax might imply increasingthe number of resistors in each resistor block, which againincreases the consumed area. Generally though, since Rint

needs to have a relatively high value to reduce the amountof current required to produce VBr in Fig. 3, the area savedby not having to replicate Rint is usually larger than the areaadded in the resistor blocks in order to reduce CMax. Sincethe second option does not require the use of a state machine,i.e. the calibration is done for all the resistor blocks simulta-neously and they all use the same control signals, and doesnot require the replication of Rint, this option is preferredespecially that designing the resistor blocks for a reducedCMax is much easier from a layout perspective than replicat-ing Rint. If the second option is chosen though, it is desirableto implement the single Rint at the center of the chip in orderto give an average estimation of the errors in the resistors inthe rest of the chip.

Taking into consideration that the control matrix itselfwhether it is used in the first or the second option could beimplemented using a single comparator on the expense ofusing a simple state machine (if used in conjunction withthe first option), or a little more complicated state machine(if used in conjunction with the second option), more areacould be saved. In addition to saving the area, using a singlecomparator adds a systematic error to the calibration processthat could be easily corrected for, instead of the more randomerrors that could be introduced due to multiple comparators.Also, using a single comparator shifts the complexity of thecontrol matrix to the digital domain, in which the designis easier, simply synthesized, and less sensitive to processvariations.

The fifth advantage is that the proposed technique doesnot require any accurate voltage references. Essentially, VB

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is arbitrary and does not need to be accurate. This is due tothe fact that the reference voltages are generated using thesame voltage VB that is used to generate the current fromRext. This is specifically an advantage for systems that do nothave a band-gap circuit available on-chip.

The sixth advantage of the technique is that it’s using thesame components that are usually used to generate accuratebiasing currents for the analog parts in the system withoutdisturbing it. The structure shown in Fig. 3 could be actuallyused to generate accurate biasing currents to the rest of thecircuit by taping off more current mirrors. In this case VB

will be the output of a band-gap circuit, which will have tobe used anyway to generate the biasing currents whether theproposed technique is used or not. In some analog parts, thebiasing currents do not have to be very accurate, and insteadof using the band-gap voltage across an external resistor, itis used across an on-chip resistor. In that case, the structurein Fig. 4 could be used to generate those biasing currents aswell by setting Rrt in Eq. (18) to the desired value. Whetherthe biasing currents are generated using the band-gap voltageacross an external resistor or an on-chip resistor, the proposedarchitecture can be easily accommodated. Hence, the powerconsumption of the proposed technique is effectively onlythe power consumed in Rint and the control matrix.

3.3. Design considerations

There are some useful considerations that should be takeninto account during the design process of the proposed archi-tecture. First, if the application specifies a certain requiredaccuracy on the on-chip resistance, then CMax has to be cho-sen to be a little tighter than the required accuracy. This isto account for the errors in the value of Rext (usually varieswithin 1%), any mismatch errors in the current mirror usedto inject the current into Rint, errors encountered in the com-parison process between VBr and the reference voltages, anderrors in the ratio between Rint and the rest of the resis-tors in the resistor block. Usually a 2 to 3 percent marginin CMax is sufficient. Extra margin could be also achievedthrough choosing DMax (the maximum error in the value ofthe on-chip resistor) to be a little higher than what the processcharacterization shows.

Second, it is not desirable to have to tune for errors dueto temperature change since it is time dependent. Having totune for temperature variations will consequently require thetuning circuit to be active at all times, which increases thepower consumption. Even though the proposed techniquecould achieve that, but it is wiser to avoid it. Therefore, un-der nominal process conditions and across all temperaturerange, the designer has to make sure that each resistor inthe resistor block does not vary more than ± CMax% fromthe nominal value. Using silicide-block poly resistors to im-plement the resistors in the resistor block easily fulfills this

requirement due to their very small temperature coefficient.Having a negligible switch resistance helps a lot too in min-imizing variations with temperature. If there is no need totune for temperature variations, then the tuning circuit couldbe activated only one time during power up and then deac-tivated for the rest of the operation time without worryingabout temperature effects.

Third, if the required on-chip resistance is small (50 � forexample), then Rint has to be much higher in order to savepower and to create a high enough VBr for adequate com-parison with VB. Otherwise if Rint is chosen to be 50 �, thecurrent needed to generate VBr will be significantly higher,and accuracy will also suffer due to the significant mismatcherror in current mirrors with large mirroring ratio. The de-signer has to be careful to design Rint and all the resistors inthe resistor block to have wide enough dimensions and arelaid out in a close proximity to guarantee that all of themare affected by the same relative magnitude with processvariation even though their values are different. Using polyresistors will significantly improve the accuracy of the tun-ing due to the good matching characteristics of poly resistors(versus well resistors for example). Also using a unit resistorto implement Rint and all the other resistors in the resistorblock will improve the accuracy even further. Yet, significantarea penalty will have to be paid for using poly resistors aswell as the concept of unit resistors. Therefore the designerhas to reach a compromise between accuracy and area.

4. Applications

Integrating transmission line terminations of high speed wireline transceivers has very attractive advantages. First, it min-imizes the number of passive components on the printedcircuit board, which leads to smaller boards and less cost.Second, in high speed systems, the termination resistors haveto be implemented as close as possible to the chip, whichsignificantly complicates the board layout. Integrating thetermination resistors eliminates this difficulty. Third, as datarates become higher, the effect of the package parasiticsbecomes more significant on the off-chip terminations tothe extent that integrating those terminations might be theonly way to achieve adequate performance. Yet, integrat-ing those terminations is a challenge due the loose accuracyof on-chip resistors, which will lead to high reflection co-efficient especially at fast data rates [14, 17]. Thus mosthigh speed transceivers require a minimum accuracy for ad-equate performance. Many techniques exist in the literaturefor implementing accurate termination resistors. Some tech-niques use purely active devices with an analog tuning loopto implement the required terminations as in [5, 18]. The im-plemented resistors usually suffer from linearity, range, andnoise limitations, in addition to the disadvantages of using

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analog tuning as discussed earlier in the introduction. Othertechniques use purely active devices along with a digital tun-ing loop to implement the required terminations as in [19].Those techniques, even though have the advantage of digi-tal tuning, yet, the terminations are still implemented usingpurely active devices, therefore, linearity, range, and noiselimitations still exist. Other techniques use a mixed combi-nation of active elements and passive on-chip resistors alongwith an analog tuning loop as in [4, 14]. Even though thosetechniques achieve better linearity than the purely active ap-proach, yet they still suffer from range and noise limitationssince the active elements still represents a significant portionof the implemented resistance, in addition to the disadvan-tages of analog tuning.

The proposed technique, which has the advantages of dig-ital tuning, better linearity (almost as good as a passive on-chip resistor), better noise performance, and wider operationrange was used to implement on-chip transmission line ter-minations for two high-speed wire line transceivers. Thefirst transceiver operates at 480 Mbps and has only one port.Thus, it requires one pair of terminations (2 resistor blocks).The second transceiver operates at 1.65 Gbps and has 8ports. Thus, it requires 8 pairs of terminations (16 resistorblocks).

4.1. The 480 Mbps transceiver

The transceiver specifications require two single-ended ter-mination resistors. Each resistor is 45 � with an accuracybetter than ± 10%. For this transceiver, Cmax was chosen tobe 8.67% in order to give a 1.33% margin to account for anypossible mismatch errors. Process characterization showedthat the maximum change from the nominal value for on-chip silicide-block poly resistors is ± 25% from the nom-inal value including variations due to temperature changesas well, which implied that Dmax should be 25%, but forextra margin, Dmax was chosen to be 26%. Using Eq. (1), thenumber of parallel resistors needed to achieve this accuracywas found to be n = 4, therefore, and by using in equalities8 to 10, the range of values of each resistor in the resistorblock was calculated, and is shown in Table 1. As discussedbefore, since the average value of the range allowed for eachresistor gives the maximum margin, the average value wassimply used as the nominal value for each resistor. Notehow the modulating resistors R1 through R4 are order ofmagnitude higher than the required total resistance (45 �).Since the values in Table 1 show the total resistance, theresistance of the switches has to be accounted for. Hence,the total resistance is divided between the switch and an ac-tual silicide-block poly resistor, where the switch resistancewas designed to be around 10% of the total resistance. Notethat the contribution of the switches to the total resistance ofthe resistor block will be even much less (less than 2%). Ta-

Table 1 Range of values the resistors in the resistor block can take forimplementing 45 � ± 8.75% terminations for the 480 Mbps transceiver

Resistor Minimum (�) Maximum (�) Average (�)

R0 56 59 57.5R1 374 806 590R2 323 323 323R3 238 564 401R4 262 953 607.5

Table 2 Values of the resistors in the resistor block divided betweenswitches and silicide-block poly resistors for the 480 Mbps transceiver

ResistorSilicide-blockresistance (�)

Switchresistance (�)

Totalresistance (�)

R0 57.5 N/A 57.5R1 531 59 590R2 290.7 32.3 323R3 360.9 40.1 401R4 546.75 60.75 607.5

ble 2 shows the resistance of each silicide-block poly resistoralong with the switch resistance. In the implementation ofthis transceiver, accurate biasing currents were needed any-way, hence, a band-gap circuit and an off-chip resistor Rext

were readily available.Therefore, the output of the band-gap circuit was used as thesource of VB , while Rext was chosen to be 6.3 K�. The mir-roring factor K was simply chosen to be unity, which makesthe nominal value of Rint 6.3 K� as well. Each resistor in theresistor block as well as Rint was checked under nominal con-ditions and temperature range from − 40 to 125◦C to makesure that the relative magnitude change in the value of eachresistor with temperature variations is less than ± 8.67%.That was easy to achieve due to the low temperature coeffi-cient of silicide-block poly resistors. The reference generatorresistors were calculated using Eq. (18) with Rrt chosen tobe 6.3 K�. Rr0 was found to be 5.208 K�, while the restof the resistors were found to be all equal to 546 �. Sincefor this application the tuning time was not critical, the con-trol matrix was implemented using a single comparator anda state machine rather than the flash architecture shown inFig. 5. Also the current mirror in Fig. 3 was implementedusing a low-voltage cascode. Since there is only two iden-tical resistor blocks implemented, they were laid out in thesame orientation and in a close proximity to each other and toRint as well, in order to minimize any mismatch errors. Theswitches were implemented using NMOS transistors, andeach resistor block occupied a total area of 206 µm2, whileRint occupied an area of 176 µm2. The reference generatorincluding the resistors as well as the Op-amp and the sourcefollower transistor occupied an area of 3229 µm2, whilethe comparator occupied an area of 6545 µm2. The totalarea of the complete design including the terminations, the

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RE

SIS

TAN

CE

(O

hm

s)

41.24

41.25

41.26

0.0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7

RE

SIS

TAN

CE

(O

hm

s)

44.79

44.8

44.81

RE

SIS

TAN

CE

(O

hm

s)

48.81

48.82

48.83

VOLTAGE ACROSS RESISTANCE (V) /3.3 (V)

Fig. 7 The linearity performance of the implemented resistance

reference generator, and the control matrix represented about3.6% of the complete transceiver. Simulations were done us-ing different process corners, temperature variations (−40to 125◦C), and different supply voltages (3.3 V ± 10%).Statistical simulations were also performed on the wholestructure. Statistical simulations take into account the er-rors due to mismatches between the resistors, current mirrormismatches, the offset introduced by the op-amps and thecomparators in the control matrix, and process variations.All the previous simulations were done taking into accounta ± 1% error in Rext. Simulation results showed that the to-tal resistance of the resistor block is well controlled within41.25 � and 48.82 �, with a nominal value of 44.8 �, whichis about ± 8.5% from 45 �. The total power consumed bythe calibration procedure was around 1.27 mW, and it wasperformed only during the start up of the transceiver, andrepeated every time the transceiver goes through a reset pro-tocol, otherwise it was otherwise disabled. This design wasimplemented on a standard 0.18 µm technology and mea-surements were performed on the design for different processcorners. The resistance was measured at different voltage lev-els up to 70% of the 3.3 V supply voltage ( ≈ 2.3 V), and themaximum error from the resistance value measured at themiddle of this range (35% of the 3.3 V supply ≈ 1.1 V) wasfound to be within ± 0.017%, which demonstrate the highlylinear performance of the resistor block over a wide voltagerange. Table 3 shows the measurement results of the imple-mented resistors, which align very well with the simulation

results. Figure 7 shows the linearity error of the implementedresistance.

4.2. The 1.65 Gbps transceiver

The transceiver specifications required the termination re-sistors to be 50 � with an accuracy better than ± 10% inthe value of the termination resistors. For this transceiver

Table 3 Measured resistance implemented using the proposed archi-tecture

− 3σ Mean +3σ Error from 45 �

Fast process 42.17 � 45.41 � 48.65 � − 6.3% to + 8.1%Nominal process 42.71 � 45.77 � 48.83 � − 5.1% to + 8.5%Slow process 43.11 � 45.81 � 48.51 � − 4.2% to + 7.8%

Table 4 Range of values the resistors in the resistor block can take forimplementing 50 � ± 5% terminations for the 1.65 Gbps transceiver

Resistor Minimum (�) Maximum (�) Average (�)

R0 63.33 65.63 64.48R1 750.06 1467.16 1108.61R2 673.94 1366.23 1020.08R3 642.62 1420.44 1031.53R4 610.00 610.00 610.00R5 475.00 1050.00 762.50R6 541.59 1685.53 1113.56R7 499.74 1544.06 1021.90R8 481.91 1609.12 1045.52

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though, and since it had 8 different ports, the required 16termination resistors could not be implemented in a closeproximity to each other, in fact, they were scattered acrossdifferent locations on the chip. Therefore, and as discussedbefore, there were two approaches to implement the tuning.The first approach is to tune each pair of termination resistorsindividually, which requires that each termination resistorspair has to have its own Rint as well as its own control ma-trix, and consequently consume more area and power. Thesecond approach is reduce the value of Cmax, i.e. tune to atighter accuracy in order to give more margin to account forthe scattered locations of the termination resistors pairs, anduse the same Rint and control matrix for all 8 terminationresistors pairs. In order to achieve that, Cmax was chosen tobe 5% in order to give a 5% margin to account for the scat-tered locations of the terminations. Process characterizationshowed that the maximum change from the nominal valuefor on-chip silicide-block poly resistors is ± 25% from thenominal value including variations with temperature, thusDmax was chosen to be 25%. Note that Dmax was not chosento be higher than 25 since the reduction in Cmax (5%) wasenough margin. Again using Eq. (1), the number of parallelresistors in each resistor block needed to achieve this accu-racy was found to be n = 8, and by using inequalities 8to 10, the range of values each resistor in the resistor blockwas calculated and is shown in Table 4. Again, the averagevalue of the range allowed for each resistor gives the maxi-mum margin, and was simply used as the nominal value foreach resistor (note the relatively high value of the modulatingresistors). The division between silicide-block resistors andthe switches was chosen to be 10% and is shown in Table 5shows the values of the resistors and the switches. As in the480 Mbps transceiver presented earlier, a band-gap circuitand an off-chip resistor Rext were readily available, thus,they were used. The rest of the design procedure used in the480 Mbps transceiver was also used including the same valueof Rext , Rint , K , and Rrt . Using Eq. (18) with Rrt chosen tobe 6.3 K �. Rr0 was found to be 5.04 K �, while the rest of

Table 5 Values of the resistors in the resistor block divided betweenswitches and silicide-block poly resistors for the 1.65 Gbps transceiver

Resistor Silicide-blockresistance (�)

Switchresistance (�)

Total resistance(�)

R0 65 N/A 65R1 997.2 110.8 1108R2 918 102 1020R3 928.8 103.2 1032R4 549 61 610R5 686.7 76.3 763R6 1002.6 111.4 1114R7 919.8 102.2 1022R8 941.4 104.6 1046

the resistors were found to be all equal to 315 �. The designwas implemented on a 0.13 µm technology, and the samesimulations performed on the 480 Mps transceiver were alsoperformed for this transceiver with − 40 to 125◦C temper-ature range, different supply voltages (3.3 V ± 10%), and± 1% error in Rext . Simulation results showed that the totalresistance of all resistor blocks (16 total) is well controlledwithin 46.76 � and 53.26 �, which is about ± 6.5% from50 �. Note that the ± 6.5% includes only the short rangemismatches between the resistor blocks (assuming they arelaid out in close proximity). Taking into account that the re-sistor blocks are scattered across the chip, a 1% more loss inaccuracy is roughly estimated.

5. Conclusion

A digital adaptive technique to provide a tight control overthe value of on-chip resistors was proposed. The techniqueuses a single off-chip resistor as a reference and does not re-quire accurate voltage reference. It could be used as a mastercalibrator for several, different valued on-chip resistors evenif they are scattered around the chip. The accuracy of the pro-posed technique is limited by the accuracy of the referenceresistor and mismatch errors. The architecture maintains lownoise, high linearity, wide voltage range, and high speedperformance of the implemented resistance. This paper de-velops, in addition to the concept, a mathematical way thatwill make the whole technique simple, fast, and practical.Transmission line terminations for two high speed wire linetransceivers (480 Mbps, and 1.65 Gbps) that required ± 10%accuracy were implemented using the proposed architecture.Simulations and measurements results show adequate perfor-mance across process, temperature, and supply voltage. Thetechnique could be used to design accurate on-chip resistorsfor different applications like on-chip terminations, filters,oscillators, and in most applications that requires accurateresistors.

References

1. M. Ismail and T. Fiez, Analog VLSI Signal and InformationProcessing, McGraw-Hill, New York, 1994.

2. T.J. Gabara and S.C. Knauer, “Digitally adjustable resistors inCMOS for high-performance applications.” IEEE J. Solid-StateCircuits, vol. 27, pp. 1176–1185, 1992.

3. A. DeHon, T. Knight, Jr., and T. Simon, “Automatic impedancecontrol.” IEEE International Solid-State Circuits Conference,Digest of Technical Papers, vol. 283, pp. 164–165, 1993.

4. T. Gabara, W. Fischer, W. Werner, S. Siegel, M. Kothandaraman,P. Metz, and D. Gradl, “LVDS I/O Buffers with a ControlledReference Circuit.” Proceedings of the 10th Annual IEEEInternational ASIC Conference, pp. 311–315, 1997.

5. H. Song, “Dual mode transmitter with adaptively controlledslew rate and impedance supporting wide range data rates.”

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Proceedings of the 14th Annual IEEE International ASIC/SOCConference, pp. 321–324, 2001.

6. M. Ismail, S.V. Smith, and R.G. Beale, “A new MOSFET-Cuniversal filter structure for VLSI.” IEEE J. Solid-State Circuits,vol. SC-23, pp. 183–194, 1988.

7. S. Sakurai and M. Ismail, “A CMOS square-law programmablefloating resistor independent of the threshold voltage.” IEEETrans. Circuits Syst. II, vol. 39, pp. 565–574, 1992.

8. R. Schaumann, M.S. Ghausi, and K.R. Laker, Design ofAnalog Filters, Passive, Active RC, and Switched-Capacitor,Prentice-Hall, Englewood Cliffs, NJ, 1990.

9. S. Sakurai, M. Ismail, J.-Y. ves Michael, E. Sanchez-Sinencio, andR. Brannen “A MOSFET-C variable equalizer circuit with simpleon-chip automatic tuning.” IEEE Journal of Solid-State Circuits,vol. 27, no. 6, 1992.

10. K. Nagaraj, “New CMOS floating voltage-controlled resistor.”Electronics Letters, vol. 22, pp. 667–668, 1986.

11. S.P. Singh, J.V. Hanson, and J. Vlach, “A new floating resistorfor CMOS technology.” IEEE Trans. Circuits. Syst., vol. 36, pp.1217–1220, 1989.

12. M. Steyaert, J. Silva-Martinez, and W. Sansen, “High-frequencysaturated CMOS floating resistor for fully-differential analog sig-nal processors.” Electronics Letters, vol. 27, pp. 1609–1611, 1991.

13. B. Razavi, Design of Analog CMOS Integrated Circuits,McGraw-Hill, New York, 2001.

14. H. Conrad, “2.4 Gbit/s CML I/Os with integrated line terminationresistors realized in 0.5/spl mu/m BiCMOS technology.” Proceed-ings of the Bipolar/BiCMOS Circuits and Technology Meeting,pp. 120–122, 1997.

15. D.A. Johns and K. Martin, Analog Integrated Circuit Design, JohnWiley & Sons, New York, 1997.

16. F. Larsen, M. Ismail, and C. Abel, A versatile structure for on-chipextraction of resistance matching properties. IEEE Transactions onSemiconductor Manufacturing, vol. 9, no. 2, pp. 281–285, 1988.

17. I. Novak, “Modeling, simulation, and measurement considerationsof high-speed digital buses.” Instrumentation and measurementTechnology Conference, pp. 1068–1074, 1992.

18. T.J. Gabara, “On-chip terminating resistors for high-speedECL-CMOS interfaces.” Proceedings of the Fifth Annual IEEEInternational ASIC Conference and Exhibit, pp. 292–295, 1992.

19. K.-H. Koo, J.-H. Seo, M.-L. Ko, and J.-W. Kim, “Digitally tunableon-chip resistor in CMOS for high-speed data transmission.”ISCAS 2003. Proceedings of the 2003 International Symposiumon Circuits and Systems, vol. 1, pp. 185–188, 2003.

Ayman A. Fayed was born Egypt, in 1975.He received the B.Sc. degree from the Elec-tronics and Communications Department,Cairo University, Cairo, Egypt in 1998, andthe M.Sc. and Ph.D. degrees from The OhioState University, Columbus, in 2000 and2004 respectively. Since 2002, he has beenwith Texas Instruments Inc. as an analog andmixed-signal circuit designer. He has been akey contributor to TI’s high-speed wire line

transceivers product line. He has been awarded two US patents in thefield. His research interests include mixed-signal CMOS circuit designfor high-speed wire line transceivers, adaptive equalization, and powermanagement systems.

Mohammed Ismail has over 20 yearsexperience of R&D in the fields of analog,RF and mixed signal integrated circuits. Hehas held several positions in both industryand academia and has served as a corporateconsultant to nearly 30 companies in theUS, Europe and the Far East. His currentinterest lies in research involving digitallyprogrammable/configurable fully integratedradios with focus on low voltage/low power

first-pass solutions for 3G and 4G wireless handhelds. He publishesintensively in this area and has been awarded 11 patents. He hasco-edited and coauthored several books including a text on AnalogVLSI Signal and Information Processing, (McGraw Hill). His last book(2004) is entitled CMOS PLLs and VCOs for 4G wireless, Springer.He co-founded ANACAD Egypt (now part of Mentor Graphics,Inc.) and Spirea AB, Stockholm (now Firstpass SemiconductorsAB), a developer of CMOS radio and mixed signal IPs for handheldwireless applications. Dr. Ismail has been the recipient of severalawards including the US National Science Foundation PresidentialYoung Investigator Award, the US Semiconductor Research CorpInventor Recognition Awards in 1992 and 1993, and a Fulbright/Nokiafellowship Award in 1995. He is the founder of the InternationalJournal of Analog Integrated Circuits and Signal Processing, Springerand serves as the Journal’s Editor-In-Chief. He has served as AssociateEditor for many IEEE Transactions, was on the Board of Governors ofthe IEEE Circuits and Systems Society and is the Founding Editor of"The Chip" a Column in The IEEE Circuits and Devices Magazine. Heis a Fellow of IEEE. He obtained his BS and MS degrees in Electronicsand Communications from Cairo University, Egypt and the PhD degreein Electrical Engineering from the University of Manitoba, Canada.

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A digital calibration algorithm for implementing accurate on-chip resistors