A DC-Link Voltage Self-Balance Method for a Diode-Clamped

IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 28, NO. 5, MAY 2013 2125

A DC-Link Voltage Self-Balance Methodfor a Diode-Clamped Modular Multilevel Converter

With Minimum Number of Voltage SensorsCongzhe Gao, Xinjian Jiang, Yongdong Li, Member, IEEE, Zhe Chen, Senior Member, IEEE, and Jingyun Liu

Abstract—Voltage balance issue of dc-link capacitors is very im-portant for applications of a cascade multilevel converter or amodular multilevel converter. In this paper, a novel diode-clampedmodular multilevel converter (DCM2 C) topology is proposed anda power feedback control method is developed. With the developedcontrol strategy, the proposed diode-clamped circuit becomes acontrollable closed loop which enables the capacitor voltages to beclamped by low power rating clamping diodes. The proposed topol-ogy and control strategy has quicker response and requires muchfewer voltage sensors than the normally used traditional method;therefore, the system performance improvement and cost reductionare expected. Based on the proposed DCM2 C, a novel N+1-levelcascade multilevel topology is proposed for a cascade active powerfilter (CS-APF). The simulation and experimental results from theCS-APF have demonstrated and verified the effectiveness of theproposed novel topology and control method.

Index Terms—Capacitor voltage balance, cascade active powerfilter (CS-APF), diode-clamped modular multilevel converter(DCM2 C), minimum number of voltage sensors.

I. INTRODUCTION

M EDIUM- and high-voltage application of power elec-tronic converters is growing, for instance, an active

power filter (APF) which is an ideal choice for power condition-ing [1]–[3]. A high switching frequency is normally required forsuch electronic converters to achieve good performance, suchas fast response, good filtering, and low harmonics; however,the high switching frequency may limit the capacity of a nor-mal two-level converter due to the power loss. A multiple con-verter configuration may be an effective solution for high-powermedium-voltage applications [4]–[7], but a bulky transformer isusually required. Recently, the topology of multilevel converter

Manuscript received February 24, 2012; revised June 2, 2012; accepted July26, 2012. Date of current version November 22, 2012. This work was supportedby the National 863 Plan 2007AA05Z227, China. Recommended for publica-tion by Associate Editor B. Ozpineci.

C. Gao was with the Department of Electrical Engineering, Tsinghua Uni-versity, Beijing 100084, China, He is now with the Automation School, BeijingInstitute of Technology, Beijing 100081, China (e-mail: [email protected]).

X. Jiang and Y. Li are with the National Key Laboratory of Power Systems,Department of Electrical Engineering, Tsinghua University, Beijing 100084,China (e-mail: [email protected]; [email protected]).

Z. Chen is with the Department of Energy Technology, Aalborg University,DK-9220 Aalborg, Denmark (e-mail: [email protected]).

J. Liu is with the Automation School, Beijing Union University, Beijing,100101, China (e-mail: [email protected]).

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TPEL.2012.2212915

have become popular in medium-voltage applications, becauseof its features of simple structure, modularity, and transformer-less. In particular, the multimodular converter based on half-bridge or full-bridge topology is a good solution for medium-/high-voltage applications, including STATCOM, APF, HVDC,and so on [8]–[30]. However, the dc-link capacitors are floatingin either a full-bridge cascade converter or a half-bridge cas-cade converter. Due to the difference of parasitic parametersbetween cells, the nonideal drive pulses, and so on, the dc-linkcapacitor voltages may become unbalanced if a specifically de-signed control method is not in place. Some capacitor voltagebalance control algorithms are studied previously [21]–[30].These methods may be classified into the following cate-gories: 1) switching patterns rotated (SPR) methods [21]–[23];2) fundamental voltage vector regulation (FVVR) methods[24]–[26]; and 3) direct duty cycle (DDC) control methods[27]–[30].

SPR may only partially remove the imbalance of the capacitorvoltages; therefore, it is usually used as an auxiliary method. Viaadjusting the modulation index and phase angle to balance thecapacitor voltages, FVVR is commonly used for STATCOM, ofwhich the current is a sinusoidal wave with line frequency. Butthe power adjustment capability (between cells) is limited whenFVVR is used in harmonics suppression applications. DDC canbe used for both var compensation and harmonics suppression.Yet, the power control depends on the current of the main cir-cuit greatly, and is very weak especially when the current islow. Besides, the duty cycle adjustment has to be calculatedfor each cell in each control cycle and the calculation effortis significant when the number of the cells is large. The volt-age rating of the semiconductor devices, such as the insulatedgate bipolar transistor (IGBT), is usually not very high (1700 or3300 V is the most popular choice for commercial applications).Consequently, the number of cells is very large in medium- orhigh-voltage applications, which results in heavy calculation forcontrolling each cell’s capacitor voltage; then, the control cy-cle would be prolonged and the system dynamic performancewould be reduced. In APF applications, a control cycle of lessthan 100 μs is normally required for good performance. Thetraditional methods usually require a large number of voltagesensors and communication cables or optical fibers which willincrease the system complexity and cost.

By adding an auxiliary circuit to each cell for exchangingenergy between cells, capacitor voltage balance can also berealized [31]. However, such an auxiliary circuit usually requiresan extra inverter and a control circuit, maybe also a transformer

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2126 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 28, NO. 5, MAY 2013

Fig. 1. Two basic topologies of a half-bridge cell.

if isolation is required, which will significantly increase thecircuit complexity and cost.

A novel simple diode-clamped modular multilevel converter(DCM2C) topology is proposed in this paper. It is based on thecascade connection of half-bridge cell converters. Via adding aclamping diode to each cell’s dc bus, the capacitor’s voltage ofone cell could be clamped by the two neighboring cells whenthe circuit works. At the same time, an energy feedback cir-cuit is used for connecting the top and bottom cells, so that aclosed loop clamping circuit is formed. In this topology, onlythe top and bottom cells need the voltage sensors, which sig-nificantly reduce the required number of sensors. Furthermore,a performance enhancing control algorithm is implemented inthe controller to ensure a quick response.

The proposed novel topology may be used in any converterwith half-bridge cascade topology. A novel three-phase DCM2Ctopology with star configuration which can be used for var com-pensation or harmonics suppression is presented for discussionin this paper. There are 3(N−1) diode-clamped cells and onecommon cell in the topology. A total of four dc-link voltagesensors are needed for the three top cells and the common cell.The control of the three-phase DCM2C applied as a CS-APF isdiscussed in this paper. The effectiveness of the novel topologyand control method is validated by simulation and experiment.

This paper is organized as follows. Section II introduces thebasic structure and principles of the novel DCM2C topology.The three-phase topology of a DCM2C is presented in SectionIII, and the control methods of a DCM2C as a CS-APF aredescribed in Section IV. In Section V, the simulation and exper-iment verification is discussed. The conclusions are presentedin Section VI.

II. TOPOLOGY AND PRINCIPLES OF A DCM2C

A. Topology of a DCM2C

The two basic topologies of a half-bridge converter cell areshown in Fig. 1, where the dc-link capacitor is completely float-ing.

The two proposed DCM2C topologies (cell topology) areshown in Fig. 2(a) and (b). Each topology is a two-port network.In Fig. 2(a), the cathode of the clamping diode Dj is connectedto the positive polarity of the capacitor, while the diode’s anodeis connected to the capacitor’s negative polarity in Fig. 2(b). xand x’ are the terminals for connecting the neighboring cells ondc side, while y and y’ are the terminals on ac side.

Fig. 3(a) shows an upward clamping topology (UCT) of aDCM2C. If udj < udj+1 (udj is the voltage of the capacitor Cdj

and udj+1 is the voltage of Cdj+1), there will be a current iacj

flowing through Dj when the switch Sj+12 is ON (neglecting

Fig. 2. Topologies of the proposed diode-clamped half-bridge cell.

Fig. 3. Voltage-clamped switch mode of the two topologies.

the voltage drop of the diode and the saturation voltage of theswitch), as shown in Fig. 3(a). Then, udj will rise and udj+1 willdrop until udj = udj+1 . If udj ≥ udj+1 , the diode Dj will keepOFF. Thus, the capacitor voltage relationship is ud1 ≥ ud2 ≥. . . ≥ udN . ud1 is the dc voltage of the top cell, and udN is thedc voltage of the bottom cell.

Consequently, if ud1 could be clamped at the same level asudN , all capacitors would have the same voltage. Fig. 3(b) showsa downward clamping topology (DCT), which uses the similarprinciple to the UCT’s. If udj+1 < udj , Cdj+1 will be clampedby Cdj when Sj1 is ON, as shown in Fig. 3(b).

Now, the key point is to realize ud1 = udN . The followingpart presents a method to solve the problem by using an energyfeedback circuit to form a closed voltage clamping loop withthe clamping diodes. Several energy feedback topologies areproposed. Fig. 4(a) shows an energy feedback topology basedon an auxiliary full-bridge inverter (AFBI) which shares the dcbus with the top cell of the UCT (or with the bottom cell of theDCT). The ac side of the AFBI is connected to the primary ofan isolation transformer Tac . The secondary of Tac is connectedwith a rectifier that shares the dc bus with the bottom cell ofthe UCT (or with the top cell of the DCT). The winding turningratio of Tac is 1: wT . When the AFBI works as a square waveac inverter (The output voltage of the inverter is uac .), a squarewave voltage with the same amplitude as uac (wT = 1) will beinduced at the secondary side of Tac . The induced ac voltage isconverted into a dc voltage by the rectifier. If the dc voltage ofcell N is lower than that of cell 1, energy will be transmittedfrom Cd1 to CdN via the feedback circuit. Then, udN will riseand ud1 will drop, so ud1 and udN will be equalized by thefeedback circuit. Therefore, a closed voltage clamping circuitis realized. Considering the leakage inductance of Tac and thevoltage drop of the switches, wT should be a little larger than 1,and the output power of the auxiliary circuit can be controlled

GAO et al.: DC-LINK VOLTAGE SELF-BALANCE METHOD FOR A DIODE-CLAMPED MODULAR MULTILEVEL CONVERTER 2127

Fig. 4. Three kinds of feedback topologies. (a) Circuit based on AFBI (UCT).(b) Circuit based on AHBI (UCT). (c) Circuit based on SHI (UCT).

by adjusting the pulsewidth modulation (PWM) duty cycle ofcell 1.

The AFBI needs four active switches, while an auxiliary half-bridge inverter (AHBI) needs only two active switches as shownin Fig. 4(b), and the winding turning ratio of the transformer is 1:wT = 1: 2 (Similarly, wT > 2 in practical application). Besides,a capacitor Cac is connected to the primary winding of Tac inseries to block the dc component.

DC-link voltage unbalance is mainly caused by the loss dif-ference between cells and the nonideal drive pulses, and such

TABLE ISUMMARY OF THREE AUXILIARY CIRCUITS

unbalance could be removed with much lower power comparingwith that of the main circuit. Then, another feedback topologywith a simpler structure is proposed, as shown in Fig. 4(c). Thistopology requires no extra inverters or active switches; instead,the auxiliary circuit shares the two active switches with the topcell (bottom cell for DCT). The feedback circuit is composed ofa transformer Tac and a rectifier connected with the secondaryof Tac . The primary of Tac is also connected with a capacitorCac for dc component blocking, and the rectifier shares one dcbus with the bottom cell (top cell for DCT).

The dc component and the low frequency components canbe blocked by Cac . Usually, the frequency of the modulatedwave of PWM for the main switches is low. If the feedbackcircuit works at the frequency of the modulated wave, the sizeof the transformer Tac and capacitor Cac would be quite large.Thus, the designed operating frequency of Tac is the same as theswitching frequency (or the carrier frequency of PWM) of themain switches. So, the size of Tac and Cac can be significantlyreduced. The core of Tac should be designed with antisaturationcapability. The winding ratio (1:wT ) of Tac is 1:2.

The advantages and disadvantages of the three auxiliary cir-cuit topologies discussed previously are summarized in Table I.

The working principles of the auxiliary circuits are similar,and the following part will focus on the SHI which is applied inthe three-phase DCM2C as a CS-APF in this paper.

B. Analysis of the Auxiliary Circuit (SHI)

The function of the feedback circuit is to transmit energyfrom cell 1 to cell N . The switching frequency component ofthe output voltage uac of cell 1 should be transmitted from theprimary of Tac to the secondary, while the low frequency com-ponents should pass Lm easily and be blocked by the capacitorCac . Lm is the magnetic inductance of Tac .

The equivalent circuit of the auxiliary circuit (SHI) is shownin Fig. 5. U ac , UC ac , UT 1 , UT 2 , Iac1 , and Iac2 are all phasors.Lσ1 and Lσ2 are the leakage inductance of the primary andsecondary, respectively. U ,

T 2 , I ,ac2 , and L,

σ2 are referred to theprimary.

The total leakage inductance is Lσ = Lσ1+ L’ σ2. It shouldbe designed as Lσ ≤ 0.1Lm . Then, the no-loading voltage of


Fig. 5. Equivalent circuit of the auxiliary circuit (SHI).

Tac UT 1 and the capacitor voltage UC ac may be expressed as

UT 1 ≈ U acωLm

ωLm − (1/ωCac), UC ac ≈ −Uac(1/ωCac)

ωLm − (1/ωCac)(1)

where ω is the frequency. The following expression should besatisfied when the circuit is designed:

ωsLm ≥ 10ωsCac

(2)

where ωs is the switching frequency. Then, UT 1 s ≈ U ac s .UT 1 s and U ac s are the switching frequency components ofUT 1 and U ac , respectively. Furthermore, it is easy to satisfythe following expression:

10ωf Lm ≤ 1ωf Cac

. (3)

Thus, UC ac f ≈U ac f . UC ac f and U ac f are the fundamen-tal components of UC ac and U ac , respectively. ωf is the fun-damental frequency (frequency of the modulated wave). WhenTac is loaded, there will be switching frequency ripples ΔuC ac

on Cac , and the capacitor Cac should be designed to satisfy thefollowing expression:

ΔuC ac ≤ 0.1ud1 . (4)

According to (1)–(4), the relationship of uC ac , uac , and uT a1could be shown in Fig. 6. ucar is the carrier waveform with theamplitude of Umcar and um is the modulated waveform withthe amplitude of Umm .

The capacitor voltage uC ac approximately equals to the sumof the fundamental component and dc component, as shown in(5). Equation (6) is the control aim

uC ac ≈ Dud1 (5)

udN ≈ ud1 . (6)

D is the duty cycle of the drive signal of S11 which is inter-locked with S12 . Then, the expression of the current iac2 can bederived, with which the output power of the auxiliary circuit canbe calculated approximately. Since the switching frequency ismuch higher than the fundamental frequency, um and uC ac canbe taken as constant in a switching cycle. Thus, the expressionof iac2 in a switching cycle can be derived, as shown in Fig. 7.Ts is the switching cycle. During time 0–t1 , uT 1 is

uT 1 = ud1 − uC ac ≈ ud1 − Dud1 , (0 ≤ D < 0.5). (7)

Fig. 6. Relationship of the voltages uC ac , ua c, uT a1 and the currentsiac1 , iac2 .

Fig. 7. Relationship of the output voltage uac and the current iac2 in thesteady state of the SHI.

The secondary voltage of Tac (uT 2) can be expressed asfollows if the secondary circuit is open:

uT 2 ≈ wT uT 1 = wT (ud1 − Dud1) (8)

0≤D<0.5,wT =2−−−−−−−−−−−→uT 2 > ud1 = udN . (9)

Since the secondary circuit is closed, the current iac2 will risefrom time 0 to t1 according to the following expression:

iac2(t) ≈1

w2T Lσ

∫ t

0(wT uT 1 − udN )dt

Equation(6),(7)−−−−−−−−−−−→ =

ud1

w2T Lσ

∫ DTs

0[wT (1 − D) − 1]dt,

(0 ≤ t ≤ t1).

(10)

From time t1 to t2 , uac becomes zero, and uT 1 is

uT 1 = 0 − uC ac ≈ −Dud1 . (11)

At the same time, the current iac2 will drop, and the expressionis

iac2(t) ≈−ud1

w2T Lσ

∫ t

t1

(wT D + 1)dt, (t1 ≤ t ≤ t2). (12)


The rising rate δi1 of iac2 during time 0 to t1 and the fallingrate δi2 during time t1 to t2 are

δi1 =ud1 [wT (1 − D) − 1]

w2T Lσ

, δi2 =ud1(wT D + 1)

w2T Lσ

. (13)

When D < 0.5, δi1 < δi2 . Thus, iac2 will fall to zero beforethe end of each cycle and will start from zero at the start of eachcycle (iac2 = 0, t = 0) in the steady state. Then, the expressionof iac2 could be obtained

iac2(t) ≈ud1 [wT (1 − D) − 1]

w2T Lσ

t, (0 ≤ t ≤ t1). (14)

When D > 0.5, the case is similar, but D should be replacedby 1−D in the aforementioned expressions. Besides, iac2 ≈0, when D = 0, D = 0.5, or D = 1 (wT = 2, ud1 = udN ).The relationship between D and iac2 is shown in Fig. 6, whereuac = D·ud1 .

Thus, the integration of iac2 in a duty cycle can be expressedas follows:

∫ t2

0iac2(t)dt = S1 + S2 (15)

where S1 and S2 are the areas of the shadows (integration ofiac2) in Fig. 7. Thus, S1 :S2 = (t1− 0):(t2−t1) = δi2 :δi1 . Then,the following expression could be obtained:

∫ t2

0iac2(t)dt = S1 + S2 =

δi1 + δi2

δi2

∫ t1

0iac2(t)dt. (16)

The power is the product of voltage and current as follows:

P (t) = udN |iac2(t)| ≈ ud1 |iac2(t)| . (17)

The energy (ET s in a switching cycle Ts can be calculated,as shown in the following equations:

ET s =∫ Ts

0P (t)dt ≈ ud1

∫ t2

0|iac2(t)| dt

= ud1δi1 + δi2

δi2

∫ t1

0iac2(t)dt

=u2

d1

w2T Lσ

[1 +

wT (1 − D) − 11 + wT D

]

×∫ DTs

t=0[wT (1 − D) − 1]tdt

=u2

d1T2s D2 [wT (1 − D) − 1]

2wT Lσ (1 + wT D)(18)

wT =2−−−−−−→ =

u2d1T

2s D2(1 − 2D)

4Lσ (1 + 2D), (0 ≤ D < 0.5). (19)

The average power (PT s of SHI in a switching cycle is

PT s =ET s

Ts=

u2d1TsD

2(1 − 2D)4Lσ (1 + 2D)

. (20)

Fig. 8. Relationship of the energy PT s and the PWM duty cycle D.

Then, the maximum value of PT s could be obtained with thefollowing expression:

dPT s

dD=

d

dD

[u2

d1TsD2(1 − 2D)

4Lσ (1 + 2D)

]= 0 → D =

√5 − 14

.

(21)Similarly, D is replaced by 1−D when D ≥ 0.5. The rela-

tionship of PT s and D is given in Fig. 8, and max(PT s) can beused to design the parameters of SHI.

C. Design Rules of the Auxiliary Circuit (SHI)

Considering that the voltage unbalance between cells ismainly caused by the loss difference and the nonideal drivepulses, the required power for balance control is usually lowerthan 5% of the rated power Pcell . Thus, the current of the clamp-ing diode in the DCM2C is lower than 5% of the rated currentof the main circuit. However, 20% of the IGBT’s rated currentis chosen as the diode rated current for a reliable design. Ofcourse, the diode should be fast recovery diode and have thesame voltage rating as the IGBT’s.

The design of SHI is focused on the auxiliary capacitor Cacand the auxiliary transformer Lm ,Lσ .

According to (4), the design rules of Cac could be obtained

ΔuC ac =1

Cac

∫ Ts

0iac1(t)dt

≈ 1Cac

∫ Ts

0wT iac2(t)dt =

wT

ud1Cac

∫ Ts

0P (t)dt (22)

wT

ud1Cac

∫ Ts

0P (t)dt ≤ wT Ts max(PT s)

ud1Cac≤ 0.1ud1 (23)

Cac ≥ 20Ts max(PT s)u2

d1, (wT = 2). (24)

Similarly, the design of the leakage inductance Lσ can bebased on the following expression:

Equation(20)−−−−−−−−−→Lσ ≈ u2

d1TsD2(1 − 2D)

max(PT s)4(1 + 2D). (25)

Lm should satisfy the aforementioned expressions: (2), (3),and Lm > 10Lσ . Besides, the resonance frequency of Lm andCac should satisfy the following expression:

10ωf ≤ 1√Lm Cac

≤ 0.1ωs. (26)


Fig. 9. Topology of a three-phase converter based on DCM2 C (N = 2M ).

Similarly for Lσ

10ωf ≤ 1√LσCac

≤ 0.3ωs. (27)

According the aforementioned expressions, max(PT s) shouldbe confirmed first. In fact, the duty cycle D changes in a sinu-soidal way with t approximately, and the detailed analysis ofthe power is presented in Section IV. The power of SHI can bedesigned according to the following expression:

max(PT s) ≈ 1.2max(PT line), max(PT line) ≈ η · Pcell(28)

where Pcell is the rated power of a cell and PT line is defined by(39). η is approximately 3–5%.

The following section will present the topology of a three-phase DCM2C which can be applied in var compensation orharmonics suppression.

III. THREE-PHASE DCM2C WITH STAR CONFIGURATION

A. Three-Phase Converter Topology Based on DCM2C

Delta configuration and star configuration are two commonchoices for a cascade converter. Because the number of the cas-cade cells of the star configuration is smaller than that of the deltaconfiguration for the same voltage level application, the star con-figuration is chosen here for discussion. The proposed topologyof a three-phase DCM2C is shown in Fig. 9. It contains threephase arms for phase a, phase b, and phase c, respectively, with

the same structure. The three arms are connected to a commonneutral point. The converter is directly connected to a mediumvoltage network via three inductors without a transformer.

2M cells are connected in series in each phase arm, and di-vided into two parts: the positive part and the negative part,by which the positive and negative voltages are generated, re-spectively. Thus, the topology is a 2M+1-level converter. TheUCT is used for the cells in the positive part and the DCT forthe negative part; thus, the common-mode voltage at the neutralpoint (taking the ground or the neutral point of the network aszero potential) will be reduced for easing the insulation. The topcell of each phase arm is connected with the feedback circuit(SHI). The three bottom cells (or the common cell of the threephases) share a common dc bus which is also shared by thethree rectifiers of the feedback circuits. The common cell pro-vides energy exchange channels between the three phases whichis beneficial to the dc-link voltage balance among three phasesand also has the merits in reduction of the required number ofvoltage sensors. As a result, only four dc-link voltage sensorsare required, and placed at the top three cells and the bottomcell for the system control.

B. Efficiency Analysis of the Proposed Topology

There is no auxiliary circuit in the traditional cascade mul-tilevel topologies and the capacitor voltage balance control isdone by the software, while the proposed topology, DCM2C, isequipped with clamping diodes and there will be current flowing


TABLE IISUMMARY OF FOUR CASCADE TOPOLOGIES

through them. Thus, the efficiency of a DCM2C is a little lowerthan that of the traditional topology.

In fact, the current flowing through the clamping diodes andthe auxiliary circuit is much lower than the rated current ofthe main circuit. According to the analysis in Section II, thecapacitor voltage unbalance is caused by the loss differenceand the nonideal drive signals, and so on; thus, the power forequalizing the capacitors between two cells is usually not higherthan 5% of Pcell . Then, if the total power of the clamping circuitPe is 5% of the system’s rated power Pr and the efficiency ofthe clamping circuit is 90%, the loss Ploss e of the clampingcircuit could be calculated as follows:

Ploss e ≈ 0.05 × (1 − 0.9) × Pr = 0.5%Pr . (29)

In fact, the clamping circuit will not run at the maximumpower point all the time. Thus, the average loss of the clampingcircuit will be lower than (29). Therefore, the clamping circuithas little influence on the system efficiency in the steady state.

C. Summary of the Proposed Topology

Generally speaking, the proposed topology has the merits inthe following aspects:

1) the capacitor voltages of the dc link are self-balanced,and the capacitor voltage balance control is completelyindependent from the voltage and current of the maincircuit;

2) only four dc-link voltage sensors are required in the topol-ogy. The measurement and control circuit is simple;

3) the auxiliary circuit control algorithm is simple and takesup little time for calculation and the complex control al-gorithm can be implemented with this topology for highperformance;

4) the power rating of the clamping diodes and the feedbackcircuit is very low. Thus, it is of low cost;

5) since the power rating of the auxiliary circuit is low, it haslittle influence on the system efficiency.

Table II summarizes the differences of the cascade convertersbased on the proposed topology and the conventional topolo-gies, respectively. N+1 is the number of the cascade convertervoltage levels, and N is an even number.

The control of a DCM2C is presented in Section IV, and as atypical application, the converter is controlled as a CS-APF.

IV. CONTROL OF A DCM2C AS A CS-APF

Applied as a CS-APF, the proposed topology based onDCM2C (see Fig. 9) is discussed in the following aspects inthis section:

1) harmonic detection and compensation control;2) current loop control;3) DC-link voltage control: phase arm dc-link voltage control

and auxiliary clamping circuit control;4) modulation method.

A. Harmonic Detection and Suppression Control

Since the capacitor voltage balance is done by an auxiliarycircuit, the digital controller has more time to realize a complexcontrol algorithm, as Fig. 10 shows.

The harmonics suppression control includes a load currentfeed-forward control and a source current feedback control [32].In the feedback control loop, a selective harmonic detectionmethod based on bandpass filters is used to improve the con-trol precision with little influence on the stability. The sourcecurrents (isa , isb , isc) are transformed into αβ coordinates. i∗shα

and i∗shβ are the harmonic components of the source current. The


Fig. 10. Control scheme of a CS-APF based on DCM2 C.

controllers for the feedback control are two P regulators. C32and C23 are the Clarke transformation and the inverse Clarketransformation

C32 =

⎡⎢⎣

1 −12

−12

0√

32

−√

32

⎤⎥⎦ (30)

C23 =

⎡⎢⎢⎢⎢⎣

1 0

−12

√3

2

−12

−√

32

⎤⎥⎥⎥⎥⎦ . (31)

The harmonic detection method for feed-forward control isbased on the famous instantaneous reactive power theory foran improved dynamic response. The load currents (isa , isb , isc)are transformed into αβ coordinates (iLα, iLβ). iLα and iLβare then transformed into the positive-sequence pq coordinates(iLp+ , iLq+) where the positive-sequence fundamental com-ponents become dc components. The positive-sequence fun-damental components are filtered out by low-pass filters andsubtracted from iLp+ and iLq+ . iLα and iLβ are also trans-formed into the negative-sequence pq coordinates (iLp−, iLq−)where the negative-sequence fundamental components becomedc components and are filtered out by filters. The harmoniccurrent, iLhα (or iLhβ ), is obtained when iLα1− (or iLβ1−),the output of the inverse pq− transformation, is subtracted fromiLα+ (or iLβ+ ), the output of the inverse pq+ transformation.Thus, the harmonic detection of the load currents is realized.The outputs of the harmonic detection and control loop are thereference currents i∗ha , i∗hb , and i∗hc . C+ and C− in Fig. 10 are as

follows:

C+ =[

sinωt − cos ωt− cos ωt − sin ωt

], C− =

[cos ωt − sin ωtsinωt cos ωt

].

(32)

B. Current Loop Control Method

Deadbeat control which is easy to be realized by the digitalcontroller is used as the current controller. i∗F (i∗F a , i∗F b , i

∗F c)

is the reference current for CS-APF; i∗h (i∗ha , i∗hb , i∗hc) is the

harmonic reference current; and i∗P (i∗P a , i∗P b , i∗P c) is the active

power reference current generated by the dc-link voltage controlloop

i∗F = i∗h + i∗P . (33)

The phase voltage output of the converter is uF

(uF a , uF b , uF c), and the source voltage is us (usa , usb , usc).udj is the dc-link capacitor voltage. Then, the expressions ofdeadbeat control are

uF (k) =LF

Ts[i∗F − iF (k)] + us(k), i∗F = iF (k + 1) (34)

D = uF

/⎡⎣ M∑

j=1

(udj + udM +j )2

⎤⎦ (35)

×M∑

j=1

(udj + udM +j )2

= M × udav

≈ M

2(ud1 + udN ).

(36)

LF (LF a , LF b , LF c) is the inductance of CS-APF; Ts is thecontrol cycle; D is he duty cycle; udj (j = 1, 2,. . ., M) is the


Fig. 11. DC-link voltage control scheme.

cell voltages and udav is the average value of the dc-link voltageof a phase arm.

C. DC-Link Voltage Control

The dc-link voltage control includes the universal dc-linkvoltage control (or phase arm dc-link voltage control) and theauxiliary circuit control. Fig. 11 shows the universal dc-linkvoltage control scheme where u∗

d is the reference voltage, anduda , udb , and udc are, respectively, the sum of the dc-link voltagein the relevant arm of phases a, b, and c. Since only the topand bottom cells’ dc-link voltage is monitored by the voltagesensors, uda can be calculated by (37) approximately. G1 isthe gain in (37). Similarly, udb and udc can be calculated. Theerrors are the inputs of the proportional-integral regulators. Theoutputs of the regulators are multiplied by the phase-lockedloop signals. Thus, the outputs of the universal dc-link voltagecontrol are the active power reference currents (i∗P a , i∗P b , i

∗P c)

for each phase

uda =M∑

j=1

udj ≈ G1(uda1 + udN ) =M

2(uda1 + udN ). (37)

The dc bus of the common cell is shared by the three phases.Thus, certain amount of energy can be exchanged among thethree phases which is beneficial for the dc-link voltage balanceof the three phases.

The dc-link voltages of the cells are balanced by the auxil-iary clamping circuit, and the control principle is described asfollows (take phase arm a for example).

According to the analysis in Section II, the equalizing of thecapacitor voltages focuses on the control of the feedback circuit(SHI). The aim of the control is that the capacitor voltage of cell1 is clamped near to the capacitor voltage of cell N .

The output power of the feedback circuit (SHI) actuallychanges with the duty cycle D. Thus, the power control ofthe feedback circuit can be realized by adjusting the duty cycleof the top cell, and it should not affect the performance of themain circuit. In fact, the major low-frequency component ofua1 (uac in Section II) is the line frequency component which isdetermined by the modulated wave (see Fig. 16). So, the energyET line output by the feedback circuit in a line voltage cycle Tlineis

ET line =∫ T l i n e

0P (t)dt. (38)

Fig. 12. Relationship between the energy ET L in e and Mk .

Fig. 13. Control scheme of the auxiliary circuit.

The average power of the auxiliary circuit PT line is

PT line =ET line

Tline. (39)

The specific expression of PT line can be derived accordingto (12), (17), (38), and (39). Besides, D is expressed in (40),where ωline is the line frequency

D ≈ 0.5[Mk sin(ωlinet) + 1] (40)

Mk = Umm /Umcar . (41)

The expression of PT line is very complex. The relationshipbetween PT line and the modulation index Mk can be obtainedby simulation and a simulation result is shown in Fig. 12 (wT

= 2). Mk ≤ 1 means the modulation is normal, and Mk ≥1means the switch holds (without switching) for a while duringhalf a line voltage cycle (over modulated). The curve of Fig. 12shows that when Mk ≥ 0.5, the trend of PT line is monotonicdecreasing. Then, the feedback circuit can be controlled in thisregion (within the shadows).

Thus, the control for power transmission from cell 1 to cell Ncan be realized by adjusting the modulation index of cell 1, andthe control scheme of the clamping circuit is shown in Fig. 13.

Δuda is the difference between uda1 and udN . When Δuda

exceeds the reference value Δu∗d ,Ga1 will increase, while

the transmitted power will decrease. Similarly, the transmittedpower will increase as Δuda decreases. Taking the voltage dropof the clamping diode and the saturation voltage of the IGBTinto consideration, Δu∗

d may be assigned with a value slightlygreater than 0.

The output voltage of the cell 1 will change if Da1 is adjustedby ΔDa1 . Thus ,the voltage should be compensated by the othercells of phase a (see Fig. 17).

D. Modulation Method

The number of the cells of the positive part equals to that ofthe negative part. Although the proposed topology is based onthe half-bridge inverter, a pair of half-bridges (one positive celland one negative cell) can be controlled together. Thus, cell j


Fig. 14. Equivalent unit of the two cells.

Fig. 15. Relationship between the output voltage and the drive signals of theequivalent unit.

TABLE IIIOUTPUT VOLTAGE OF THE EQUIVALENT UNIT AND SWITCH STATE

(1 ≤ j ≤ M) and cell M+j can be taken as an equivalent unit oran imaginary unit from the viewpoint of modulation, as Fig. 14shows (i.e., phase a). Vd is the capacitor voltage.

The output voltage of the equivalent unit is uo1 . The relation-ship of uo1 and the switch state is presented in Table III andFig. 15.

According to Table III, Sa11 and SaM +11 could share thesame modulated wave if SPWM method is applied.

Among the modulation methods of the cascade multilevelconverter [33]–[39], phase-shifted PWM method is easy to berealized without complex algorithm. Moreover, the equivalentswitching frequency is very high. So, it is a good choice forDCM2C. Fig. 16 shows the modulation principle for a DCM2Cbased on phase-shifted PWM method. M is the number of thecells in the positive part or the negative part (M is 3 in Fig. 16).Sj1 is the drive signal for the upper switch of cell j, which isinterlocked with the drive signal Sj2 .

The phase of the carrier of cell j leads that of cell j+M byπ. The carrier phase shift between cell j and cell j+1 is

Δθ =π

M. (42)

The drive signals for the six upper switches are shown inFig. 16. uphase is the output voltage of a phase arm.

Since the auxiliary circuit control of cell 1 will change theduty cycle, it will be better if the duty cycle control for cell 1is independent from that of other cells in the phase arm. The

Fig. 16. PWM method for a DCM2 C.

Fig. 17. PWM duty adjustment.

Fig. 18. Simulation waveforms of isa , iL a , and iF a .

PWM duty control scheme is shown in Fig. 17. D∗a1 is the new

PWM duty cycle for cell 1(see Fig. 13), and D∗a is for the other

cells of phase a.The gain G2 is determined by the following expression:

G2 =1

2M − 1. (43)

V. SIMULATION AND EXPERIMENT VERIFICATION

A. Simulation Study

A simulation model of a seven-level CS-APF based onDCM2C has been built in PSIM. The topology is the sameas the one shown in Fig. 9, and the system control is presentedin Fig. 10. The parameters of the model are given in Table IV.A resistor is connected to each cell’s capacitor in parallel, andthe differences of power loss between cells are simulated withdifferent values of the resistors.

Fig. 18 shows the simulation results of the proposed seven-level CS-APF. The sequence of the waveforms is (from top tobottom) isa , iLa , and iF a . The distorted source current is wellcorrected by the CS-APF.


TABLE IVSPECIFICATION AND PARAMETERS OF THE SIMULATION MODEL

Fig. 19. DC-link voltages of CS-APF (phase a) with the clamping circuit inoperation.

The dc-link voltages of a seven-level CS-APF based onDCM2C are presented in Fig. 19 (phase a). The capacitor volt-ages are well balanced by the clamping circuit, and the voltagedifferences are not higher than 10 V. Besides, the voltage ripplesof CdN are very low for the common cell shared by the threephases.

Fig. 20 shows the simulation results of the dc-link capacitorvoltages of the proposed seven-level CS-APF with the energyfeedback circuit turned OFF. The capacitor voltages becomeunbalanced. However, with the clamping diodes working, therelationship of the capacitor voltages is uda1 > uda2 > uda3 >uda4 = uda5 > udN .

Fig. 21 shows the simulation results of a seven-level CS-APF based on the basic half-bridge inverter. With no voltagebalance control, the dc-link capacitor voltages gradually be-come unbalanced. Unlike that in the system based on DCM2C,the relationship of the voltages is uda3 > uda5≈uda1 > uda2 >uda4 > udN . It is similar to the relationship of the resistance inTable IV: Ra3 > Ra1 > Ra5 > Ra2 > Ra4 > RaN .

Fig. 20. DC-link voltages of CS-APF based on DCM2 C with the energyfeedback circuit turned OFF.

Fig. 21. DC-link voltage of a CS-APF based on basic half-bridge inverter.

Fig. 22. Common-mode voltage of the neutral point of the proposed CS-APF.

The common-mode voltage of the neutral point of a seven-level CS-APF based on DCM2C is shown in Fig. 22.

The sequence of the waveforms is (from top to bottom)un , u′

n , and uF a . un is the voltage between the negative pole ofCdN and the neutral point of the power source. It is much lowerthan the source voltage. u′

n is the voltage filtered from un by alow-pass filter with the cutoff frequency of 1 kHz. u′

n is lowerthan 200 V. uF a is the voltage of phase arm a of the CS-APF,and is seven-level voltage.


Fig. 23. Seven-level CS-APF based on DCM2 C.

TABLE VPARAMETERS OF A SEVEN-LEVEL CS-APF BASED ON DCM2 C

B. Experiment of a Seven-Level CS-APF Based on DCM2C

A 10-kVA prototype of a seven-level CS-APF based onDCM2C has been implemented in the laboratory. A photographis presented in Fig. 23, and the specifications are presented inthe following parts.

1) Main Power Circuit: The prototype topology is exactlythe same as that in Fig. 9. The number of cells in a phase armis six. There are six floors in the prototype. Every three cell forphases a, b, and c is fixed on one floor. The cells in the upperfloor are connected with the cells in the lower floor via cables.The common cell is fixed on the bottom floor. Remarkably,only the top three cells and the bottom common cell of the CS-APF are equipped with voltage sensors. So, the total numberof voltage sensors for dc-link voltage control is just four. Theenergy feedback circuit is based on SHI. The load working asa harmonics source is a three-phase rectifier. The parameters ofthe prototype are given in Table V.

2) Control Unit: The digital control based on a DSP and afield-programmable gate array (FPGA) as shown in Table V isintroduced to the control system. The analog signals are sam-pled by the A/D converters controlled by the FPGA. The mainalgorithm is executed in the DSP which transmits the PWM dutycycle to the FPGA. Finally, 36 PWM signals are generated bythe FPGA.

Fig. 24. Waveforms of isa , iL a , and iF a .

Fig. 25. Waveforms of isa and uF a .

3) Experiment Results: An oscilloscope DSOX2024A pro-duced by Agilent and a scopecorder DL850 produced by Yoko-gawa are used to collect the experiment data. Fig. 24 shows theharmonics suppression results of seven-level CS-APF, whereisa is the source current, iL is the load current, and iF a isthe CS-APF current. The harmonics components in the sourcecurrent are greatly declined, and the waveform of is becomessinusoidal.

The output voltage uF a of phase a in the seven-level CS-APFis shown in Fig. 25. The harmonics components of the voltageare much lower than the two-level inverter.

Fig. 26 shows the experiment results with all three-phaseauxiliary circuits in operation. The sequence of the curves is(from top to bottom) source current isa , CS-APF current iF a ,common cell dc-link voltage udN , dc-link voltages: uda5 of cell5, uda4 of cell 4, uda3 of cell 3, uda2 of cell 2, and uda1 ofcell 1. The experiment results of phases b and c are similar tothat of phase a. The process of the system from the start to thesteady state is recorded. The dc-link voltages of CS-APF arewell balanced with the maximum voltage difference less than2 V. The detailed results of the steady state are presented inFig. 27.

For the common cell shared by phases a, b, and c, the aux-iliary circuit of one phase is beneficial for voltage balance ofother phases, as shown in Figs. 28 and 29. Fig. 28 demonstratesthe experiment results with auxiliary circuit of phases b and c


Fig. 26. Three-phase auxiliary circuits are all in operation.

Fig. 27. Detailed results of the steady state of Fig. 26.

Fig. 28. Auxiliary circuits of phases b and c are in operation.

in operation. The dc-link voltages ud2∼ud5 and udN are about117 V, while ud1 is higher than the others by about 6 V whichnearly has no effect on the system performance. Fig. 29 demon-strates the experiment results with only auxiliary circuit of phasec in operation. Still ud1 is the highest, about 21 V higher thanthe others. Yet, the system keeps stable without obvious effectson the system performance.

The experiment with auxiliary circuits out of operation duringthe process has been carried out for comparison. The results areshown in Fig. 30. After the system went into steady state, all

Fig. 29. Only the auxiliary circuit of phase c is in operation.

Fig. 30. Dynamic process when the auxiliary circuit was turned OFF.

Fig. 31. DC-link voltage waveforms with reactive power output.

of the auxiliary circuits were turned OFF at time t1 . All ofthe dc-link voltages ud2∼ud5 and udN decreased, while ud1increased whether the current isa was high or low. At time t2 ,the maximum voltage difference (ud1−udN ) exceeded the limit.The protection acted, and the CS-APF stopped working.

Because the three phase arms of CS-APF are split and the cells(except the common cell) in different phase arms are separatedfrom each other, the power flowing in one cell is single-phasepower when the ac-side current of the cell is the fundamen-tal current. Clear fluctuations of dc-link voltages (uda1∼uda5)


could be observed when the fundamental current is output bythe CS-APF as Fig. 31 shows (the experiment results when theCS-APF outputs reactive power). However, the dc bus of thecommon cell is shared by three phases, and the power flowingin this cell is three-phase power. Theoretically, the instantaneouspower is constant when positive-sequence fundamental currentsflow in the common cell, and there will be no voltage ripplesin the dc capacitor as the experiment results (udN ) shown inFig. 31.

VI. CONCLUSION

A novel topology of a DCM2C is proposed in this paper. Thetopology is proved to be a suitable solution for high-voltage andhigh-power application. Voltage balance for all dc-link capaci-tors is realized with a proposed simple feedback auxiliary cir-cuit. The number of dc-link voltage sensors could be decreasedsignificantly, which reduces control complexity and system cost.Three kinds of auxiliary circuits are presented and analyzed inthis paper.

The novel topology of a three-phase DCM2C with the auxil-iary circuits (SHI) is applied as a CS-APF, and the system con-trol algorithm and specific mathematical model are presented.With only four voltage sensors at the dc-link side, the dc-linkvoltages are well balanced. Furthermore, the complexity of thesystem control algorithm does not increase with the number ofcells increasing. The system can operate under normal condi-tion even only one phase auxiliary circuit is in operation. So, thereliability of dc-link voltage balance is significantly enhanced.

With simple topology, perfect clamping performance, andvery small number of voltage sensors, a DCM2C is a perfectsolution for medium-/high-voltage applications. It can be usefulin many applications, such as HVDC, STATCOM, etc.

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Congzhe Gao was born in Hebei, China, in 1984.He received the B.S. degree in electrical engineer-ing from the Department of Electrical Engineering,Chongqing University, Chongqing, China, in 2007,and the Ph.D. degree from the Department of Electri-cal Engineering, Tsinghua University, Beijing, China,in 2012.

He is currently in Automation school, Beijing In-stitute of Technology, Beijing. His research interestsinclude harmonics suppression, reactive power com-pensation both in low-voltage and medium-voltage

distributing networks.

Xinjian Jiang was born in Jiangsu, China, in 1964.He received the Graduate and M.S. degrees from theDepartment of Electrical Engineering, Tsinghua Uni-versity, Beijing, China, in 1987 and 1999, respec-tively.

Since 2000, he has been an Associate Professor atTsinghua University, Beijing. From September 2008to August 2009, he was a Visiting Scholar at AalborgUniversity, Denmark. His main research interests in-clude the control of power quality, motor drives andconverter for wind turbines.

Yongdong Li (M’08) was born in Hebei, China. Hereceived the B.S.E.E. degree from the Harbin Insti-tute of Technology, Harbin, China, in 1982, and theM.S.E.E. and Ph.D. degrees from the Department ofElectrical Engineering, Institute National Polytech-nique de Toulouse, Toulouse, France, in 1984 and1987, respectively.

From 1988 to 1990, he was a Postdoctoral Re-searcher with the Department of Electrical Engineer-ing, Tsinghua University, where he was an AssociateProfessor from 1991 to 1996, and since 1996 has

been a Professor. He is also with the Laboratory of Power Electronics andMotor Control. In 1995, he was a Visiting Scholar with the Department ofElectrical Engineering, Yokohama National University, Japan. From June toDecember 1996, he was a Visiting Professor with Virginia Power ElectronicsCenter, Virginia Polytechnique Institute and State University. During 2002, hewas an Invited Professor at the Institute National Polytechnique de Toulouse.He has authored or coauthored more than 200 conference and journal papers,and two monographs on digital control of ac motor and multilevel converter. Hisresearch interests include control theories, real-time implementation, sensorlessdrives and applications of vector and direct torque control of ac motors, windpower generation, medium-voltage high-power inverter for motor drives, andactive power filter application.

Dr. Li is a Senior Member of the China Electro-Technique Society, the ViceChairman of the China Power Electronics Society, and the Vice Chairman ofthe Electrical Automation Committee of China Automation Association.

Zhe Chen (M’95–SM’98) received the B.Eng. andM.Sc. degrees from the Northeast China Instituteof Electric Power Engineering, Jilin, China, andthe Ph.D. degree from the University of Durham,Durham, U.K.

He is a Full Professor with the Department of En-ergy Technology, Aalborg University, Aalborg, Den-mark, where he is also the Leader of the Wind PowerSystem Research Program in the Department of En-ergy Technology. He has more than 260 publicationsin his technical field. He is also the Principal Investi-

gator of Wind Energy at Sino-Danish Center for Education and Research. Hisresearch interests include the areas of power systems, power electronics, andelectric machines His current research interests include wind energy and mod-ern power systems.

Prof. Chen is an Associate Editor (Renewable Energy) of the IEEE TRANS-ACTIONS ON POWER ELECTRONICS and the Guest Editor of the IEEE TRANSAC-TIONS ON POWER ELECTRONICS–SPECIAL ISSUE ON POWER ELECTRONICS FOR

WIND ENERGY CONVERSION. He is a Fellow of the Institution of Engineeringand Technology, London, U.K., and a Chartered Engineer in the U.K.

Jingyun Liu was born in Hebei, China, in 1983. Shereceived the B.S. degree from North China ElectricPower University, Beijing, China, in 2007, and thePh.D. degree from Automation School, Beijing Uni-versity of Posts and Telecommunications, Beijing,China, in 2012.

She is currently working at the AutomationSchool, Beijing Union University, Beijing. Her re-search interests include intelligent measuring andcontrol system and mathematical modeling ofcomplex systems.

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