Applied Surface Science 39 (1989) 535-551 535 North-Holland, Amsterdam

A CROSS SECTION OF HOT-CAP~'JER PHENOMENA IN MOS ULgi ' s

Eiji TAKEDA Central Research Laboratory, Hitachi Ltd, KokubtmJi, Tokyo 185, Japan

Rect~ved 29 March 1989; accepted for publication 31 Marg'h 1989

The state-of-the-art and future perspective of hot-carrier effects in MOS devices are discussed from the viewpoint of: (l) the AC versus DC hot-carrier degradation mechanism, (2) initial stage degradation, (3) a hot-cartier effect specific to p-channel MOSFE'r's, (4) new hot.carrier effects in the - 0,3 pm region. (5) hot-carrier resistant device structure, and (6) mechanical stress induced hot-carrier effects. In particular, new hot-carrier ¢ff¢cls and/or phenomena which have not been clarified so far, will bc focused on. Thus, such a deeper physical insight into hot.carrier effects as shown here and feedback or this knowledge to device structures and circuits a re strongly rcquired to realize the deep submicron MOS ULSI's.

L Intr~luetion

"ULSI revolution" marl'ring a new epoch in the electronic industry has made remarkable progress to such an extent that 107-10 a transistors are fabricated on a single chip. For instance, current ULSI microfabrication technologies are being pushed to the extremes by the DRAM community, hereby expediting research on 64 Mbit DRAM's using a 0.3 ~m design rule. Since process and device technologies in such a deep submieron region are, however, approaching practical limits, reliability problems as well as improve- ment of performance are becoming increasingly significant. In particular, the scaled MOSFET (ULSI building element) is suffering from hot-carrier de- gradation and the down-sliding of scaling merit due to high field effects,

Among ULSI reliability problems, the hot-carrier effect is an important factor to determine MOS device structure and power supply voltage, Fig, 1 shows device structures and hot-carrier breakdown voltage for each DRAM generalion. It can be seen that several kinds of hot-carrier rcsistam device structures such as DDD [1] and LDD [2], have been proposed so far, but a 5 V supply voltage cannot be used even in LDD with LEF~ tess than 0.8 ~m. Therefore, in the region of 0.5-0,3 pro, two approaches will be taken accord- ing to the type and purpose of ULSI's. These are: (i) new hobcarrier resistant devices [3,4] usable with a 5 V supply, and (it) reduction of power supply voltage (3-1.5 V). In the former approach, a deeper physical understanding of

0169-4332/89/$03.50 © Elsevier Science Publishers B.V. (North-Holland Physics Publishing Division)

536 E. Takeda / .4 cross section of hol-carrier phenomena in MOS ULSI's

DDD : Double Diffused Drain LDD : Lightly Doped Drain

GOLD GOLD : Gate-dram OverLapped Device

[::::3

CO ~ M I ~ ~'~'~ ~' \

EEB

LDD ODD

001 0'20:~ 0's ; % '~ 's 1'0 L G ( p , m )

Fig. 1. Device structures and hot-carder breakdown voltage for each DRAM generation.

high field effects such as hot-carrier and short channel-effects is needed a n d

the power consumption problem [5] becomes significant. The second approach must also overcome a low speed problem because subthreshold voltage is difficult to scale, resulting in the low che, nnel current. Optimal device oper- ation for any ULSI device can be achieved by choosing the best hot-carrier-re- sistant device structure. Also, since hot-carrier effects are phenomena caused by "hot '-earriers (electrons and holes) with high energy, its fundamental physical mechanisms have something in common with the time-dependent-di- electric breakdown (TDDB), radiation damage (RD) due to the cosmic and

®

Fig. 2. Problems surrounding hot-carder efleet.

E. Takeda / A crass section of hot-carrier phenomena m MOS ULSI*s 537

a-rays, and electro-static discharge (ESD), as shown in fig. 2. Such a trend requires a deeper physical insight into hot-carrier effects in the deep submi- crun Si MOSFET's and feedback of this knowledge to device structures and circuit design.

In this paper, the state-of-the-art and future perspective of hot-carrier effects in MOS devices are discussed from the viewpoint of: (1) the AC ,~ersus DC hot-cartier degradation mechanism, (2) initial stage degradation, (3) a hot.carrier effect specific to p-channel MOSFET's, (4) new hot-carrier effects in the ~ 0.3 p,m region, (5) hot-carrier resistant device structure, and (6) mechanical stress induced hot-cartier effects. In particular, I would like to concentrate on new hot-carrier effects and /o r phenomena which have not been clarified so far.

Z. AC versus DC llot-ea~ier degradation mechanism

With regards to hot-carrier (HC) degradation in ULSI's, primary attention is now paid to device degradation under the pulse (AC) stress corresponding to actual circuit operation. Device life-time (TAC) under AC stress has been shown to be related to effective DC stress time by ~'AC = "rncR [6], where R is a circuit duty ratio, but recently discovered device degradations specific to AC stress requires a re-examination of this equation. Firstly, device degradation due to DC stress will be reviewed.

2.1. D C stress degradaaon

The main experimental results are summarized in table 1: (i) In n-channel As-drain and D D D structures, the majcr cause of the Gm degradation is surface state generation rather than trapped electrons. Such a tendency becomes more remarkable in a long term stress [10]. Also, the Gm decrease is more marked than the VTn shift in the n-channel device degrada- tion. Several hypotheses for the surface state generation have been proposed so far: The hydrogen model [11] suggested by Fair and Sun and /or the hot-hole model [12] seem to be promising. At any rate, it is certain that hot-holes play a primary role in the surface state generation. It is particularly important to note that even in the drain avalanche hot-cartier (DAHC) injection region ( [ V D I > I ["rG I), the gate current is dominated by the channel hot-cartier injection composed of "lucky electrons" which gain sufficient energy to surmount the Si-SiO2 barrier without suffering an energy-losing collision in the channel [13]. This fact supports the hot-hole model. (ii) In the LDD devices, on the other hand, the Gm degradation is due to an increase of n--resistance depleted by electrons trapped into the sidewall SiP 2. (iii) For the p-channel devices, electron trapping into gate SiP 2 causes a G m

538 E. Takeda / A cross section of hat-carrier phenomena in MOS ULSI's

Table 1 Experimental results of DC stress degradation

Device Max degradation Degradation Degradation structure condition mechanism

N M O S S-drain VTn shift - Electron trapping in gate DDD /sun peak oxide

Om decrease - Surface state generation

Increase of n-.resistance LDD lsu a peak G m decrease depleted by deetrons

trapped into the sidewall

PMOS S-drain VTH shift - Electron trapping in gate IG peak oxide

LDD G m increase - Trap neutralization or shortening of tile effective channel lenstia

increase and a VTH shift. The G., increase is due to LEF F shortening caused by the trapped electrons [14]. However, the LEF F dependence of device degrada- tion in the p-channel is considerably larger than in the n-channel as will be mentioned later. These device degradations all become maximum in the drain avalanche hot-carrier (DAHC) region. The hot-carrler lifetime determined by DC stress is given as [15,16]:

• oc ~ exp( - ~ / v o ) , (1)

,rnclr. cx ( I s u n / I D ) ", n = -- 3, (2)

~nc ~ ( - ~/LEFV), (3)

and from eqs. (1) and (3), the hot-cartier breakdown voltage (BVHc) is given as a function of Lee e as follows:

BVHc = C I L EFF/( L ~FF + C2)" (4)

2.2. A C s t r e s s d e g r a d a t i o n

In the actual ULSI circuits, hot-cartier degradation is influenced by AC (pulse) stress, rather than DC stress. Although there is an opinion that hot-carrier degradation under AC stress is also determined by effective DC stress time or circuit duty ratio, several recent reports state that carrier trap-detrapping effects and/or excess cartier generation at pulse fall/rise periods cause degradation enhancement and device structure dependent phe- nomena to occur. The main experimental results [7-9] are summarized in table 2.

IS, Takeda / A cross section of hot.carrier phenomena in MOS ULSI's

Table 2 Experimental results of AC stress degradation

539

Hitachi UCB Siemens

Experimental - Device structure - Enhanced in the - Enhanced when results under dependence falling period of plasma nitridc is AC stress - Suppressed in As-D Vg (Vd: large) used as a

and enhanced in - In other cases, no passivation layer LDD difference between - Device structure

AC and DC stress dependence

AC stress - Electric field - Excess carriers - Electric field degradation modulation due to (hole) in the modulation due to mechanism electron dctrapping channel region hole dctrapping

cause the degradation at large Va

As an e x a m p l e of the e lect ron d e t r a p p i n g effect in A C ho t -ca r r i e r p h e n o m - ena, the device l ife t imes in b o t h s inglc d r a i n ( S D ) an d L D D are s h o w n as a func t ion of subs t ra te cur ren t ( / s u n ) in fig, 3, c o m p a r i n g A C vdth D C stress. I t can be seen lha t "rAC obeys the re la t ion of eq. (2), and s t rong ly d e p e n d s o n the device s t ructure , l ead ing to the cqua t ion :

~'AC = aTDcR, ( 5 )

where a is a functicn of device structure. Thcsc experimental rcsuhs seem to

10 ~

~ 105

-iT E

in

v)o-'

S D

'", AC

o DC AC

• J ~

I 500kH~. Duly 50%

L D D

'I

~d 4 10 s

Iso B (Alpm)

l l

16 e 16 ~ id 4 Id 3

Fig. 3. Substrate current versus hot cartier lifetime both in SD and LDD.

540 E. Takeda / A cross section of h6t-c,~rrier phenomena in MOS ULSI's

300 ]150

200 ~00

100 50

0 ~ ' I0 ~ 103 1040 Stre~s Time (see)

Fig. 4. DC stress time dependence of/SUB both in SD and LDD.

be due to electric field modulation by the carrier trap-detrapping effect under AC stress condition. To investigate the AC stress degradation mechanism, let us look at the/sub behavior during stress. The DC stress time dependence of lsuR is shown in fig. 4. It can be seen that there is a noticeable difference between the SD and L D D devices: For SD devices, lsu B increases monotoni- cally, because the electric field near the drain increases as electrons are trapped in the gate oxides during the DC stress. In LDD devices, on the contrary, lsu B decreases with stress time, probably because the electric field near the drain weakens by an increase of n - resisglance due to electrons trapped in the sidewall spacer.

Drain(Gate) Voltage

"hot . . . . cool"

I_F-]_ Elect r ic Fietd 4, 4,

'LDD - - _ _

Fig. 5. Pulse waveform and the electric field strength (electric field modulation).

E. Takeda / A cross section of hot-carrier phenaraena in MOS ULSI's

l hol v ~ o:x:l

541

"E FIELD MODULATION"

~S-L ~

I I DECREASE IN n RESISTANCE ¢

E FIELD INCREASE

MECHANISM OF AC STRESS EFFECTS

IN LDD DEVICES

Fig. 6. Electric field modulatEon effect in LDD devices.

Based on these /sue bellaviors, the above AC stress effects could be explained. In the AC pulse stress, a portion of the trapped electrons, which may have considerably short relaxation times ( ~ 10 ns), are detrapped in every cool period where V D or V o is 0 V. Due to such a detrapping effect, the electric field near the drain in the initial instance of every pulse becomes different from that under DC stress, as shown in fig. 5. That is, the electric field modulation due to hot-cartier trap-detrapping effects will give rise to new hot-carrier effects upecific to AC stress, leading to device structure dependence and passivation layer dependence [18]. Fig. 6 schematically il- lustrates an electric field mod,,dation effect in LDD devices. Thus, it is significant to re-examine hot-carrier effects in terms of hot-carrie~" trap-de- trapping [19], which will provide new facets in ULSI reliability.

3. ~nitia~ s~a~ degF~da~on

In n-channel LDD and p-channel devices, the initial stage degradation is known ~o be remarkable because it is caused by electron trapping. Therefore, by invest!gafing device degradation in short times less than ms, it is possible to obtain, new insights into the hot-carrier trapping mechanism 120]. The initial stage degradation in p.cl,,annel LDD (buried-channel) is shown in fig. 7. It should be noted that both the VTH shaft and G m degradation occur with two phases. In the first phast ( < ms), the degradation is most evident under the ma~,mum Isua condition, where surface state generation and then electron

542 E. Takedu / A cross section of hot-carrier phenomena in MOS ULSI's

p ch LDD Lo.=O&um

10 2 V~ -9.or

1 1 ~, ~t ~ - - - - , , s . ~

'~ V G ~,/ p,,'

~ o - ~ - ~ ~ , I . . . . . . 16 B .iO -~ 10 0 10 3

T I M E ( s e c )

o 10 I p c h LOD V~,:-1.2 ~

1 (j l / -4.0 o ,.=

1 0 3 / - ° - . - ° - . - " / , . . . . . 16' 16 s 10 ° lo 3

TI ME (sec)

Fig. 7. Initial stage degradation in p-channel LDD (buried-channel).

trapping into its surface states take place. With the second phase, the maxi- mum degradation occurs when 1 G is maxim,ira, where the electron-trapping- process in the gate oxide is responsible. Also, in n-channel LDD devices, two modes of degradation exist in the same way as p-channel. These pieces of information will be useful for understanding the degradation mechanism.

4. Hot-earrler degradation specific to p-channel M O S F E T s

The hot-carrier lifetime in p-channel devices is shown in fig. 8 as a function o f / son with LEF F as a parameter. The criterion is ,AVTH ~ 10 mV. It is found that the p-channel lifetime is strongly dependent on LEFF, compared with that of the n-channel, in spite of normalization by lso B. In n-channel devices, as you know, eq. (2) is valid fm lifetime prediction, regardless of LEFF. This is probably because electrons trapped in the gate oxide effectively decrease the

E. Takeda / A cross section of hot-carrler phenomena in MOS ULSI's

I0 s

I\ \ ,0%, \o;lO\ lc~ o6 o

'°'t \ \, ,\ \ \ ,

10 s 10 ~ 10 6 16 ~ 10 ~ 10 3

]~B (A) Fig, S. Hal-cartier lifetime in p-channel devices.

543

channe~ ~ength [14] and as a result, increase /sub in the form of positive feedback. Consequently, this results in a larger dependence of lifetime on LEe r . However, the role of hot-holes in p-channel devices has not been clarified so far. It will also be important to investigate three-dimensional effects of trapped electrons.

5. New hot-cartier effect in the deep submieron region

In the deep submicron region, such new hot-carrler phenomena as low energy hot-cartier effects [21-23] and direct tunneling degradation [22] will appear with deviee dimension scaling. However, the physical meauing of these phenomena is not yet clear. This st~'ongly calls for a deeper physical under- standing of the reciprocal action between the Si-SiO 2 interface and injected hot-carriers.

Here, a new mode of device degradation caused by "cold" carriers due to band-to.band tunneling [14] in a MO$ drain is studied [25]. Recently, the band-to-band tunneling phenomenon has received considerable attention be- cause it deteriorates the refresh characteristics of DRAM's and determines device structures in the deep submicron region. Electron-hole pairs created by band-to-band turmeling are still "cold" when they arc generated, and such carriers are believed to have no influence on device characteristics.

544 E. Takeda / A cross section of hot-carrier phcnomena in MOS ULSI's

o t'o t'e ,o o STRESS T I N E (sec)

Fig. 9. Time dependence of tunnel threshold voltage VTH arid tunnel leakage current ltk.

5.1. T ime dependence o f tunnel leakage current

Fig. 9 shows the typical time dependence of tunnel threshold voltage V-~H in n-channel devices (n + drain region in n-channel MOSFET's) under two different stress conditions, with V o - V G kept constant ( = 10 V). The tunnel leakage current lek under the stress is also monitored. Here, V~H is defined as the drain voltage at which the tunnel leakage current is 10 -14 A / g m . VtH increases monotonically, while lek decreases. These facts strongly imply that holes are captured in the oxide during the stress application. I f the hole injection is merely proportional to the rate of charge generation, ~V,~ H should be the same for these two stress conditions and should not depend on the magnitude of V v . Experimental data, however, show that AV-[- H strongly depends on VD, although VD - V~ is kept constant. Thus, it can be concluded that the rate of hole injection is not determined by V D - Vo, but rather is determined by VD- This means that the holes must obtain energy from the electric field parallel to the Si-SiO 2 interface. There may exist other mecha- nisms for hole injection such as FN tunneling or impact ionization at the gate edge. The rates of these effects, however, are determined by V D - V G (which is constant in our experiment) and do not explain the change in Z~VgH.

5.2. Mode l o f hole injection

A simple model, which adopts the basic idea of the lucky electron model, is proposed on the basis of the experimental results stated above. This model is illustrated schematically in fig. 10: (1) Due to the band-to-band tunneling, electron-hole pairs are created in the drain region under the gate edge close to the St-St02 interface. They arc "cold" when generated.

E. Takeda / A cross section of hot.carrier phenomena in MOS ULSrs 545

1 geno

2 ,accelera t i - - 2 1

3.injection

Fig. 10. Hole injectiota model.

(2) The electrons are swept away to the drain electrode, while the holes travel along the Si-SiO~ interface towards the junction edge. The majority of the holes flow into tim substrata and are observed as substrate currant. A part of the created holes, on the other hand, move without suffering any collision and obtain enough energy to surmount the Si-SiO 2 barrier. (3) As a result of elastic scattering, such hot holes are injected into the oxide, and cause degradation in device characteristics as shown in fig. 9.

Hereafter, the proposed model is treated analytically. First. I = @JqE, , is the dislance that a hole must travel in the electric field Em to gain an energy @b, the barrier energy at the S t -S in 2 interface. Here, E,, is the maximum electric field. Tim probability that a hole travels a sufficient distance to gain energy ~'b without suffering a collision is given as:

P( / ) ~ e x p ( - ¢ b / q h h E m ) , (6)

wheca, ~h is the mean free path for holes. The number of hajected holes is proportional to the created charge multiplied by P(I). The shift of V~H is given by the trapped charge divided by the oxide capacitance:

a V ~ , = Q,~p/Co~ ~ Qgo, exp( - ~b/q~hnm)/Co~. (7)

546 E. Takeda / A cross section of hot.carrier phenomena in MOS ULSI's

Em (V/m)

9 8 7

3 , ~ , NM0;

~2 0.5

1.1 112

×10 7

rox= 15nm

~0,,.

~:3 1:4 1;~ 16 x15 s

l lEm (m/V)

Fig. 11. LOg(dVTH ) versus I/E m bolh in n- and p-channel MOSFET's.

In this derivation, both the probabilities that a scattered carrier is injected into the oxide and that an injected carrier is trapped in the oxide are assumed to be constant and therefore, are not written explicitly.

Fig. 11 shows the log(Z3V-~H) versus 1 / E m relation. Here, each AVgn is taken at a time when the same amount of electric charge has been created by band-to-band tunneling, namely, Qge, = f l ek dt = constant. In calculating Era, a device simulator C A D D E T H was employed. The mean free path h h is calculated from fig. 11 to be 8 nm. This value of 3. h agrees wall with the previously reported value (4.5 nm [26]). The same argument is applicable to the tunnel leakage phenomenon in p-channel devices (p+ drain region in p-channel MOSFET's). In this case, electrons, instead of holes, are injeeted into the oxide and captured. As a consequence, /W~-H is negative and the tunnel leakage current decreases. In fig. 11, the result for the p-channel case is also presented. The mean free path for electrons, At, is estimated as 10 rim, which is large- than A n and agrees with the reported value of 6.2 nm.

6. Hot-e.arrier resislanti devlee structures

Recently, "drain-engineering" methods such as the double diffused drain (DDD) and the lightly doped drain (LDD) are being used to improve

E Takeda / A cross section ofhot-carrierphenomena in MOS ULSI's 547

native oxide(2) oxide

Ti\ poly-Si oxide(1 ) gate ~ l . I~ I | SELOCS

I ~ . 1' J "~ I oxide

p-sub overlap lenglli

Fig. 12. GOLD structure.

reliability. However, it is difficult to achieve high reliability and high perfor- mance at 5 V with these methods, because there is a trade-off between transconductance and device breakdown voltage (hot-carrier, drain sustainins). This is because drain-engineering methods optimize only n - length and n - dose. Moreover, the gate-drain/source overlap length F is another important parameter in the control of device characteristics.

lnvursed-T [4] and G O L D [3], which make good use of the gate-drain overlapped (GOLD) effect [27], have been reported as MOS device structures usable with a 5 V supply voltage. A typical G O L D structure is shown in fig. 12. In such G O L D structures, not only high resistance against HC effects, but also high transconductance are realized in 0.3.-0.5/~m regions as shown in fig. 1. This high performance is essentially due to source resistance decreased by the G O L D effect. Thus, concurrence of reliability and performance will make the G O L D structures more suitable for Bi-CMOS ULSI 's and high-end computers aimed at high speed.

6.1. L D D structure

As shown in fig. 1, a 0.5/Lm LDD device cannot be used vAth a 5 V supply voltage under a criterion of A G , J G m = 0.1/10 years, even when taking the duty ratio = 0.1 into account. However, if the criterion can be varied as Z~Gm/G m = 0.2/10 years or z~V.ru = 100 mV, the LDD is usable even at a 5 V supply voltage, and in tliat case, the sophisticated circuit design is needed.

6.2. G O L D structure

6.2.1. G,, improvement

G O L D has 1.25 times higher transconductance (Ur,) and 1.15 times larger channel currents ( I o ) dmn conventional LDD, with LEFF=0.5 t~m and V o = 5 V. i f V D = 3 V is assumed for LDD's, G O L D has 2 times larger I o. Furthermore, this G m improvement becomes greater with decreasing LEF F.

548 E. Takeda / A cross section of hot.carner phenomena in MOS ULSI's

11 . , . Tin= =15 nm

'., ~, Vo=V~:5v 10 , , \ :'", VBB=-3V

. , , ,~,, ...o,.,

~ 8

SO ',, ; ' , , ' , 5 ",~ ? ""-. ". LDD

BVos (V)

Fig. 13. Relalionship belwe~n IDS and BVDs in GOLD, LDD and As-D.

These G O L D characteristics are due to the reduced n resistance caused by the vertical field induced by the overlapped gate.

6.2.2. Suppressed avalanche-induced breakdown G O L D has higher drain sustaining voltage (BVDs) than conventional

LDD's. The BVDs in G O L D increases up to 10 V with LE~ F =0.5 #m. This BVDs improvement is due to the reduced lateral electric field caused by the vertical field induced by the overlapped gate. The overlapped gate reduces not only n - resistance but also the lateral electric field. As a result, there is no trade-off between transconductance and drain sustaining voltage in GOLD, as shown in fig. 13. It is found from this figure that the trade-off results from using LDD in place of As-D (As-single drain) to improve reliability.

6.2.3. Reduced hot.carrier degradation GOLD is a surprisingly hot-carrier resistant structure. The hot-carrier

breakdown voltage (BVnc)(,~G.u/Gm = 0.1/10 years) is about 8 V even for LEE F = 0.5 /~m, while in conventional LDD's, BVHc < 5 V. Fig. 14 shows the mechanism of reduced hot-carrier degradation. It is found that the electron-hole pair generation rate peak position in G O L D is away from the gate sidewall oxide, resulting in the suppression of hot-carrier injection into the sidewall oxide. The reduced lateral field causes the peak generation rate value (GRm) in G O L D to be on order of magnitude smaller than that in L D D as well. Consequently, G O L D reduces not only the trapped electrons in the sidewall spacers specific to LDD, but also the avalanche-induced hot-carrier

E. Takeda / A cross section of het-carrier phenornena in MOS ULSI's

it- oxide I gate

2x b ~ ' /~ .4x l~e .~ ' r :o .o5 - drai. ~ / OR~ w n

(LDO) [ / /J

r=o.2j Um oxide [ gate ~ J o.o

Fig, ]4. Electron-ilol¢ pah' generation tale distni~mions in the drain whh GOLD and LDD,

Stre~s Va=OV ~ . rc=SXlO crff v VD:9,SV,Vfi~4V tolf:l.0 tt m a vo: 9.sv.vo=3.?v

lbZ ' ~ , ° 1,0¢ ' i0 s Stress Time (see)

Fi 8.15. DeFendence of G m degradation on stress lime in GOLD and LDD.

549

generation. The dependence of stress time on G~ degradation for both GOLD and LDD is shown in fig. 15. In tiffs figure, (I) shows how the degradation is improved by eliminating electron trapping in this sidewall spacer. The other improvement (II) is caused by the reduced hot-carrier generation.

7. Meeha~lca~ stress induced ho~-cn~rler effects

A relation between HC effects and mechanical stress at the Si-SiO, interface has not been clarified so far [28]. As device dimensions are scaled down, proees- and material-induced mechanical stress to the Si-SiO: interface is considerable. There are two types of HC effects due to mechanical stress: (1) surface state and defect generation induced by ULSI process steps, and (2) decrease of channel currents and of BVHc due to package mold stress [28].

550 E. Takeda / A cross section of hot-carrier phenomena in MOS ULSI's

10°1"-~--'~-" ~ /~Vth=lOmV l I \ \ \ \ ~=~o~ /

..d106 t W ~ f m ) \ \ \ \ ' ~ [ ~

\\) 10 "~ 10 s 105 104 S,Jbstrctte Current [E~/W(/Vpm)

Fig. 16. Channel width dependence of HC-lifetime as a function of/suB.

The physical meaning for (2), in particular the BVHc decrease, is not yet well clear. Fig. 16 shows a channel width dependence of HC lifetime as a function of IsuB. It is obvious that the lifetime decreases with a decrease of channel width. This is considered to be due to surface states generated by increased mechanical stress as the channel width decreases. Thus, the mechani- cal stress effects will become increasingly important for HC degradation and will reveal new facets in ULSI reliability from now on.

8. Condmions

Several kinds of hot-carrier phenomena in ULSI reliability have been discussed. In some cases, the physical meanings of the hot-cartier phenomena still need clarification. Among them, ha particular, the degradation mechanism (reciprocal interaction between hot-carriers and Si bonds) at the $ i -$ iO 2 interface including mechanical stress effects should be explained in order to realize more sophisticated U L S r s for the future.

E. Takeda / A cross section of hot-carrier phenoment~ ~ M O S ULSI's 551

Regetenc6,s

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geomet~, IEEE ISSCC (1985) pp. 272-273. [7] Y. ]gura and E. Takeda, Hot.carrier degradatien mechanism under AC stress in MOSFET's,

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