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Real-Time Syst (2011) 47:382–385DOI 10.1007/s11241-011-9131-z
C O R R I G E N D U M
A Corrigendum to: “Sticky-ERfair: a task-processoraffinity aware proportional fair scheduler”
Arnab Sarkar · Sujoy Ghose · P.P. Chakrabarti
Published online: 2 June 2011© Springer Science+Business Media, LLC 2011
Abstract This paper provides a corrigendum to resolve a couple of minor issues inthe algorithm presented in Sarkar et al. (Real-Time Syst., 2011). The first issue relatesto the postponement of execution of a task when its own ‘deadline of postponement’have not been crossed. The second issue concerns the updation of certain schedulerdata structures.
Keywords Proportional fairness · ERfair scheduling · Real time scheduling ·Task migration · Task preemptions · Cache affinity
Two issues have been noticed in the “Sticky-ERfair” algorithm presented in Sarkaret al. (2011) which underline the need for this corrigendum.
The first issue relates to deciding on whether to postpone a particular task andreplacing it with another one. The algorithm as presented in (Sarkar et al. 2011) con-siders postponing a task if it has not crossed its own deadline of postponement (step 5;p. 8 of Sarkar et al. 2011) and tries to schedule another task to avoid migrations ifpossible. However, this needs to be more carefully done if there are other tasks whichhave crossed their deadlines of postponement. Indiscriminate choice of an alternativetask under such conditions may lead to missing deadlines of some tasks at a laterstage. This issue can be resolved by allowing such a postponable task to be only re-placed by tasks that are more urgent than those which have crossed their deadlines ofpostponement.
A. Sarkar (�) · S. Ghose · P.P. ChakrabartiComputer Science & Engineering Department, Indian Institute of Technology, Kharagpur,WB 721 302, Indiae-mail: [email protected]
S. Ghosee-mail: [email protected]
P.P. Chakrabartie-mail: [email protected]
Real-Time Syst (2011) 47:382–385 383
Algorithm 1 Sticky-ERfair1: {Given: A set of n tasks and m processors}2: for Each time slot t , do3: Select the most urgent m tasks from the AVL tree A in ERfair fashion.4: for Each task Ti of these m tasks do5: Extract Ti from AVL tree DA.6: {Let Tr denote the task at the root of AVL tree DA.}7: if t ≥ δi OR t ≥ δr {Postponement of Ti ’s execution may possibly lead to
ERfairness violation} then8: if Vlei
is free {Vleidenotes the processor where Ti last executed} then
9: Allot Vleito Ti .
10: else if Ti was executed more recently on Vleithan the currently allocated
task Tc on Vlei{this is determined by the relative positions of Ti and Tc
in the AVL tree ATlei} then
11: Allot Vleito Ti ; Transfer Tc to a separate list l2.
12: else13: Transfer Ti to list l2.14: else15: Transfer Ti to list l1.16: {Let sg1, sg2, . . . , sgf be the indices of the processors yet to be allocated a
task in this time-slot. The lines below (15 to 25) attempts to replace the execu-tion of tasks in l1 by executing the most recently executed runnable tasks fromthe AVL trees ATsgj
(1 ≤ j ≤ f ; f = |l1| + |l2|).}17: k = j = 118: while k ≤ h and j ≤ f {h denotes the number of tasks in l1} do19: if ATsgj
is not empty then20: Extract index c of the most recently executed task in ATsgj
.21: if Task Tc is one of the m tasks selected in step 3 then22: Extract Tc from list l1.23: else24: Extract Tc from AVL tree A and DA.25: Allocate Tc to processor Vsgj
; Increment k; Increment j .26: else27: Increment j .28: Allocate tasks in l2 in the remaining free processors. {Each allocation incurs
a migration}29: while There is still a free processor Vx do30: Allocate the next task in l1 to Vx . c{Each allocation incurs a migration}31: Reinsert remaining tasks in l1 into the AVL trees A and DA.32: Execute the tasks selected for each of the processors.33: For those tasks among the m tasks that executed in the previous step and still
have subtasks pending execution, calculate the pseudo-deadlines and deadlinesof postponement of their next subtasks and reinsert them into AVL trees A andDA.
384 Real-Time Syst (2011) 47:382–385
The second issue relates to the updation of certain scheduler data structures aftereach time-slot of task execution by the system.
We present a revised version of the Sticky-ERfair algorithm (Algorithm 1) whichaddresses the above two issues. In particular the first issue is resolved by not allowinga task to be postponed when there exists ready tasks whose deadlines of postponementhave been crossed (Algorithm steps 5 to 7). To be able to maintain a schedulingcomplexity of O(m lg n), Algorithm 1 uses an additional AVL tree (called DA) ofready tasks ordered in terms of the deadlines of postponement of the tasks in additionto the AVL tree A which is ordered in terms of task pseudo-deadlines. Steps 32 and33 of the algorithm presented here addresses the issue of data structure updation.
References
Sarkar A, Ghose S, Chakrabarti PP (2011) Sticky-ERfair: a task-processor affinity aware proportional fairscheduler. Real-Time Systems. doi:10.1007/s11241-011-9120-2
Arnab Sarkar received the B.Sc. degree in Computer Science in 2000and B.Tech degree in Information Technology in 2003 from Universityof Calcutta, Kolkata, India. He received the M.S. degree in ComputerScience and Engineering at the Indian Institute of Technology (IIT),Kharagpur, India in 2006 and is currently pursuing his Ph.D. in thesame institute. He received the National Doctoral Fellowship (NDF)from AICTE, Ministry of HRD, Govt. of India, in 2006 and the MSRIndia Ph.D. fellowship from Microsoft Research Lab India, in 2007. Heis currently pursuing his research as a Microsoft Research Fellow. Hiscurrent research interests include real-time scheduling, system softwarefor embedded systems and computer architectures.
Sujoy Ghose received the B.Tech. degree in Electronics and ElectricalCommunication Engineering from the Indian Institute of Technology,Kharagpur, in 1976, the M.S. degree from Rutgers University, Piscat-away, NJ, and the Ph.D. degree in computer science and engineeringfrom the Indian Institute of Technology. He is currently a Professor inthe Department of Computer Science and Engineering, Indian Instituteof Technology. His research interests include design of algorithms, ar-tificial intelligence, and computer networks.
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P.P. Chakrabarti received the BTech and PhD degrees in computerscience and engineering from the Indian Institute of Technology (IIT),Kharagpur, in 1985 and 1988, respectively. He joined the Departmentof Computer Science and Engineering, IIT, as a faculty member in 1988and is currently a professor in the Computer Science and EngineeringDepartment, where he currently holds the position of dean (SponsoredResearch and Industrial Consultancy) and where he was the professorin charge of the state-of-the-art VLSI Design Laboratory. He has pub-lished more than 100 papers and collaborated with a number of world-class companies. His areas of interest include artificial intelligence,CAD for VLSI, and algorithm design. He received the President of In-dia Gold Medal, the Swarnajayanti Fellowship, and the Shanti SwarupBhatnagar Prize from the Government of India for his contributions.
