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On behalf of the CEPC VTX study group
The 2019 international workshop on the high energy CEPCNov, 18-20 2019
A compact CMOS pixel design for the CEPC vertex detector
Ping Yang
Ping Yang (CCNU )
Outline
• CEPC vertex detector and design specifications
• CPS development and the prototypes
─ Sensitive diode study
─ First prototype of an asynchronous readout mode and test results
─ A more compact prototype design of rolling-shutter readout mode
• Summary
2
3Ping Yang (CCNU )
Detector Layout
The vertex detector
Vertex detector:
– Single point resolution near the IP: ≤ 3 µm→ high granularity
– material budget: ≤ 0.15%X0/layer → Low power dissipation,
thinned, monolithic pixel sensor
– pixel occupancy: ≤ 1% → High granularity and/or short readout time
– Radiation tolerance: ~1Mrad/y (TID) and ~1012 Neq/cm2/y (NIEL)
Design specification
4Ping Yang (CCNU )
◆ Generally require:
• High granularity, σ = 3-5 μm;
• thin pixel sensors with fast readout, readout time = 10 -100 μs ;
• and low power dissipation, Power < 100 mW/cm2
◆ Spatial resolution
•𝟎.𝟓pitch
𝟏𝟐< S.P.resolution <
pitch
𝟏𝟐
• 若 S.P.resolution = 3 μm,10.3 μm < pitch < 20.7 μm
◆ Low power
• Binary circuit inside pixel
• Inside matrix zero-suppression readout, but have large pixel pitch
Developed CMOS Pixel Sensor prototypes for CEPC
Prototype Pixel size(μm2)
Collection diode bias
(V)
In-pixel circuit R/O architecture Main goals Status
JadePix1 33 × 3316 × 16
< 1.8 SF/amplifer,analog output
Rolling shutter Sensor optimization
Lab. and beam test finished
JadePix2 22 × 22 < 10 V (ac-
coupled)
amp., discriminator,binary output
Rolling shutter Small pixel,Power < 100
mW/cm2
Electricalfunctionality
verified
MIC4 25 × 25 reverse bias
Low power front-end,
address encoder
Data-driven,Asynchronous
Small pixel, fastreadout
Electricalfunctionality
verified
TaiChuPix1 25 × 25 reverse bias
Low power front-end,
address encoder
Data-driven,Asynchronous
Small pixel, fast readout withtime stamp
In measurement
JadePix3 16 × 2616 × 23.11
reverse bias
Low power front-end,
binary output
Rolling shutter with end of col. priority
encoder
Small pixel, low power
In fabrication
JadePix1 (IHEP)
3.9 × 7.9 mm2JadePix2 (IHEP)
3 × 3.3 mm2MIC4 (CCNU & IHEP)
3.2 × 3.7 mm2
All prototypes in TowerJazz 180 nm CIS process
TaiChuPix1 (IHEP, SDU,
NWPU, IFAE, CCNU)
5× 5 mm2
JadePix3(IHEP, CCNU,
Dalian Minzu Unv., SDU)
10.4 × 6.1 mm2
5Ping Yang (CCNU )
Lower input C lower analog power
6Ping Yang (CCNU )
Fixing the S/N for a given bandwidth higher Q/C allows for a lower power
a = 2 in strong inversion a = 1 in weak inversion
Assuming that main analog power dissipation comes from the input transistor bias
C
Y.Zhang, et al, NIMA 831(2016) 99-104
7Ping Yang (CCNU )
Sensitive diode test results
• Goals: sensitive diode geometry optimization with JadePix1
L.J.Chen, et al, RDTM (2019)DOI: 10.1007/s41605-019-0124-0
• Conclusion: Small collection electrode
size and large footprint can achieve high
charge-over-capacitance ratio.
(a)sensitive diode test circuit scheme
(b) conversion gain VS. sensor geometry
(C) ENC VS. sensor geometry
First prototype MIC4 overall introduction
8Ping Yang (CCNU )
• Goals: ① To explore a new data-driven readout architecture which can be implemented into a small pixel size; ② Front-end study. ③ Periphery block.
• Pixel size: 25 um x 25 um
• Matrix: 128 rows x 64 columns
• Two different front-ends in the matrix
• Zero suppression readout inside matrix
• DACs, bias
• No memory in the periphery, real time
readout, serial readout rate 1.2 Gbps
• Analog test for the last row pixels
(a) MIC4 structure (MAPS IN CCNU4) P. Yang, et al., NIM-A 924 (2019) 82-86
MIC4:Pixel digital front-end version 1
9Ping Yang (CCNU )
• Power cons.: 35 nW/pixel
• TN noise 18 e- is consistent with the
sim results, but FPN noise 120e- is
much larger than simulation
(mismatch).
AmplifierSource
follower
Vsub
Cf
Rf
Comp
Collection diode
OUT_A OUT_D
(a) CSA based analog front-end V1
by Ying ZHANG @ IHEP
Test results
(b)
(c)
MIC4:Pixel digital front-end version 2
10Ping Yang (CCNU )
• The ALPIDE front-end structure, Power: 110 nW/pixel
• Peaking time< 1 μs, duration < 3 μs (sim and test results)
• Mean threshold around 99 e- (test results)
• Mean FPN ~ 31 e-, TN ~ 6 e- ( test results)
(a)Front-end V2 based on ALPIDE by Weiping
Ren @ CCNU
(b) OUT_A with different Vpluse voltage
(c) Test results of peaking time and duration time
11Ping Yang (CCNU )
➢ ALPIDE matrix readout circuit AERD has many
connection lines occupy large area;
➢ OR gate chain: speed is limited with the
number of the chain pixels;
➢ Combine these two solutions
➢ Digital periphery provide a CLK signal of 60% duty cycle to enhance the readout
circuit to work at 40 MHz to decode 1024 pixels; -> a few μs readout time
8*8 pixels
20 address lines to the PeripheryA
DD
RX
<0
:7>
AD
DR
Y<0
:7>TG1
TG1
SIN STATE
SOUTSELECT
ADDR_EN
ADDR_ENRESET_PIX
RESET_PIX_B
RESET_PIX_B
RESET_PIX
RESET_PIX
DVDD ADDRX
ADDRY
Pix_OR_logic
Active low
AD
DR
<0:
3>
MIC4 data-driven readout scheme
P. Yang, et al.,INT J
MOD PHYS A
DOI:10.1142/S021775
1X17460125
• In-pixel circuit
– Low power binary front-end
– Optimized DFF
• Matrix Readout
– Rolling shutter
– 200ns/row
• Periphery digital Readout:
– Shared column lines
– End of column Priority Encoder
Zero suppression
– 64 columns processed during readout of
one row
JadePix3: Prototype of small pixel design
12Ping Yang (CCNU )
Serializer & LVDS
➢ Goal: Small pixel size → Low power FE + Rolling shutter Readout
Matrix 512 row x 192 col
Pixel
Periphery digital readout
• Design goals: small pixel size and low power consumption
• Sensor: High Q/C (collected charge/sensor capacitance) ➔ low power
➢ Electrode size of 4 µm2, with a large footprint of 36 µm2→ compromise of Q/C
with area
• Front-end:
➢ Operating principle derived from ALPIDE front end, two version designed (diff.
power & peaking time)
➢ Reduction on layout area, ~210 µm2
➢ Improvement on the threshold dispersion (compromise with area)
JadePix3:Sensor & Front-end design
Footprint
Electrode
16 μm
16 μm
110 120 130 140 150 160 170
0.0
0.2
0.4
0.6
0.8
1.0
Mismatch
µ = 138.1 e-
σ = 3.1 e-
Qin [e-]
Pro
b
110 120 130 140 150 160 170
VCASP
VCASN
IBIAS
ITHR
IDB
VCASN2
M1
M2
M4
M6M10
M7
M8
M9
AVDD
Out_A
Out_D
PIX_IN
M3
M5
Amplification Discrimination
area limitationFE_V0
13Ping Yang (CCNU )
JadePix3: DFF optimized for compact pixel
~6*6 um2
Standard version: ~16*6 um2
In-pixel DFF Modified :
• Compared with standard version:
– Transistor Num.: reduced from 36 → 16
– Layout size: 16*6 μm2 → 6*6 μm2
(reduced >60% )
• D connect to ground;
• Signal input from pin CLK;
• One control line shared for:
– RST of row n / Read of row n+1
Layout of modified DFF compared with standard version
14Ping Yang (CCNU )
Zero suppression at the EOC
• Priority encoder and reset decoder
- 4 bit address encoder * 4 Sectors
- 3 Columns as one block
• Hit information 16bit:
- 9 bit row Addr. + 4bit col. Addr. + 3bit hit
(one-hot code)
• FIFO R/W clk: 80 MHz
• FIFO depth: 48
• Data after 8b/10b : 400Mhz
• Layout: ~ 5120 μm * 200 μm
• Power: 15.35 mW
JadePix3: Digital periphery readout
15Ping Yang (CCNU )
Priority encoder
1 16
1
2
3
1 2 3 4
Multiplexer
FSM
8b/10b
FIFO FIFO FIFO FIFO
Serializer
LVDS
PLL
16bit 16bit 16bit 16bit
8bit 8bit 8bit 8bit
8bit
400 Mhz
80 Mhz
W/R CLK
Hit Reset Hit Reset Hit Reset Hit Reset
Cache
9 bit Row Addr.
Sensor Out
Zero Suppression
Matrix
Priority encoder Priority encoder Priority encoder
JadePix3: Status
6.1 mm
10
.4m
m
Sector Diode Front-end Pixel digital Pixel layout
0 2 + 2 μm FE_V0 DGT_V0 16×26 μm2
1 2 + 2 μm FE_V0 DGT_V1 16× 26 μm2
2 2 + 2 μm FE_V0 DGT_V2 16× 23.11 μm2
3 2 + 2 μm FE_V1 DGT_V0 16×26 μm2
Team IHEP, CCNU, Dalian Minzu Unv., SDU
• Submission in Sept. 2019
• Sensitive diode, minimum size
• Front-end based on ALPIDE, but 2 versions
– FE_V0, FE_V1 (9mW/cm2 , 26mW/cm2 )
• Pixel digital, 3 versions
– DGT_V0,DGT_V1, DGT_V2
• Pixel area
– 16×26 μm2
– 16×23.11 μm2
16Ping Yang (CCNU )
Summary
17Ping Yang (CCNU )
• Sensitive diode geometry was studied, minimum sensitive area (JadePix1/2)
• Explored a new zero-suppression structure inside matrix, with low power
front-end and almost full chip periphery blocks. All of the modules are
functional. The threshold and noise was studied. (MIC4 chip)
• JadePix3 optimized the pixel size and chip periphery power consumption
- Small pixel size, better spatial resolution expect ~3 um
• Radiation test and beam test is ongoing
Thank you for your attention!
Thanks to my colleagues:
IHEP: Yunpeng Lu, Ying Zhang, Yang Zhou, Zhigang Wu, Qun OuYang
CCNU: Xiangming Sun, Di Guo, Chaosong Gao,Le Xiao, Chenxing Meng,
Anyang Xu
Dalian Minzu Unv: Zhan Shi
SDU: Liang Zhang