A charge-sheet capacitance model based on drain current modeling

1678 IEEE TKANSACIIONS O K F.LF.C'TKON L)F.VIC'ES. VOI.. 37. N O . 7. JULY I Y Y I )

A Charge-Sheet Capacitance Model Based on Drain Current Modeling

WOLFRAM BUDDE A N D WOLFGANG H. LAMFRIED

Abstract-Based upon the charge-sheet approach analytical models of the drain current and the capacitances of a MOSFET are formu- lated. Mobility reduction due to velocity saturation and interface scattering of carriers are taken into account. A saturation criterion is developed from the condition of output conductance continuity. The capacitance modeling requires no additional parameters not contained in the dc model. The comparison with experimental data confirms the theory to be useful for analog circuit simulation down to channel lengths of about 1 pm.

x

NOMENCLATURE

Oxide capacitance per unit area. Critical field for mobility reduction. Critical field for CLM. Drain current. Boltzmann constant. = a used as fitting parame-

ter for CLM. Channel length. Substrate doping. Intrinsic carrier concentration. Elementary charge. Depletion charge per unit area. Gate and semiconductor charges per

Mobile charge per unit area. Total gate and depletion charges. Junction depth. Oxide thickness. = k T / q thermal voltage. Channel potential. Terminal voltages. Flat-band voltage. Channel width. Coordinate along the channel. Dielectric permittivity of silicon. Dielectric permittivity of oxide. Transverse mobility reduction coeffi-

= =/CO, substrate effect pa-

unit area.

cient.

rameter.

Manuscript received September 29. 1989: revised February 2, 1990. The review of this paper was arranged by Associate Editor B . Ricco.

The authors are with the Department of Electron Devices and Circuits, University of Duisburg. D-4100 Duisburg I . Federal Republic of Ger- many.

IEEE Log Number 9035772.

p o Bulk mobility.

4, Surface potential. @F = UT In ( 10 /n i 1.

++at Surface saturation potential.

I. INTRODUCTION HE SIMULATION of the transient behavior or the ac T analysis of VLSI circuits with the help of simulators

like SPICE requires a sufficient accurate MOSFET model. This model should provide currents as well as small-signal conductances and capacitances for all operating modes. To avoid convergence problems the continuity of the calculated quantities is of major importance. Further- more, the model should be physically based which means that the number of fitting parameters introduced to achieve best agreement with a certain technology process has to be reduced to a minimum. Besides improving the versa- tility of the model, the understanding of the implications of new technology trends on device properties is thus fa- cilitated.

The surface potential approach [ 11 is well suited to satisfy these requirements. Used in its simplified form, the Charge-Sheet Approximation (CSA) [2]-[4], it has the advantage to cover all regions of operation from weak to strong inversion in a uniform analytical framework.

In spite of its inherent benefits the approach suffers from some limitations. First, short-channel effects which are not included in the original formulation have to be added. This can be done in a first step by some kind of charge- sharing concept [5]. Secondly, saturation being beyond the Gradual Channel Approximation (GCA) is in princi- ple outside the scope of the theory. Another model de- scribing the saturation mode has therefore to be matched. The Channel Length Modulation (CLM) [6] is conven- tionally used here. Unfortunately, problems concerning the continuity of the output conductance arise from this treatment.

Starting from the CSA this paper presents a unified MOSFET model which provides a continuous description of drain current and conductivities as well as capacitances. The model takes into account mobility reduction effects caused both by velocity saturation and interface scattering of carriers. To avoid the discontinuities men- tioned above, a saturation criterion is proposed which is based just on the requirement of output conductance continuity thus yielding smooth drain current characteristics

00 18-9383/90/0700- 1678$0 1 .OO O 1990 IEEE

BUDDE A N D LAMFRIED: A CHARGE-SHEET CAPACITANCE MODEL 1679

without an assisting parameter fit. The CLM framework used to model saturation is improved introducing an explicit dependence of the channel length shortening upon terminal voltages and channel length. The reduced influence of the gate charge upon the bulk charge in short- channel MOSFET's is approximated with the help of the equilibrium charge-sharing factor F [7].

Developing the capacitance model we concentrate on a complete description of the gate impedance. The influence of substrate charging effects are included via c h , y and ch(,. Transcapacitances due to the nonreciprocity of the capacitance matrix and capacitances based on source and drain charges are consequently ignored. This reduced model is hoped to be sufficiently accurate up to rather high frequencies [8] if the channel length is not too long. Fur- thermore, our main motivation is the development of a model which provides continuous current and capacitances derived from a consistent theoretical foundation. The proportionality of the gate and bulk capacitances to drain current derivatives [9] demonstrates the need of a smooth current model to obtain a continuous description of capacitances.

In saturation we use, consistent with the CLM, a two- regions model to derive gate and bulk charge expressions. The gate-controlled charge in the space-charge region neighboring the drain is modeled by considering the mobile camers only. Using again a continuity argument we arrive at gate and bulk charge formulas which guarantee smooth capacitances at the transition from triode region to saturation.

11. DC-CURRENT MODEL In GCA the drain current is given by

The appearance of the channel potential V , which is defined as the difference of the quasi-Fermi levels of elec- trons and holes in the channel region, ensures that the diffusion part as well as the drift part of the drain current are correctly accounted for. The effective mobility model used to derive (1) reads

The bulk mobility p0 is reduced by the factor A , describ- ing enhanced scattering of carriers concentrated near the interface via

A,(+ , \ ) = ( + e ( V G - VFB - 4,)) -I ( 3 ) and by the carrier velocity saturation which becomes important if the longitudinal electric field in the channel reaches the order of a magnitude of some critical field E,..

The mobile charge Q,, can be expressed as the difference of the semiconductor total charge Q,\ and the fixed depletion charge Q),. Using CSA the latter is given by

Assuming that only a part F I 1 of the total depletion charge is controlled by the gate charge Q , = CO,( VG - VFB - 4,) due to short-channel effects leads to

GX( VG - VFB - 4\) = - Q l , - FQ/,. ( 5 )

Q, can be found from the first integration of Poisson's equation. Combining Q, = Q,, + Q/, with ( 5 ) the transcendental equation

is obtained. This equation relates the surface potential 4 \ ( y ) and the channel potential V ( y) at every point y in the channel. The boundary values 4,, = 4,(0) and 4 , ~ = 4, ( L ) , corresponding, respectively, to V ( 0 ) = Vs and V ( L ) = VD can be calculated from (6) by iteration. The transistor operates in weak inversion if 4\s I 4:s where

Equalizing the argument of the logarithm in (6) with UT 4;s = 2 i p F + Vs [8].

the critical value of Vc for weak inversion

V(G = VFB + 4:s + - VB

- A(1 - F ) J + : , - VB - UT ( 7 )

is readily obtained. To calculate the drain current according to ( 1 ) we use

(6) to replace the variable V by 4, and find the following expression valid in the triode region:

This integral can be evaluated in closed form. We approximate the derivative under the integral in the sense of Brews's modification of the CSA, namely [2]

- dV = 1 - - ( I UT. Cox - F K ) . A2COX (10) d4\ Q l ,

Using the auxiliary functions

1680 IEEE TRANSACTIONS ON ELECTRON DEV1Ck.S. V O L . 37. NO. 7. JULY IYY(1

one obtains with a better description of the characteristics in the saturation mode. Obviously, the onset of weak inversion at the drain could be used to define saturation. With the same

+ Vgt is obtained the solution of which is approximately given by

+ 2wJ4, - Vn - UT

AF + JvO - Vn - UT

( V o - V n - 1.5UT)In- . ( I l b ) h - h+ 1

The charge-sharing factor F is chosen to be equal to the value given by Yau [7]

where the depletion depth Xn is given by

Treating the depletion region as symmetric ( VD = V s ) and approximating the surface potential by a value character- istic for strong inversion make the modeling of the short- channel effect rather poor. On the other hand, our empha- sis is on a consistent formulation of current and capacitance characteristics on the same level of description. Furthermore, the independence of F upon V , simplifies the modeling of saturation behavior and avoids a rather artificial dependence of 4,ss on VD.

111. SATURATION With increasing channel potential V the surface poten-

tial becomes independent of V . So, for high VD, 4,,D asymptotically approaches the limit

F2X2 V,,. = V G - VFn + -

2

( 1 3 )

given by the zero of the argument of the logarithm in (6). V,,. is independent of VD thus realizing saturation of the drain current. Saturation is in this way characterized by the asymptotic decrease of the drain conductance g,/ and the mobile charge Q,, to zero. For short-channel transistors, this behavior clearly contradicts reality. Further- more, the surface potential cannot satisfy the proper boundary condition at the drain in this case which is a well-known shortcoming of the GCA.

To construct a more realistic model of saturation it is necessary to define a suitable saturation criterion together

r 1

L J

(14)

The corresponding saturation value of VDS = VD - VS

V:,t = vg' - Vs = - 2+/7 - Vs (15)

equals, taking F = I , the usual saturation voltage of the long-channel strong inversion model (see, e.g., [SI). On the other hand, it is well known that for shorter channel lengths the velocity saturation effect has great influence on the characteristics which, if incorrectly described, can even produce a nonmonotonic current in the pre-saturation region. A smaller saturation value +,,, < 4yat should therefore evolve which is governed strongly by velocity saturation. We define by the requirement of continuity of the output conductance at the transition point 4qD = 4,,, from triode region to saturation

s: = gd>. (16)

The output conductance is defined by the usual expression

Using (8) and (9) the following formulation, valid in the triode region ( VDs < is obtained

Pam, g: - 4sD - 45s E, aVD L +

E,

-I- Ilomt(4,~) Q,z (~ .O) ] . (18)

The first term in brackets, which diminishes the conductance, originates from velocity saturation.

In saturation, the modeling is based on the CLM concept. Using conventional CLM the channel length shortening L D is

where V,,, = V ( 4,at ) - Vs can be calculated directly from (6) as soon as 4,at is known. The drain current in satura-

BUDDE AND LAMFRIED: A CHARGE-SHEET CAPACITANCE MODEL 1681

tion is easily derived from (1). It reads

IDsat being given by (8) with 4sD replaced by In this expression, only LD depends on VD. Therefore, the output conductance in the saturation range ( V,, > Vsat) is given by

Approaching the transition from the upper side, g d tends towards the limiting value

(21b) ID sat

) * gd> =

4sat - 4 s ~ E g ( L -t E,

To solve for +sat, the continuity equation (1 6) is expanded in terms of E,,, = V, - up to the first and second order in weak ( VG 5 VC,) and strong ( V, > I/&) inversion, respectively. The resulting algebraic equations are readily solved. In strong inversion, the solution could be improved by a small correction not exceeding the order of magnitude of 1% with the help of a subsequent one- step Newton iteration procedure.

Following the original reasoning Eg turns out to be the critical value of the lateral electric field Ey at pinch-off. To get some estimate of Eg we note that near pinch-off the field components E, and Ey at the interface are equal in magnitude. In GCA we have E, = E , ~ / ( E , ~ ~ ~ ~ ) ( V , - V,, - &). Approximating +s in this expression rather crudely by V , according to (13) we assume that

(22) €0,

Esitox E , = Y - ( V G - V F B - V , ) .

Extensive comparison with experimental data suggested that the proportionality factor y can be approximated by

Y = Yo - YlL (23) reflecting an explicit channel length dependence of Eg. The parameters yo and yl are found by fitting.

Fig. 1 compares V:at according to (15) with Vsat deter- mined by the continuity condition (16). In the strong inversion region the latter is substantially smaller than the former indicating that saturation is governed predomi- nantly by the velocity saturation effect rather than by the vanishing of the inversion charge near the drain. In deep weak inversion Vsat approaches the value UT In ( 1 + E g L / U T ) while Vyat vanishes at the threshold voltage.

IV. CAPACITANCE MODEL The total gate and bulk charges are given by integration

of the corresponding charges per unit area. In the triode region we have

0 -1

I

0 1 0 00 05 10 1 5 , , 2 0 , , 25 , , 3 0 , Gate vo l tage [ V I

Fig. 1 . Comparison of saturation voltages V:, (dotted line) and V,,, (solid line). ( V , = 0 V; V, = 0 V; and V, = -3 V; L = 1.9 p n . )

QG = WCOX 1: (VG - VFB - 4s) dY

S: (24)

(25) Q B = - WCo,X J4s - VB - U T dy.

The differentiation of these integrals with respect to the terminal voltages V, and VD determines the small-signal gate and bulk capacitances

The integrals (24) and (25) cannot be evaluated as they are written down because 4s is an implicit function of y . Fortunately, changing variables from y to 4, with the help of the relation

(28) dY - 1 P o X ~ W Q ~ dV d4s Er I D d 4 s - - _ _ - ~-

which follows directly from ( l ) , Q G and QB are obtained in closed form. The definitions (26) and (27) then imme- diately lead to the following expressions for the capacitances in the triode region

1682 IEEE TRANSACTIONS ON ELECTRON DEVICES. VOL. 37. N O . 7. JULY I Y W

and

Explicit expressions for the integrals fc and f B are given in the Appendix. The conductance gd is given by (18) while g,s = a I D / a V s can be written in analogy to (18) with

and VD in the bracket replaced by 4,ss and Vs, respectively, and the overall sign reversed. To simplify the analysis somewhat, the charge-sharing factor F is treated as a constant when carrying out the differentiations of I D , FG, and F B with respect to Vs and VB. Considering the full dependence of F on Vs and VB would lead to additional terms in (29b), (29c), and (30b). However, the resulting error was observed to be less than 3 %. Expressions similar to (29) and (30) are used by Turchetti er al. [9] for the case of a constant mobility. Here it is shown that the structure of these expressions is essentially preserved if mobility degradation is taken into account.

The influence of velocity saturation and transversal mobility reduction on gate capacitances and surface potential

. . ----- ~

. > I--. ~

c c 22 r ,: INorrna,ised i ha rn r l CO r ': -18' ,' '

Fig. 2 . Influence of velocity saturation and transversal mobility reduction on the surface potential variation along the channel. The curve marked by ( E , --t 00; 8 = 0 ) corresponds to the constant mobility case. ( V ( ; = 5 V . V , , = 2 . 5 V . V , s = V , = O V : L = 1 . 9 p m . )

is shown in Figs. 2 and 3. The function &( y ) can be obtained by integration of (28). The calculation is similar to that utilized above to derive the drain current expression. It can be seen from Fig. 2 that enhanced surface scattering (increasing e ) raises +$ along the channel compared with the constant mobility case (E, -, 00; 8 = 0) . On the contrary, a stronger velocity saturation effect (de- creasing E,) reduces +\. Acting together, the two independent mobility degradation effects cancel each other to a certain degree. Reduced surface potential leads to a rais- ing gate charge. Fig. 3 shows the pronounced effect of velocity saturation on the gate capacitances. The corresponding shift of the saturation voltage to lower values is reflected in the behavior of C,(,.

If the drain voltage exceeds V\atr CLM must be incor- porated in the capacitance model. Thus a two-regions model is suggested to describe the charges. Actually, we write

QG = QCO + Qc\,r. (33) QCO represents the charge coupled with the inner transistor to the left of the pinch-off point L - LD. It is given by the GCA using (24), (28), and (31) as

1 QCO = Kx[ FG 4,s)

(34) The charge e,,, is related to the space-charge region. We suppose that the total charge in this region is dominated by mobile carriers [ 101. This assumption becomes more realistic when the channel length decreases. Thus we set

QGwr = - LD

where ufr,, denotes the velocity the carriers are thought to be moving with through the space-charge region L - LD < y < L . Bearing in mind that is not affected by VD

(35) I D

ZlfiIl

BUDDE A N D LAMFRIED: A CHARGE-SHEET CAPACITANCE MODEL 1683

Fig. 3 . Erect of mobility reduction on gate capacitances C,, and C,,,. The capacitances are calculated without using CLM. ( Vc, = 5 V. V , = Vs = 0 V; W = 50 wm, L = 1.9 p n . )

the differentiation of Q, yields the following expression for C,, at the onset of saturation:

Continuity of C,q, is ensured if (36) equals (29a) at the transition point. This can be achieved by choosing

Inserting vtin into (35) we arrive at a formula for Qc which guarantees' continuous gate capacitances

Performing the corresponding differentiations the capacitances in saturation are written as

(39a)

Ccs,, is similar to (29a) with L and + s D replaced by L - LD and respectively. The derivatives a+,,, / aVs and

The symmetry of (29b) is lost in (39b) due to the dependence of +sat on Vs.

In saturation, field lines emanating from the drain can penetrate the depletion region and reach the gate. Thus an additional charge

is influenced at the gate. In the triode region, the fringing field is shielded by the mobile carriers and Qcf is small. Following Sheu er al. [ 101 the fringing-field capacitance CL,, can be approximated by an expression which inter- polates between the limiting cases VDs = 0 and saturation. It is written as

where C,q,o is calculated from (29a) and (39a) in the triode and saturation region, respectively. The bias-independent unshielded fringing-field capacitance C, is given by [ 1 1 1

~

a+,,,/iiB can-be found from the continuity condition (16).

C,= sW In ( 1 + - [:, sin (2;)). - (42) 7r

The term in brackets in (41) provides for the approximate description of shielding because in strong inversion C,q,o + 0.5 WLC,, as VDs approaches zero. The total gate-drain capacitance is then given by

The calculation of the bulk capacitances C,, and C,, in saturation encounters difficulties. The widening of the depletion area underneath the drain junction causes problems in distinguishing between channel and junction capacitances. Additionally, this effect cannot be separately measured with the equipment used. We therefore follow the ideas leading to (38) to model the bulk charge in saturation writing

QB = QEO - WC,,,X J k a t - VB - UTLD (44)

The bulk charge Q,, related to the GCA region ( y < L - LD) is given by

as can be shown from (25), (28), and (32). The bulk capacitances are found by differentiation of (44) with respect to VD and Vs

46a

1684 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 31, NO. 7, JULY 1990

a L D + w C o x X J + s a t - VB - U T - a VS ( 46b ) where g d is given by (21a).

The expressions for the gate and bulk capacitances according to (29), (39), and (43) as well as (30) and (46) ensure continuity at the saturation point. The capacitances have to fulfill the sum rules

c g g - c g d - cgs - c g b = 0 C b b - c b d - c b s - c b g = 0.

(47)

(48) The capacitances not included in our model can neverthe- less be calculated from the charge expressions. Using (24), (25), (38), and (44) these conditions have proven to be satisfied within numerical error both in the triode region and in saturation. Inclusion of the fringing-field charge (40) does not disturb the validity of (47).

V. RESULTS AND DISCUSSION

The model has been checked by comparison with measured data of NMOS transistors with channel lengths from 9.6 pm down to 1.1 pm and a threshold voltage of about 0.9 V. The test devices were fabricated in an n-well silicon-gate CMOS process at the Fraunhofer Institute for Microelectronic Circuits and Systems in Duisburg. Ca- pacitance measurements were performed using a direct measurement technique adopted from [ 121. A measurement frequency of 100 kHz and a signal amplitude of 50 mVms have been used. For the measurement of Cgs, C g d , and c b , the HP-4275 LCR-meter was calibrated with Vs = V D = V B = 0 V and V , = -3 V. Measuring the bulk capacitance c b d one has to take into account the V, dependence ( VB = 0 V) of the parallel junction capacitance. Therefore, calibration was performed by applying the actual operating point drain bias. Because the calibration procedure cannot distinguish between area and sidewall capacitances the measured c b d and c b s tend to be underestimated by a contribution stemming from the channel sidewall of the junctions.

The gate voltages were chosen to cover the range from weak to strong inversion to demonstrate the capabilities of the charge-sheet approach. All theoretical curves were calculated using the same set of transistor parameters which are summarized in Table I.

The dc output characteristics are depicted in Fig. 4. The overall agreement of measured and calculated curves is good. The discrepancy of the near-threshold characteristics seen in Fig. 4(a) for high drain voltages is attributed to the imperfect description of two-dimensional short- channel effects in our dc model. It is even more pronounced in the output conductance shown in Fig. 5. How- ever, up to intermediate values of VD the modeling of g d

is very good even in weak inversion. Resorting to the idea of drain-induced barrier lowering seems to be necessary to improve the simulation for high drain voltages.

U T

0

n.

0

Drain vo l tage [ V I

O 1

CO - -3 € I

0

' Y

+ + + + + + + + + + +

0

0

0 1 2 3 4 5 Drain vo l tage- [ V I

1

Drain vo l tage [ V I

Fig. 4. Atput characteristics of NMOS-transistors with W / L = 50/1.1 (a), 50/1.9 (b), 3000/9.6 (c). The terminal voltages are Vs = V, = 0 V and V , = 1 { x }, 2 { 0 }, 3 { A }, 4 { + }, 5 V { }. Symbols and solid lines denote measured and calculated quantities, respectively.

TABLE I COMMON NMOS PARAMETERS

fox I 48nm

3.3 v p - 1 ,085 V-'

Yo I 0.4

y1 I 0.012s p-'

BUDDE AND LAMFRIED: A CHARGE-SHEET CAPACITANCE MODEL I685

1

10’1 I 1 I , I , I I I I

Drain voltage [ V I

Fig. 5 . Comparison of measured (symbols) and calculated (solid lines) output conductances for the 1.9-pm device. The terminal voltages are V, = VB = OVand VG = 0.5 ( U } , 1 ( x } , 2 (0}, 3 ( A } , 4 { + } . 5 V { + I .

7 m 0

D

‘k I

U N

Y

a U -

0

0 1 2 3 4 J

Drain voltage [ V I

& + + + + + i

0 C8d

0 1 2 3 4 5

Fig. 6. Gate capacitances for the same transistors as in Fig. 4. Vc has the values0.7 { x }, 1.0 { 0}, 3 { A }, 5 V { + } [(a) and (b)] and0.7 { X }, 1.1 {0} , 1 . 5 { A } , 2 . 0 V { + } ( c ) ( V s = V,=OV).Measuredand calculated curves as denoted in previous figures.

- - - -~~~~-~~..~.~~.~. . . .~. . .~~~~~--- 0 , I I , I , I I , , 3 ) c w

(b)

-------.-..--- ~ . . .~~ .

0 1 2 3 4 5 Drain vo l tage .- [VI

Fig. 7. (a) Calculated bulk capacitances C,, and C,, compared with measurements for the 9.6-pm transistor. The terminal voltages are Vs = VB = 0 V and V , = 0.7 { x }, 1.1 { 0}, and 1.5 V { A } . (b) Simulated bulk capacitances of the SO/ I .9 transistor. The terminal voltages are Vs = VB = OVand VG = 0.7 {-}, 1 { . . . . . } , 3 ( - . - . } . 5 V { - - - } .

The gate capacitances for three channel lengths are il- lustrated in Fig. 6. The calculated curves are smooth also at the transition from the triode region to saturation. This is an inherent feature of our approach resting on the gate charge expression (38). Again, the matching with experimental data is satisfactory.

As expected, neglecting the fixed depletion charge in saturation according to (35) causes some inaccuracy. This becomes evident in the behavior of Cgs near threshold in the short-channel case (see Fig. 6(a)). Regarding the fixed charge in a suitable manner should improve the description. On the other hand, comparing different models foi QGscr, the long-channel results turned out to be rather in- sensitive. The slight decrease of C,, in saturation seen in Fig. 6(c) is, therefore, caused by CLM (compare also with Fig. 3 where CLM is ignored).

Fig. 7(a) shows the bulk capacitances of the 9.6-pm device. A good match between model and experiment is obvious and reflects the adequate fit of the bulk doping N,. The difficulties concerning the calibration method dis- cussed above lead to uncertainties in the measured bulk capacitances. Specifically, c b , becomes negative in saturation and Cb, is pushed by about 30% below the, simulated results for the 1.9-pm transistor. Therefore, only simulations of short-channel bulk capacitances are pre- sented in Fig. 7(b).

Fig. 8 shows the gate-bulk capacitance of the 9.6-pm transistor. Here calibration was performed in very strong

1686 IEEE TRANSACTIONS ON ELECTRON DEVICES. V O L 37. NO 7. JULY I990

I --- - ~ , ~ ~ ----- , . ? . < . ' "

I : I, , 4 ,

T ~ 7~ -1 ~. , ~,~~ r~~ ~ ~ . l -.., ~ ~ - ~ . - ~ I i J

iJrm J G I C ~ ~ ~ I j l l

Fig. 8. Calculated gate capacitance C,c,, compared with measurements for the 9.6-pm transistor. The terminal voltages are V s = VB = 0 V and Vc; = 0.5 { x } , I ( 0 ) . 1.5 {A}, a n d 2 V { + } .

inversion ( V, = VD = VB = 0 V, Vc = 10 V) assuming that at this operating point C,, is approximately zero due to the strong screening property of the high channel charge. A good correspondence between simulation and measurement can be observed. For gate voltages above 3 V (not shown in the figure) c,, becomes nearly constant in the whole voltage range. In these cases, simulations slightly overestimate the measured data.

VI. CONCLUSIONS In this paper we present a MOSFET model which en-

ables the calculation of the drain current and its derivatives as well as the intrinsic capacitances on the same theoretical level of description. The saturation criterion is acquired from the condition of output conductance continuity.

The number of fitting parameters is chosen to be as small as possible. It should be stressed that the capacitance model is developed without introducing any further fitting parameter not contained in the dc model.

The good agreement with measurement proves the model to be useful for analog CAD applications down to channel lengths of about 1 pm provided that the iteration procedure to solve the transcendental equation (6) con- verges rapidly.

Our capacitance model comprises only a reduced set of capacitances which are believed to be the most important to describe the time behavior of the MOSFET [8], namely, the gate capacitances C,,, CSd, and C,, as soon as the bulk capacitances C,, and e h \ . Introducing transcapacitances would extend the region of validity of the model to higher frequencies. On the other hand, we feel that allowing for parasitic effects not included in the intrinsic model tends to a certain extent to mask the shortcomings of the reduced model for higher frequencies.

The modeling of the saturation behavior can be improved by including the fixed depletion charge contribution to Qc. Combined with a proper model of the channel length shortening the theoretical inconsistency between the CLM formalism used and the treatment of the charge in the space-charge layer near the drain could be avoided. The description of the drain-induced barrier lowering in a

tractable way causes, however, serious problems in the charge-sheet formalism. Some improvements could per- haps be achieved for high drain voltages by considering the charge-sharing factor F to be dependent on VD in a suitable manner.

APPENDIX EXPLICIT EXPRESSIONS FOR FG AND FB

Inserting ( I O ) we get from the defining (3 1 ) and (32)

L"X

(A2) Using (1 la) one obtains after a straightforward but lengthy calculation

n

BUDDE AND LAMFRIED: A CHARGE-SHEET CAPACITANCE MODEL 1687

ACKNOWLEDGMENT [ 111 R. Shrivastava and K. Fitzpatrick, “A simple model for the overlap capacitance of a VLSI MOS device,” IEEE Trans. Electron Devices, vol. ED-29. DD. 1870-1875. 1982. The authors would like to thank R . Lackmann for his

1 r. ~ ~~ ~

suppofi concerning the capacitance measurements and F. 1121 K. C.-K. Weng and P. Yang, “A direct measurement technique for small geometry MOS transistor capacitances,” IEEE Electron Device Lerr., vol. EDL-6, pp. 40-42, 1985. Horn for developing a measurement control routine.

REFERENCES I11 H. C. Pao and C. T. Sah, “Effect of diffusion current on the char-

[41

[51

acteristic of metal-oxid (insulator)-semiconductor transistors,” Solid- Stare Electron., vol. 9, pp. 927-937, 1966. J . R. Brews, “A charge-sheet model of the MOSFET,” Solid-State Elecrron., vol. 21, pp. 345-355, 1978. G. Baccarani, M. Rudan, and G. Spadini, “Analytical i.g.f.e.t. model including drift and diffusion currents,” Solid-State and Electron De- vices, vol. 2, pp. 62-68, 1978. F. van de Wiele, “A long-channel MOSFET model,’’ Solid-Stare Electron., vol. 22, pp. 991-997, 1979. P. P. Guebels and F. van de Wiele, “A small geometry MOSFET model for CAD applications,” Solid-State Electron., vol. 26, pp. 267- .. _. 273, 1983.

sistoren,” Solid-State Electron., vol. 13, pp. 789-798, 1970. [6] G. Baum, “Driftgeschwindigkeitssaettigung bei MOS-Feldeffekttran-

Wolfram Budde was born in Dortmund, F.R. Germany, in 1958. He received the Dipl.-Ing. degree in Nachrichtentechnik from the University of Dortmund in 1985.

Since 1985, he has been with the Department of Electron Devices and Circuits, Faculty of Elec- trical and Electronic Engineering of the Univer- sity of Duisburg, F.R. Germany, where he is working in the field of MOS transistor modeling.

*

Wolfgang H. Lamfried graduated in physics from Karl-Man-University, Leipzig, DDR, in 1969. He received the Dr.rer.nat. degree from Fried- rich-Schiller-University, Jena, in 1977.

Since 1985, he has been with the Department of Electron Devices and Circuits at the University of Duisburg, F.R. Germany, where he is engaged in the modeling of short-channel field-effect transistors.

[71 L. D. Yau, “A simple theory to predict the-threshold voltage of shod- channel IGFET’s,” Sdid-Srare Electron., vol 17, pp. 1059-1063, 1974.

[8] Y P. Tsividis, Operation and Modeling of the MOS Transistors. New York, NY. McGraw-Hill, 1987.

[91 C. Turchetti, G. Masetti, and Y Tsividis, “On the small-signal behavior of the MOS transistor in quasistatic operation,” Solid-State Electron., vol. 26, pp. 941-949, 1983.

[lo] B. J . Sheu and P. K. KO, “Measurement and modeling of short-chan- ne1 MOS transistor gate capacitances,” IEEE J Solid-Stare Circuits, VOI SC-22, pp. 464-472, 1987.

Documents

A charge-sheet capacitance model based on drain current modeling