A 30Gb/s 1:4 Demultiplexerin 0.12µm CMOS

A. Rylyakov, S. Rylov, H. Ainspanand S. Gowda

IBM T.J. Watson Research Center

Outline

• Motivation• 1:4 Demultiplexer schematic, building

blocks and design issues• Bulk and SOI CMOS technologies• Measurement results• Conclusion

Motivation

• Evaluate key building blocks in 0.12µm CMOS at data rates above 10 Gb/s

• Explore the portability of bulk CMOS designs to SOI and applicability of SOI to broadband communication

Design Overview

• Half rate• Current mode logic, differential• Full custom layout• No inductive peaking• Nominal NFETs only: no low-Vt devices,

no thick oxide devices• No ESD protection• Design for bulk, then direct map of

physical design to SOI

Block Diagram of 1:4 DemultiplexerD00

D01

D10

D11

DATA

/20°

90°

1:2

CLOCK

1:2

1:2

Block Diagram of 1:2 Demultiplexer

DATA

CLOCK

LatchD

DBC CB

Q

QBLatch

D

DBC CB

Q

QBD0

LatchD

DBC CB

Q

QBLatch

D

DBC CB

Q

QBD1

Latch SchematicVDD

OUTPUT

DATA

400 Ω

CLOCK

VTAIL 2 mA

Buffer SchematicVDD

500 Ω

OUTPUT

INPUT

VTAIL 2 mA

Input Buffer SchematicVDD

INPUT

VTAIL

OUTPUT

Output Stage Schematic

OUTPUT

VDD

INPUT

1kΩ 50Ω

Power Budget

37%53

89 63%

142 100%Everything

44411Output 924.5Input

I/O

45153Buffer B1682Buffer A

20%28142Latch

CORE

Totals(mA) (%)

# of inst

Current (mA)Block

1:4 Demultiplexer Core Layout1:2 DEMUX

Divide by 2

Buffer

DATA

CLOCK

140 µm x 100 µm

D00

D01

D10

D11

Die micrographDATA

D01 D00

1:4 DMUX

CLOCK

D10 D11

SOI Process • Same technology node, tool set and

metallization as existing bulk technologies• Same ground rules• Partially depleted• Normal resistivity substrate (~ 12 Ω cm)

P-Substrate

Buried Oxide

n+ n+P

n+ Gate

Ring Oscillator Performance

7

8

9

10

11

12

13

0.6 0.8 1 1.2 1.4 1.6 1.8

VDD, V

Del

ay p

er s

tage

, ps

Bulk

SOI *

12-stage differential

* SOI CML rings with inductive peaking achieve 5.4 psJ.-O. Plouchart et all, submitted to VLSI 2003

Test Setup

1:4 DEMUXPPG BERT

Clock Source15 GHz

30 Gb/s

7.5 GHz

Bulk chip I/O at 26Gb/sCLOCK13 GHz

DATA26 Gb/s

500 mV

960 mV

600 mVD00

D01

D10

D11

100 ps

SOI chip I/O at 30Gb/sCLOCK

100 ps

500 mV15 GHz

DATA 960 mV30 Gb/s

D00 600 mV

D01

D10

D11

Performance Summary

IDD(mA)

IDD(mA)

Data rate(Gb/s)

Data rate(Gb/s)

90

130

193

105

142

204

16.1

17.7

20.0

231-1

17.7

19.3

22.4

231-1

18.221.11.2

21.126.21.5

26.130.42.0

27-127-1

BULKSOI

VDD(V)

40 Gb/s ?

• Internal divider operational at 20 GHz• BER ~ 10-3

D00 600 mV

100 ps

Conclusions

• A 0.12µm CMOS 1:4 demultiplexer demonstrated at data rates of26Gb/s (bulk) and 30Gb/s (SOI)

• Existing bulk CMOS physical design can be directly transferred to SOI

• SOI CMOS can be used in broadband communication applications