A 1kb 9T Subthreshold SRAM with Bit-interleaving Scheme in 65nm CMOS

Ming-Hung Chang, Yi-Te Chiu, Shu-Lin Lai, and Wei Hwang Department of Electronics Engineering & Institute of Electronics, and

Microelectronics and Information System Research Center (MIRC) National Chiao-Tung University, Hsinchu 300, Taiwan

tako.ee88g@nctu.edu.tw

Abstract—Subthreshold SRAM is a significant approach to reduce power consumption in energy-constrained SoC design. For the ultra-low power consideration, the primary concerns of SRAM are stability and reliability instead of performance. In this paper, the proposed 9T bit-cell enhances write ability by cutting off the positive feedback loop of inverter pair. In the read mode, the isolated read path and storage node enlarge the read SNM. Besides, a 9T subthreshold SRAM is proposed to enable implementation of bit-interleaving structure which achieves soft-error tolerance. The proposed SRAM is able to operate at a voltage as low as 0.3V. One extra virtual ground (VVSS) line is used to reduce the bit-line leakage to ensure the data can be read successfully. A 1kb bit-interleaved 9T SRAM is implemented in UMC 65nm 1P10M CMOS technology to verify the proposed scheme, which operates at the minimum energy point (0.3V) with 5.824pJ energy consumption for one write and one read operation.

Keywords-ultra-low power; subthreshold SRAM; bit-interleaving scheme

I. INTRODUCTION

Embedded SRAMs dominate performance and power consumption in SoC since SRAM blocks usually occupy over half of the system [1]. For power-constrained applications, such as medical instruments, wireless sensor networks, and implantable devices, subthreshold SRAMs and logics are popular utilized to minimize power consumption. However, with the progress of process technology scaling down, designing reliable subthreshold circuits have to face many challenges, including process-induced device variation, serious threshold voltage variation due to dopant fluctuation, and decreasing Ion-Ioff-ratio. These all limit circuit operation especially in ultra-low voltage region.

Conventional symmetric 6-transistor (6T) SRAM fails to perform reliable operation in subthreshold region because of read current disturbance induced static noise margin (SNM) degradation. There have been several previous works on subthresold SRAM for enhancing read reliability. The 8-transistor (8T) SRAM is presented to reduce the read SNM degradation problem by adding two transistors (read buffer) into the 6T bit-cell to block read path and storage node [2], [3]. A 64 kb 8T SRAM utilizes the reverse short channel effect

(RSCE) in the bit-cell, which improves read performance and write margin (WM) without peripheral circuits assisting [3]. Despite tolerant read destruction, undesired read failure still happens if read bit-line discharge owning to leakage from unselected bit-cell. In [4], a fully differential 10T-transistor (10T) bit-cell is proposed for high read stability. The 10T subthreshold SRAM also employs efficient bit-interleaving structure to deal with soft-error immunity. Moreover, a conventional 6T SRAM faces the fundamental confliction of read versus write operation. The Schmitt Trigger II (ST-2) bases on differential sensing subthreshold SRAM, which can cope with the confliction design requirement. A built-in feedback mechanism is also incorporated in the ST-2 to heighten process variation tolerance [5]. In addition to SNM degradation, there are still many critical issues in subthreshold SRAM: write margin degradation, write-half-select disturbance, limited bit-line capability, and sensing margin degradation.

In this paper, a novel 9T subthreshold SRAM with a bit-interleaving scheme is proposed. The stability and performance of proposed scheme is compared among the conventional 6T SRAM, and aforementioned subthreshold SRAM. An overview of this paper is organized as follows. Section II proposes a novel 9T subthreshold SRAM and presents the operating principles and improvements. In section III, the bit-interleaving scheme is discussed. Section IV describes the architecture of the proposed SRAM. We analyze the post-layout simulation results in section V. The final section draws the conclusions of this work.

II. PROPOSED 9T SUBTHRESHOLD SRAM BIT-CELL

The proposed 9T subthreshold SRAM bit-cell is shown in Fig. 1. The 9T single-port SRAM bit-cell contains three word-lines, one bit-line, and one virtual VSS line. MTCMOS design in the bit-cell delivers benefits of saving leakage and increasing WM/SNM. The reverse short channel effect (RSCE) [6] is utilized in access and buffer transistors. In subthreshold region, incurring a little area penalty, the usage of longer channel length lessens subthreshold voltage variation and improves Ion-Ioff -ratio leading to higher performance.

The operation truth table in each mode of the proposed 9T SRAM is shown in Table I. The cell only has one bit-line, BL, for performing read or write operation. WL is enabled both in This research is supported by Ministry of Economic Affairs, Taiwan,

R.O.C., under Grant 99-EC-17-A-03-S1-005. The authors would like to thank Ministry of Education, Taiwan, R.O.C. and ITRI for their support.

978-1-61284-660-6/11/$26.00 © 2011 IEEE 291

read and write mode. WWL, and its complementary signal, WWLb, are enabled (disabled) only in write mode. Besides, the virtual ground signal, VVSS, keeps in VDD and only discharge to ground in read mode.

During hold mode, bit-line leakage current is considerably reduced by cascaded transistors. Because of only a bit-line scheme and the regular-Vt pass transistors, MNP and MNN, are both on, the proposed 9T SRAM is no voltage drop between node Q and node Qc in Fig. 1. The hold SNMs among the recent subthreshold SRAMs are almost the same because of the isolated storage nodes.

In the read mode, MAW is turned off to isolate the read path and storage node, thus eliminating read disturbance. Because of the isolation, its read SNM is nearly the same as its hold SNM. Fig. 2 shows the distribution of read SNM in Monte Carlo Simulation (10000 times) and indicates that the conventional 6T SRAM bit-cell has awful mean (μ) and standard deviation (σ) values. For the 9T and 10T SRAM, the isolation of storage node leads to reliable mean and standard deviation values of read SNM. On the other hand, read-buffer-footers are attached to the foot of each read-buffer (VVSS) in all rows of the SRAM array. In the read mode, all feet of read-buffers remain at VDD except the accessed word, the feet of cells in which are pulled to GND. Besides, the channel length of the read-buffer is increasing to 100nm to improve single ended read delay time. This helps the proposed bit-cell have nearly the same read delay among all the other SRAMs in subthreshold region. The increasing length also decreases the variation of Ion-Ioff-ratio to ensure robust operation.

Writing “1” is the worst case in write operation due to it is much harder to pass “1” than pass “0” through two cascaded n-type access transistors, MAR and MAW. Smaller threshold voltage of access transistors facilitates writing “1” because of decreasing the voltage drop between BL and Q. Therefore, access transistors, MAR and MAW, are utilized by regular-Vt transistors instead of high-Vt transistors. Besides, longer channel length of access transistors, MAR and MAW, also helps to lower threshold voltage because of reverse short channel

effect (RSCE) in the subthreshold region. On the other hand, the utilization of RSCE leads to lower threshold voltage variation [6]. In addition to decreasing threshold voltage of access transistors, VVSS is always keeps in VDD thus helping to write “1”. In the write mode, the proposed 9T bit-cell enlarges write margin by cutting off the positive feedback loop of inverter pair. Fig. 3 shows that the proposed 9T SRAM has the largest write margin among the other subthreshold SRAMs at supply voltage of 0.4V±10% in Monte Carlo (MC) simulation (10000 times). It obviously shows that the proposed 9T SRAM cell has better write-ability and less variation than the others. In addition to write-abillity improvement, the proposed 9T SRAM bit-cell has short write delay time. By cutting off the inverter pair, the write delay time of the proposed 9T SRAM bit-cell is equivalent to the propagation delay from BL through regular-Vt access transistors, MAR and MAW, through inverter A and B to Qc. Thus, the proposed 9T SRAM has shorter write delay than conventional 6T, 10T subthreshold SRAM, and Schmitt Trigger II (ST-2) based SRAM.

Fig. 4 shows the layout view of the proposed 9T SRAM bit-cell. The longer channel length in access transistors, MAR and MAW, and adding pass transistors, MNP and MNN, cost more area comparing to conventional SRAM designs. Although it takes 2 pitches for thin cell layout and costs 55% area overhead relative to the 8T SRAM bit-cell which is presented in [2], the 10T SRAM bit-cell in [4] costs more area overhead than the proposed 9T scheme. Nonetheless, the area penalty of the 9T

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This Workμ=0.078σ=0.014

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6Tμ=0.040σ=0.012

ST2μ=0.045σ=0.012

65nm tech. @25℃ VDD=300mV±10%MC Simulation (10000 times)

Figure 2. Distribution of read SNM in MC Simulation.

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6Tμ=0.096σ=0.074

Figure 3. Distribution of write margin in MC Simulation.

BL

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L

Figure 1. Proposed 9T SRAM bit-cell.

TABLE I. OPERATION TRUTH TABLE OF PROPOSED 9T SRAM

Mode WL WWL WWLb VVSS

Hold low low high high

Read high low high low

Write high high low high

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and 10T cells is acceptable since the 9T and 10T SRAM bit-cell can be formed as bit-interleaving scheme, which deals with soft-errors efficiently. The bit-interleaving scheme will be discussed in the next section. A detail comparison of the novel 9T SRAM bit-cell, conventional 6T SRAM, various subthreshold SRAMs is shown in Table II.

To sum up, the proposed 9T has less normalized area than ST-2 and 10T SRAM which also utilize the bit-interleaving scheme. Moreover, employing the RSCE improves the Ion-Ioff -ratio and read/write speed in subthreshold region.

III. BIT-INTERLEAVING SCHEME

Soft error problem caused by the reduction of critical charge in weak inversion region is an issue recently. That becomes more critical for subthreshold SRAM than those for super-threshold SRAM. Soft error rate increases by 18% for every 10% supply voltage reduction [7]. Accordingly, soft error rate would increase 720% when the supply voltage drops from 1V to 0.3V. Therefore, error correction coding (ECC) and bit-interleaving scheme are two of the solutions to handle multiple bit soft errors efficiently for subthreshold SRAM.

A. Soft Error

Soft errors are caused by radiation of energetic particles, thermal neutrons, random noise, or signal integrity. A soft error is a signal or data which is wrong, but is not assumed to imply such a mistake or breakage. Since the circuit will work correctly again if the data is rewritten, soft errors may flip the data but not change to the circuit. There are some physical methodologies to minimize soft error rate, including judicious device design, critical node isolation using deep N-well structure, using 210Pb free chip package and substrate materials, and increasing the capacitance of critical nodes in layout geometry [8].

Since contiguous bit-cells could be corrupted at one radiation injection, the interleaving scheme takes a benefit that the effect of soft error will associated with different logical words. Most soft error events are single-bit errors. Such single error correction would be quite effective by properly implementing ECC. In [9], ECC can reduce failure rate by over four orders of magnitude. The ECC requires system latency, throughput, and area overhead. However, a non-interleaving scheme may encounter more bit-errors in one word because of continuous bit-cells structure. A soft-error may flip adjacent multiple bits simultaneously. Therefore, more effective and complex ECC design for an acceptable reliability is required [10]. A better way to reduce soft error rate is to implement a SRAM bit-cell with bit-interleaving scheme.

B. Half-Selected Disturbance

Half-selected disturbance occurs in a common 4-to-1 bit-interleaved SRAM array shown in Fig. 5. In each row, bit-cells of words A, B, C, and D are interleaved and share one word-line (WL). During a read/write operation, the column-multiplexers select the bit-lines of accessed columns among words A, B, C, and D. The bit-interleaving scheme decreases numbers of bit-cells in the bit-line, thus reducing bit-line capacitance as well as delay time of charging and discharging. As word-line simultaneously enable all bit-cells including words in non-selected columns, half-selected disturbance happens in these row-selected but column-non-selected bit-cells.

During a read operation with interleaved conventional 6T SRAM, the selected bit-cells and half-selected bit-cells are enabled by word-line simultaneously. Read disturbance unfortunately occurs both at selected bit-cells and half-selected bit-cells. It would result in the same consequence of half-selected disturbance during a write operation. The read SNM of 8T SRAM is much larger than that of the conventional 6T SRAM using a separated buffer for read access. During a read operation with interleaved 8T SRAM, since write-word-line (WWL) of the accessed word is not enabled, the read-half-selected disturbance is eliminated by the isolated storage nodes.

During a write operation, the data are transferred to the storage nodes of the accessed word with the selected bit-lines. Because the write-word-line (WWL) of the accessed word is asserted, the half-selected bit-cells cause the bit-lines to discharge as if the conventional 6T SRAM during a read

Figure 5. Bit-interleaved SRAM array.

Figure 4. Layout view of the proposed 9T SRAM bit-cell.

TABLE II. COMPARISON OF VARIOUS SRAM BIT-CELLS

6T 8T [2] ST-2 [5] 10T [4] This Work

#WL 1 2 1 2 3 #BL 2 3 2 2 1

#VVSS 0 1 0 1 1 Sub-Vt OP no yes yes yes yes

Normalized Area

0.8 1 1.68 1.61 1.55

Half-select disturbance

yes yes yes no no

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operation. The write-half-selected disturbance injures the static noise margin seriously at low supply voltage [11].

The template is used to format your paper and style the text. All margins, column widths, line spaces, and text fonts are prescribed; please do not alter them. You may note peculiarities. For example, the head margin in this template measures proportionately more than is customary. This measurement and others are deliberate, using specifications that anticipate your paper as one part of the entire proceedings, and not as an independent document. Please do not revise any of the current designations.

C. 9T SRAM with Bit-Interleaving Scheme

A write after read scheme is employed for the bit-interleaved subthreshold SRAM in [12]. Nonetheless, extra read operation is required in each write operation, which wrests more overhead power consumptions and takes much delay time.

Furthermore, a low power bit-interleaved 10T subthreshold SRAM is proposed in [4]. In this architecture, write operation slightly affects the hold stability of the non-accessed cells. As shown in Fig. 6, WL is shared by the bit-cells in a row, and W_WL is shared by the bit-cells in a column. The bit-cells would be affected only on the fact that WL and W_WL rise at the same time. There are no write-half- selected disturbances for the half-selected bit-cells, since storage nodes of which are blocked.

The proposed 9T subthreshold SRAM not only strongly improves write-ability comparing to 10T SRAM presented in [4] but also provides efficient bit-interleaving scheme to achieve soft error tolerance with conventional simple error correcting codes.

During read operation, MNA transistors of selected bit-cells and read-half-selected bit-cells are off thus isolating the storage nodes from disturbance noise.

During write mode, write-half-selected bit-cells, including SNM_L and SNM_V in Fig. 7, of the proposed 9T SRAM have nearly the same SNM as hold cells. Although the write-half-selected cells have only one regular-Vt pass transistor (MNP-SNM_L and MN-SNM_V) between the inverter pair, their SNMs are almost the same as the hold SNM. Fig. 8 shows the SNM distributions of write-half-selected 9T SRAM bit-cells and serious SNM degradation of 8T SRAM due to write-half-selected disturbance.

IV. ARCHITECTURE OF THE PROPOSED SRAM

Fig. 9 shows block diagram of the proposed 9T subthreshold SRAM. The SRAM consists of address decoders,

Figure 9. Block diagram of proposed 9T SRAM.

Figure 10. Word-line drivers.

Figure 6. 10T subthreshold SRAM array [4].

SNM_Hold

Din “1”

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WWL1WWL0BL0 BL1write-half-selected

SNM_L

SNM_V

Figure 7. Write mode of the proposed 9T SRAM.

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SNM_Vμ=0.0776σ=0.0136

65nm tech. @25℃ VDD=300mV±10%MC Simulation (10000 times)

8T w_half_selμ=0.0411σ=0.0194

Figure 8. SNM distributions of write-half-selected 9T SRAM bit-cells.

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write drivers, sense amplifiers, word-line pulse width controller, replica column, and storage element. The storage element is composed of bit-interleaved 9T SRAM array that described in the previous sections. A 9T SRAM replica column is designed to automatically adjust the word-line (WL) pulse width for PVT variation tolerance.

A. Address Decoders and Word-Line Driver

An address decoder of a SRAM is a device which converts a n-bit address to 2n select lines to physical words in SRAM array. Since the proposed SRAM performs 4-to-1 bit-interleaved SRAM array architecture, the last significant 2 bits of address (A[1:0]) are decoded to select the accessed columns that going to read or write. The 4 select-signals (sel_A, sel_B, sel_C, and sel_D) select interleaved bit-lines for write drivers and sense amplifiers with multiplexers. The other bits of address (A[5:2]) are decoded to select the accessed row. In other words, the row decoder converts the selected address (A[5:2]) on the address bus to corresponding row address word-lines (WL and WWLb). Fig. 9 shows the row decoder and column decoder of the proposed 1kb interleaved SRAM with 16-bit in each word.

As shown in Fig. 10, row-based word-lines (WL[N] and WWLb[N]) and column-based word-lines (WWL_A~WWL_D) are enabled with the word-line drivers which is controlled by select-signals and read/write-pulse-signal (RP and WP).

B. Pulse Control Circuits and Replica Column

For the single-ended 9T SRAM bit-cells to perform read/write operation, a sense amplifier, a write driver, and a

precharge controller are needed in each bit-line (BL). The circuit of column is shown in Fig. 11. During the precharge period (WP=0 and RP=0), BL is charged to VDD.

During the read mode, all bit-lines would be floating and voltage swing on the selected read bit-lines would be generated according to the selected word content. As shown in Fig. 11, a sense amplifier at the output of multiplexer, which selected the accessed bit-line, will amplify the signal on the accessed bit-line and hold the output data by a latch.

During the write mode, the selected bit-lines would be clamped to the voltage level wanted to write (DIN), and the non-selected bit-lines would be stay in VDD.

1) Read Pulse Control Circuit: The word-line active time in read mode should be long enough for the sense amplifier to function reliably, but it should be turned off soon after the read operation is finished to cut off the marginal compensation current in order to reduce the power consumption [3]. A 9T SRAM replica column and a read pulse control circuit are designed to automatically adjust the word-line (WL) pulse width for PVT variation tolerance (Fig.11). The replica column creates the worst case of discharging the bit-line voltage to ground (All bit-cells save “1”s). It means that it takes the longest delay time for the replica column than any other column. In this way, the replica column can generate the longest word-line pulse width needed for sense amplifier to accurately capture the read data. All of the bit-cells in the replica column are hardwired to “1”s so that the R_ok pulse is generated in every read cycle. Finally, a delay line is inserted in the output of sense amplifier of the replica column to provide enough margin of word-line width for variations tolerance.

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Figure 13. Energy profile of the proposed 9T SRAM bit-cell.

TABLE III. SUMMARY OF THE 1KB SUBTHRESHOLD 9T SRAM

Technology UMC 65nm Memory Size 64x16 (1kb) Layout Area 182.25μm x 45.46μm

Supply Voltage 300mV

Frequency (Worst Case) f = 38.46KHz (@SS, -40°C)

Operation Temperature -40 ~ 125˚C

Write Power 112nW (@TT, 25°C)

Read Power 109nW (@TT, 25°C)

Leakage Current 353nA (@TT, 25°C)

One Read/Write OP Energy 5.824pJ (@TT, 25°C)

BL_rp

Figure 11. The replica column and read pulse control circuit.

Figure 12. The write pulse control circuit.

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2) Write Pulse Control Circuit: The write pulse control circuit is shown in Fig. 12. For write control signal generation, at the positive clock edge, if CEN=0 and WEN=0, the write pulse control circuit will generate a write pulse signal (WP) and disable it by the W_ok pulse. The write pulse signal, WP, properly control the write behavior of the proposed SRAM, including word-line width control and write driver control. The word-line width is implemented as long as possible to ensure a robust write operation.

V. SIMULATION RESULTS

The efficiency of SRAM is usually defined by the energy consumption for one read/write operation. The figure of merit is interesting as it can define the minimum energy point where the most operations can be performed at the least energy. Therefore, the minimum energy operating point is a key point for ultra-low power constrained systems. Fig. 13 shows the energy profile of the proposed 9T subthreshold SRAM per read/write operation at maximum frequency with respect to the supply voltage and the minimum energy point is around 0.25V to 0.3V. As it makes subthreshold variations more serious and leads to slower frequency if lowering the supply voltage, to operate the proposed SRAM at 0.3V is absolutely the best scenario.

To verify the proposed design, a 64-word by 16-bit robust ultra-low power subthreshold SRAM is implemented in UMC 65nm CMOS technology. Fig. 14 shows the layout of the proposed design, and the design profile is summarized in Table III. The post-layout simulation results show that the proposed 1kb subthreshold 9T SRAM can tolerate -40˚C to 125˚C temperature variation and satisfy on all process corners (TT, FNSP, SNFP, SS, and FF corners) with 300mV of supply voltage and 38.46 KHz of frequency (worst case @ SS, -40˚C). Note that the pre-simulation results shown in Fig. 15 say the

worst operating case is at SS corner and -40˚C. The average read power, write power, and leakage current are 0.109μW, 0.112μW, and 0.353μA, respectively. It takes only 5.824pJ energy consumption in average per read/write access.

VI. CONCLUSION

In this paper, a 9T subthreshold SRAM with bit-interleaving scheme is proposed. The 9T SRAM bit-cell enlarges write margin (WM) as well as decreases WM variation by cutting off the positive feedback loop of inverter pair with on peripheral assistant circuit. MTCMOS design in the bit-cell delivers benefits of saving leakage and increasing WM/SNM. Reverse short channel effect (RSCE) is utilized in access and buffer transistors. In subthreshold region, incurring a little area penalty, the usage of longer channel length lessens subthreshold voltage variation and improves on-off current ratio leading to higher performance. Finally, the bit-interleaving scheme of the proposed 9T SRAM addresses the issues of write-half-select disturbance and achieves soft error tolerance with conventional simple error correcting codes.

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Replica array

Figure 14. Layout view of proposed 1kb 9T subthreshold SRAM.

Figure 15. Operating frequency with respect to corners / temperatures (VDD=0.3V).

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