A 1-Ps Resolution Jitter-Measurement Macro

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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 12, DECEMBER 2006 2911

A 1-ps Resolution Jitter-Measurement MacroUsing Interpolated Jitter OversamplingKoichi Nose, Member, IEEE, Mikihiro Kajita, and Masayuki Mizuno, Member, IEEE

AbstractThis paper reports thedevelopment of an in-field real-time successive jitter-measurement macro whose features include1-ps resolution jitter measurement. The newly developed jitter-measurement macro has four key features: 1) interpolated jitteroversampling; 2) a hierarchical Vernier delay line; and 3) feed-forward calibration, each of which helps attain high jitter-mea-surement resolution; as well as 4) an oversampling rate and mea-surement range-control technique. A test chip of the macro hasbeen fabricated in a 90-nm process. It successfully measures smallrandom jitter with 1-ps resolution, and large deterministic jittercan also be measured by extending the jitter-measurement rangeby a factor of 4.

Index TermsCalibration, integrated circuit measurement,jitter measurement, oversampling.

I. INTRODUCTION

WITH THE CONTINUED increases in chip performance

that accompany device-process scaling, the inability to

measure directly the degree of on-chip jitter has become a se-

rious issue, and on-chip jitter-measurement macros [1][6] ap-

pear to be an attractive solution for measuring jitter more pre-

cisely. The most important specifications for these macros are

jitter-measurement resolution and measurable jitter characteris-tics. As shown in Fig. 1, measurable jitter characteristics may be

expressed in the form of jitter histogram [5], [6], jitter spectra

[4], or jitter transience [1][3]. Measurements that produce his-

tograms and spectra are capable of producing fine resolution

(lower than 10 ps) because random measurement errors due to

the noise generated in the measurement macro can be attenuated

by multiple jitter measurements. Unfortunately, these methods

are not capable of measuring overall jitter transience. In contrast

to this, with jitter-transience measurements, it is possible to ob-

tain nonperiodic jitter, such as program-dependent jitter. How-

ever, because of the noise generated in the measurement macro,

it has been difficult to achieve a resolution better than 10 ps. A

conventional 10-ps resolution jitter-measurement macro can beused only for 1) determining whether or not jitter is abnormally

high and 2) roughly estimating main jitter sources when jitter is

abnormally high. However, other jitter sources which cannot be

detected under this limitation could become a serious problem

in next-generation chips, which can be expected to be fabricated

in more advanced processes and to operate faster. Our goal has

Manuscript received June 1, 2006; revised August 18, 2006.K. Nose and M. Mizuno are with NEC Corporation, Kanagawa 229-1198,

Japan (e-mail: [email protected]).M. Kajita is with NEC Corporation, Tokyo 183-8501, Japan.

Digital Object Identifier 10.1109/JSSC.2006.884402

Fig. 1. Conventional expression from on-chip jitter-measurement macros.(a) Histogram. (b) Spectra. (c) Transience.

Fig. 2. Target jitter. (a) Timing difference. (b) Period jitter.

been to achieve fine-resolution jitter measurements while still

being able to obtain overall jitter transience.

The remainder of this paper is organized as follows. Section II

describes our target jitter type and gives an example of measure-

ment implementation. Section III describes key techniques em-

ployed in our proposed jitter-measurement macro. Section IV

reports experimental results for a jitter-measurement macro fab-

ricated in a 90-nm CMOS process. Section V summarizes our

work.

0018-9200/$20.00 2006 IEEE


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2912 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 12, DECEMBER 2006

Fig. 3. Jitter measurement macros in an LSI.

Fig. 4. Jitter measurement circuit overview.

II. TARGETJITTER ANDIMPLEMENTATION

A. Target Jitter

Fig. 2 illustrates two types of jitter measurement: (a) measure-

ment of timing differences [4] and (b) measurement of period

jitter [5], [8]. In (a), timing jitter can be obtained by measuring

the timing difference between a reference clock (REF) and a

measured signal (SIG). In (b), jitter for individual periods is ob-

tained, and timing jitter can also be obtained by accumulating

this period jitter. Results with approach (b) are not, however, ac-curate measurements of timing jitter because measurement er-

rors for individual periods are also accumulated. For example,

when the timing jitter in a 100-cycle clock signal is measured,

the overall error for timing jitter will be up to 100 ps if the error

for individual periods is 1 ps. That is why we chose to use the

timing difference approach.

B. Implementation

Fig. 3 shows an example of the location of jitter-measure-

ment macros in a digital LSI. The LSI has two clock domains,

one for the logic and one for SerDes. Two examples of uses for

jitter-measurement macros are shown: 1) the upper and lowerjitter-measurement macros receive the reference clock to the

PLL and the feedback clock to the PLL and measures the jitter

generated by the PLL and the clock distributions, and 2) the

middle jitter-measurement macro receives clock signals from

the logic and the SerDes and measures the timing jitter between

the two different clock domains. One of the two clock signals is

used as REF and the other as SIG, and knowing the timing jitter

between the two domains is important for creating an interface

between them.

III. JITTERMEASUREMENTMACRO

In order to measure jitter with high resolution, three internal

noise sources in the on-chip measurement macro that degrade

measurement accuracy have to be suppressed. One of the noise

sources is the quantization noise that results from converting

jitter values to quantized digital data. The second is thermal

and 1/f noise in the measurement macro. The third results from

process variations in the measurement macro.

In order to reduce these noises, our newly proposed macro

has four key features:

1) an interpolated jitter oversampling technique to overcome

limitations in measurement resolution resulting from quan-

tization error;

2) an hierarchical Vernier delay line technique for internalnoise reduction;


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NOSEet al.: A 1-ps RESOLUTION JITTER-MEASUREMENT MACRO USING INTERPOLATED JITTER OVERSAMPLING 2913

Fig. 5. Timing diagram and power spectrum for jitter measurement. (a) Conventional jitter measurement. (b) Interpolated jitter oversampling.

Fig. 6. Four-phase clock generator. (a) Schematic. (b) Operation diagram.

3) an oversampling rate and measurement range control

technique;

4) a feedforward calibration technique that improves immu-

nity to process variations while maintaining a small circuitarea.

Fig. 7. Jitter measurement techniques using multiple

Ms. (a) Single.(b) Averaging. (c) Oversampling.

Fig. 8. Simulated jitter-measurement results. (a) Input jitter and internal noisemodel. (b) Simulation results.

Fig. 4 is a schematic of the proposed jitter-measurement

macro. It consists of two sets of 4-phase clock generators, four

small measurable-range jitter-measurement macros referred tohere as micro-measurement macros Ms , four encoders, a


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Fig. 9. Conventional jitter-measurement macro using Vernier clock delay lines. (a) Schematic. (b) Vernier delay cell.

parallel-to-serial converter to serialize the outputs of four Ms

in order to output data using only two digital output ports, and

input selector circuits which determine the input of the M

in accordance with the required measurement resolution and

measurement range. The four separate-phase clock signals for

interpolated jitter oversampling are created in each of the two

4-phase clock generators. Each of these can be fed to one of

the four Ms. Each M has hierarchical Vernier delay lines

in which process variation can be compensated for by digital

codes.

A. Interpolated Jitter Oversampling

Fig. 5(a) shows a timing diagram and a power spectrum for

conventional jitter measurement. The timing difference between

REF and SIG is observed at each cycle, i.e., , , etc. The

spectrum of the timing difference is expressed as a signal spec-

trum whose bandwidth is half of the clock frequency, . The

measured results are converted to quantized digital data, and the

resulting quantization error and internal noise in the measure-

ment macro may be expressed as a noise spectrum. The band-

width of the noise spectrum is half of the clock frequency, ,

the same as the bandwidth of the jitter spectrum, which means

that the noise spectrum cannot be reduced by filtering without

attenuating the jitter spectrum.To reduce the quantization noise, we propose an interpolated

jitter oversampling technique. Although oversampling is a pow-

erful technique for reducing noise, it has not yet been applied to

jitter measurement. This is because jitter is a discrete-time event,

and sampling frequency cannot generally be increased to a level

higher than that of the clock frequency. To increase sampling

frequency above that of the clock frequency, we have introduced

4-phase clock generators which can generate 4-phase signals

from REF and SIG, followed by four Ms which can measure

jitter for each phase. The schematic of the 4-phase clock gener-

ator is shown in Fig. 6. It consists of simple phase-interpolators

and CMOS delay lines. The output of the generator can sepa-

rate the timing of adjacent clock edges at regular intervals. As

shown in Fig. 5(b), the clock generator successfully generates

four sampling points per clock cycle, thus achieving a 4X sam-

pling frequency. If the sampling rate is increased by a factor

of 4, noise intensity will be suppressed by a factor of 4, while

the noise spectrum will be extended from to . The total

amount of noise can then be reduced by attenuating the high-fre-

quency component of that noise by means of a low-pass filter.

That is why interpolated jitter oversampling makes it possible

to suppress noise intensity.

It may seem possible that inaccuracy due to noise compo-

nents might be suppressed by conducting multiple Ms of the

jitter between REF and SIG and averaging the results, and it

is true that an averaging technique like that shown in Fig. 7(b)might help suppress inaccuracy due to internal random noise,

such as the thermal noise and 1/f noise generated independently

by each M. However, this would not be effective with respect

to quantization noise because the same signals are input to all

Ms, and the Ms would contain the same quantization errors.

We compared the effectiveness of these techniques quantita-

tively using the input jitter and internal noise model shown in

Fig. 8(a). This model includes input jitter, internal noise, and

quantization noise. Simulation results are shown in Fig. 8(b).

Oversampling yields values for input jitter much more accurate

than those yielded by averaging.

B. Hierarchical Vernier Delay Line

To measure the jitter with fine- resolution, a jitter-measure-

ment circuit using Vernier delay lines has been proposed [1], [7]

[see Fig. 9(a)]. This circuit contains series-connected Vernier

delay cells [Fig. 9(b)] in which the delays of individual paths

are set at and , respectively, and timing differences

between REF and SIG can be measured at a resolution of by

counting the number of 1s in the output of the 16 comparators.

This design offers a simpler and faster CMOS delay-line-based

structure than does the use of phase-interpolator-based jitter-

measurement macros [3]. However, the latency of the paths in-

creases at a rate proportional to the measurement range. For ex-

ample, in order to support a measurement range of 16 , overall

latency would become 16 . Such an increase in latency would


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Fig. 10. Proposed

M using hierarchical Vernier delay lines. (a) Schematic. (b) Delay controllable Vernier delay cell.

result not only in an increase in internal jitter but also in degra-

dation of the maximum operation frequency.To suppress the latency, we propose a novel low-noise

M circuit that employs hierarchical Vernier delay lines [see

Fig. 10(a)]. It is composed of delay controllable Vernier delay

cells and comparators. Fig. 10(b) shows a schematic of the

delay controllable Vernier delay cell. The delay cell consists

of simple CMOS buffers and tunable load capacitances which

can change the delay of individual paths in accordance with

the delay select code. The delay difference between REF path

and SIG path can be set to 0, , or . The operation of the

hierarchical Vernier delay line is outlined below. In the coarse

delay line, the delay difference of each delay cell is set to .As REF and SIG signals proceed along a coarse delay line, the

timing difference between them decreases by at each Vernier

delay cell. These signals are then fed into fine delay lines in

which the delay difference between individual paths is set at .

The timing differences between comparator inputs in the first

fine delay line are , , , , respectively

( is the timing difference between REF and SIG), and those

in the secondfine delay line are , Thus,

can be determined by counting the number of 1s in the output

of the 16 comparators. Compared with conventional Vernier

delay lines which can support a measurement range of , the

proposed hierarchical structure is able to shorten latency from16 to 4 .

Fig. 11. Oversampling-rate and measurable-range control.

C. Oversampling Rate and Measurement Jitter Range Control

Features of the proposed jitter-measurement macro in Fig. 4include the use of an oversampling-rate and measurable-jitter-


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Fig. 12. Calibration codes for latency and comparator offset compensation. (a) Delay-controllable Vernier delay cell. (b) Offset-tunable comparator.

Fig. 13. Feedforward calibration procedure.

Fig. 14. Latency variation in Vernier delay cell.

range controller to control the relative values of oversampling

rate and measurable jitter range. Fig. 11 describes the three

oversampling modes: 4X, 2X, and 1X. In the 4X oversampling

mode, in which signals are input to Ms from four separate

phase clocks. This mode is the most effective for suppressing

quantization noise intensity while the measurable jitter range is

the sameas thatof a M.In the 1Xoversamplingmode,it ispos-

sible to measure the timing difference between REF and SIG

within the range of 15 in M , and the timing difference

between signals output from M is 16 smaller than the timing

difference between REF and SIG [see Fig. 10(a)]. In M , it

is possible to measure the timing difference between REF andSIG within the range of 16 31 by inputting to M the

Fig. 15. Measured latency variations in

M.

output signals from M . Thus, the measurable range of four se-

rially connected Ms is 4 times larger than that of a single M.

The 1X oversampling mode is used to perform on-chip mea-

surements over a wider jitter range.

D. Process Variation Compensation Methodologies

Device matching constraints play a considerable role in de-

termining the accuracy and performance of the measurementmacro. The main sources of phase spacing variation in Ms are:


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Fig. 16. Calibration data input circuit. (a) FF-based data input circuit. (b) Latch-based compact data input circuit.

1) delay variation in Vernier delay cells and 2) comparator offset

voltage variations that appear as effective phase errors. To alle-

viate the reduction of measurement resolution due to process

variations, our jitter-measurement circuit employs three tech-

niques: 1) a feedforward calibration procedure; 2) the use of

a compact calibration data input circuit; and 3) the use of a

self-precharge offset-tunable comparator.

1) Feedforward Calibration Procedure: To compensate for

the latency variations, a 4-bit code for calibration is placed in

each Vernier delay cell [Fig. 12(a)]. Offset variations in com-

parators can also be compensated for by locating a 3-bit code in

each comparator [Fig. 12(b)]. The main issue in calibration ishow to determine the optimum code for each of the numerous

Vernier delay cells and comparators in the macro. Convention-

ally, offset calibration procedures are mainly based on statistical

analysis [2]. In this analysis, clocks with known jitter, which is

generated by an off-chip jitter generator, are input into the mea-

surement macros. The calibration codes can then be changed

on the basis of the error between the known input jitter and the

measured results, and the jitter is then measured again. There

are two problems with this calibration procedure. One is that an

external jitter generator has to be used. Another is that feedback

calibration requires a complex code decision algorithm and long

calibration time.To overcome these drawbacks, we propose the feedforward

calibration approach shown in Fig. 13. Here, before calibration,

in (a), the same signal is applied to two input nodes on M,

and, in (b), the delay select code in each Vernier delay cell is

then set to zero. In this setting, the timing difference between

the two signals input to the comparators should be zero. Cali-

bration can then be started. First, offset is compensated for

by selecting offset modulation signals for which the probability

of s output being 0 and its being 1 will be the same. Next,

offset and delay line variations in are compensated for

on the basis of the monitoring of output. After and

calibration, no recalibration of is required because the mod-

ulation results for and do not influence offset. In thisway, calibration can be completed without any need to recali-

brate comparators and delay lines that have previously received

compensation calibration. Another feature of this calibration is

thatno external known-jitter generator is required because the

same signal is applied to two input nodes.

Here, the variation in load capacitances in the Vernier delay

cell [ and in Fig. 10(b)] cannot be calibrated with the feed-

forward calibration because the feedforward calibration is con-

ducted with the delay select codes set to zero. However, while

variations in capacitance may remain, variations in latency of

REF path and SIG path can be drastically reduced. This is be-

cause latency in Vernier delay lines is mainly CMOS buffer

delay, which can be compensated for when the delay selectcodes are set to zero. Fig. 14 shows the results for calculation of

variation of latency difference between REF path and SIG path

in a Vernier delay cell. Maximum latency variation is 4.3 ps be-

fore calibration. After calibration, maximum latency variation is

only 0.4 ps, even when delay select codes have been switched.

The measurement results in Fig. 15 are for the integral non-

linearity (INL) of the timing difference between Vernier delay

cell input values in a M. By means of feedforward calibration,

a measured maximum phase spacing error before calibration of

5.3 ps has been successfully reduced to 1.4 ps.

2) Compact Calibration Data Input Circuit: Normally, the

calibration data is fed to all Vernier delay cells and comparatorsby using serially connected flip-flops [Fig. 16(a)]. In order to

avoid the large area overhead that results from a large number of

flip-flops, we use a compact calibration data input circuit which

providesa 7-bit latch cell and a 1-bit flip-flop to each comparator

and delay cell set [see Fig. 16(b)]. Flip-flops change active latch

cell lines sequentially. This design requires only half the area of

a conventionalflip-flop array.

3) Self-Precharge Offset-Tunable Comparator: Fig. 17(a)

shows a schematic of an offset-tunable comparator. It consists

of differential-type latch circuit which is capable of 3-bit

digital offset tuning and an SR-latch circuit to hold the output

data in the precharge phase. With conventional offset-tunable

comparators [2], a special external design is required for dis-tributing precharge clock signals to individual comparators.


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Fig. 17. Offset-tunable self-precharged comparator. (a) Schematic. (b) Operation diagram. (c) Simulated waveforms (evaluation phase). (d) Simulated waveforms(precharge phase). (e) Offset modulation results.

This is unnecessary with our comparators because each is a

self-precharge comparator in which precharge clock signals

are generated on the basis of the two input signals. When both

inputs are low, precharge signal PC also drops to low, S and SB

will be precharged, and the output data, OUT and OUTB, will

be kept on hold. The evaluation phase is from the rising edge

of any of two input signals. In the evaluation phase, either S or

SB will fall to low in accordance with the timing of the rising

of the inputs. The operation waveforms of the comparator

[Fig. 17(c), (d)] show that, when a 90-nm ASPLA process and

1-V supply voltage are used, the input-to-output delay of thecomparator is 140 ps and the precharge time from the fall edge

of the inputs is 120 ps. Fig. 17(e) shows simulated offset-tuning

results. The resolution of offset tuning is smaller than 1 ps.

IV. MEASUREMENTRESULTS

A microphotograph of the macro, fabricated in an ASPLA

90-nm process, is shown in Fig. 18. The area of the macro is

712 m 340 m.

Fig. 19 shows a block diagram of the test system used for

our jitter-measurement macros. It consists of a pulse generator

that can generate signals with jitter, a test chip embedded withon-chip jitter-measurement macros, a data storage memory, and


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Fig. 18. Microphotograph.

Fig. 19. Test system.

a PC. Digital low-pass filtering to attenuate the noise compo-

nents is performed on the PC.

We evaluated the accuracy of the on-chip jitter-measurement

macro by comparing the PC output results to results for jitter

transience obtained with an off-chip real-time oscilloscope.

Fig. 20(a) shows small Rj measurement results. In the 1X over-sampling mode, quantization noise is sharply defined and both

measured peak-to-peak jitter (18.8 ps) and RMS jitter (2.64 ps)

are larger than the oscilloscope results by 5.8 ps and 0.61 ps,

respectively. By way of contrast, in the 4X oversampling mode,

this difference is less than 1 ps for each. Fig. 20(b) illustrates

measurement results of another jitter which contains small Dj.

This result shows that in the 4X oversampling mode, not only

the peak-to-peak jitter and RMS jitter but also Dj characteristics

are well reproduced. Large Dj jitter-measurement results are

shown in Fig. 20(c). Where timing jitter is larger than the

measurable range of a M (15 ) and the 4X oversampling

mode cannot be used, the lower precision of the 1X oversam-

pling mode is far less significant, and results are sufficientlymeaningful.

Fig. 20. Measurement results. (a) Small Rj jitter. (b) Small Dj jitter. (c) LargeDj jitter.

V. SUMMARY

We have developed a novel on-chip jitter-measurement macro

to help achieve jitter-transience measurements with high res-

olution. One technique we use is interpolated jitter oversam-

pling, which can reduce quantization noise. Other techniques

include the use of hierarchical Vernier delay lines and the use of

a feedforward calibration procedure. These help improve reso-

lution over that of conventional jitter-measurement macros that

give transience results. Our jitter-measurement macro success-

fully measures both small random jitter and large jitter with 1 psresolution.


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With our high-resolution jitter measurement, we can analyze

the jitter element in detail in a product chip, and we can detect

individual jitter components, such as random jitter and system-

atic jitter resulting from the bounce. Our proposed design

promises to help improve turn-around time in chip development.

REFERENCES

[1] N. Abaskharoun and G. W. Roberts, Circuits for on-chipsub-nanosecond signal capture and characterization, in Proc. IEEECustom Integrated Circuits Conf. (CICC), 2001, pp. 251254.

[2] D. Weinlader, R. Ho, C.-K. K. Yang, and M. Horowitz, An eightchannel 35 GSample/s CMOS timing analyzer, in IEEE Int.Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers , Feb. 2000, pp.170171.

[3] L.-M. Lee and C.-K. K. Yang, A sub-10ps multi-phase samplingsystem using redundancy, in IEEE Int. Solid-State Circuits Conf.(ISSCC) Dig. Tech. Papers, Feb. 2005, pp. 510613.

[4] M. Takamiya, H. Inohara, and M. Mizuno, On-chip jitter-spectrum-analyzer for high-speed digital designs,in IEEE Int. Solid-State Cir-cuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2004, pp. 350351.

[5] R. Kuppuswamyet al.,On-die clock jitter detector for high speed mi-croprocessors,in Symp. VLSI Circuits Dig. Tech. Papers, Jun. 2001,pp. 187191.

[6] K. A. Jenkins, A. P. Jose, and D. F. Heidel,An on-chip jitter measure-ment circuit with sub-picosecond resolution,inProc. Eur. Solid-StateCircuits Conf. (ESSCIRC), Sep. 2005, pp. 157160.

[7] P. Dudek, S. Szczepanski, and J. V. Hatfield, A high-resolutionCMOS time-to-digital converter utilizing a Vernier delay line, IEEE

J. Solid-State Circuits, vol. 35, no. 2, pp. 240247, Feb. 2000.[8] P. J. Restle, R. L. Franch, N. K. James, W. V. Huott, T. M. Skergan,

S. C. Wilson, N. S. Schwartz, and J. G. Clabes, Timing uncertaintymeasurementson the Power5 microprocessor, inIEEE Int. Solid-StateCircuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2004, pp. 354355.

[9] K. Nose, M. Kajita, and M. Mizuno, A 1ps-resolution jitter-mea-surement macro using interpolated jitter oversampling, in IEEE Int.Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers , Feb. 2006, pp.520521.

Koichi Nose (S99M02) received the B.S., M.S.,andPh.D.degrees in electronics engineering fromtheUniversity of Tokyo, Tokyo, Japan, in 1997, 1999,and 2002, respectively.

In 2002, he joined NEC Corporation, Kanagawa,Japan. His research interests are in the area ofsignal integrity, high-speed clocking, and wirelesstechnologies.

Mikihiro Kajitareceived the B.E. and M.E. degreesin applied physics from the University of Tokyo,Tokyo, Japan, in 1990 and 1992, respectively.

In 1992, he joined the Opto-Electronics ResearchLaboratories, NEC Corporation, Tokyo, Japan.Since 1997, he has been with the Computers Divi-sion, where he has worked on the development of

high-performance computers.

Masayuki Mizuno (M94) received the B.S., M.S.,and Dr.Eng. degrees in electronic engineering fromOsaka University, Osaka, Japan, in 1991, 1993, and2000, respectively.

In 1993 he joined NEC Corporation, Kanagawa,Japan, where he has been engaged in the research

and developmentof low-powercircuit techniques, theworlds firstsingle-chip MPEG2 video encoder LSIs,high-speed clocking techniques especially for NECssupercomputers, and high-speed serial links. Duringa leave from 1999 to2000, he engaged inthe research

of interconnection network for chip multiprocessors at Stanford University as avisiting scholar. Currently, his research interests lie in signal/power integrity, ro-bust design for nanoscaleCMOS devices, and low-powerwirelesstechnologies.

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A 1-Ps Resolution Jitter-Measurement Macro