A 0.56 THz Phase-Locked Frequency Synthesizer in 65 nm ...download.xuebalib.com/w0blb8iGv7A.pdf14 architecture for the ﬁrst ILFD. The resultant prototype realizes 15 a 21 GHz frequency

This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.

IEEE JOURNAL OF SOLID-STATE CIRCUITS 1

A 0.56 THz Phase-Locked Frequency Synthesizerin 65 nm CMOS Technology

Yan Zhao, Senior Member, IEEE, Zuow-Zun Chen, Yuan Du, Student Member, IEEE, Yilei Li, Student Member,IEEE, Richard Al Hadi, Senior Member, IEEE, Gabriel Virbila, Yinuo Xu, Yanghyo Kim, Student Member, IEEE,

Adrian Tang, Senior Member, IEEE, Theodore J. Reck, Senior Member, IEEE,and Mau-Chung Frank Chang, Fellow, IEEE

Abstract— This paper presents the design and characterization1of a 0.56 THz frequency synthesizer implemented in standard265 nm CMOS technology. Its front end consists of triple-3push Colpitts oscillators (TPCOs), followed by the first and4second stage injection locking frequency dividers (ILFDs) and a5divide-by-16 chain. TPCOs are used to triple their fundamental6frequencies to 0.53–0.56 THz, while ILFDs and the subsequent7divider chain are used to divide such frequencies to 2.7–2.9 GHz.8Its back end consists of separate frequency and phase-locked9loops with unique CMOS circuit designs to accomplish the10desirable frequency/phase locking, including: 1) band-selection11inductor switches; 2) simultaneous bulk voltage tuning over12TPCOs and the first ILFD; and 3) a dual port injection13architecture for the first ILFD. The resultant prototype realizes14a 21 GHz frequency locking range with phase noise lower than15-74 dBc/Hz at 1 MHz offset, and consumes 174 mW dc power.16

Index Terms— Bulk voltage tuning, frequency synthesizer,17harmonic oscillator, injection locking, phase-locked loop (PLL),18subsampling phase detector, terahertz, triple-push Colpitts19oscillator (TPCO), triple-push oscillator (TPO).20

I. INTRODUCTION21

TERAHERTZ (THz) frequencies between 500 and22 600 GHz play a critical role in planetary and Earth23science, as many important chemical species including several24isotopes of water, nitrates (NO2, N2O, NH3), and some25organics (CH4 and HCN) offer spectral responses (absorption26or reflection based) in this band. NASA, ESA, and other27space agencies have developed a wide range of remote sensing28spectroscopic instruments in the submillimeter-wave regime,29

Manuscript received April 19, 2016; revised June 21, 2016; acceptedAugust 10, 2016. This paper was approved by Guest Editor Antonio Liscidini.This work was supported in part by the U.S. Air Force Office of ScientificResearch under Grant FA9550-12-1-0181 and in part by the U.S. ArmyResearch Office under Grant W911NF-14-1-0665.

Y. Zhao, Z.-Z. Chen, Y. Du, Y. Li, R. Al Hadi, and Y. Xu are with the HighSpeed Electronics Laboratory, University of California at Los Angeles, LosAngeles, CA 90095 USA (e-mail: [email protected]).

G. Virbila is with HRL Laboratories, LLC, Malibu, CA, USA.Y. Kim, A. Tang, and T. J. Reck are with the Jet Propulsion Laboratory,

Pasadena, CA 91109 USA.M.-C. F. Chang is with the High Speed Electronics Laboratory, University

of California at Los Angeles, Los Angeles, CA 90095 USA, and also withNational Chiao Tung University, Hsinchu 300, Taiwan (e-mail:[email protected]).

Color versions of one or more of the figures in this paper are availableonline at http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/JSSC.2016.2601614

such as the Heterodyne Instrument for the Far-Infrared on- 30board the Herschel Space Telescope, providing insight into 31the gas dynamics of young galaxies and new star formation; 32the Microwave Instrument for the Rosetta Orbiter aboard the 33Rosetta spacecraft, which previously investigated H2O emis- 34sions from Comet 67P in our solar system; and submillimeter 35wave instrument (SWI) on the upcoming Jupiter Icy Moon 36Explorer mission to the Jovian system, which will investigate 37the structure, composition, and thermophysical properties of 38Jupiter’s atmosphere and the exo-atmosphere of its moon, 39Europa. Key to the success of these instruments is a wideband, 40relatively low phase noise local oscillator (LO) source for 41these THz spectroscopic receivers. Low phase noise is required 42to obtain the high spectral resolution needed for making a 43clear distinction between close-lying chemical species, while 44the wide bandwidth is required to capture as many species as 45possible with a single instrument. Additionally, for instruments 46planned to rendezvous with outer planets (Saturn, Jupiter, 47Uranus, etc.), power consumption of the LO remains critical 48as little sunlight or other spacecraft power is available. 49

Current LO chains for NASA and other spectroscopic 50receivers are implemented in expensive, power hungry, and 51heavy metallic waveguide assemblies. For example, the 52planned THz LO chain of the 600 GHz spectrometer on 53the SWI instrument begins with a 33 GHz phase-locked 54loop (PLL), which is then tripled by a discrete waveguide 55tripler to 100 GHz, doubled by a proceeding doubler to 56200 GHz, and then tripled again to 600 GHz with another 57tripler component. In all, this LO chain consumes well over 588 W of dc power and provides phase noise levels of about 59−70 dBc/Hz at 100 kHz offset at the 600 GHz LO port. 60

Advances in CMOS technology offer a pathway to reduce 61the size, weight, and dc power of these instrument LOs, 62while maintaining the wide bandwidth and low phase noise 63required for preserving the fidelity of science data. Reducing 64the size, weight, and power enables the possibility of car- 65rying more instruments on one spacecraft to explore more 66chemical species, or even the possibility of larger array-based 67instruments that can provide scientific data with higher spatial 68resolution and more overall instrument sensitivity to identify 69chemicals. 70

Fig. 1 summarizes the recent works on the THz frequency 71synthesizer. To date, frequency synthesizers with LO fre- 72

0018-9200 ©2016 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.


2 IEEE JOURNAL OF SOLID-STATE CIRCUITS

Fig. 1. State-of-the-art monolithic integrated PLL works.

Fig. 2. Different THz synthesizer architectures. (a) Low frequency VCO +frequency multiplier. (b) THz VCO directly.

quency around 300 GHz have been demonstrated in InP and73SiGe HBT technologies [1]–[3], which confirmed the potential74of implementing THz LO in IC technologies. However, there75is still no IC work supporting LO frequency synthesizing at76the scientifically important frequency band between 500 and77600 GHz. It would be beneficial to further develop frequency78synthesizers at this band using mainstream CMOS technolo-79gies with larger integration and lower power than that of SiGe80HBT counterparts. Although VCOs/multipliers [4]–[7], [9]81have been developed at these frequencies, the realization of82wide-bandwidth and low phase noise synthesizers remains83challenging.84

This reported 560 GHz frequency synthesizer work, partly85presented in [11], is intended to dramatically reduce the size,86weight, and power consumption of the existing LO chain used87in space submillimeter wave listening equipment. Our paper is88therefore organized as follows. Section II describes the system89architecture, followed by Section III to discuss the circuit90design issues for THz VCO, frequency divider, wide tuning91front end, and low noise back end. We then discuss circuit92implementation and characterization results in Section IV, and93conclude this paper in Section V.94

II. SYSTEM ARCHITECTURE95

The conventional way of building a sub-mm-wave frequency96synthesizer starts from a lower frequency VCO associated97with a frequency multiplier chain as shown in Fig. 2(a).98Such an approach typically consumes higher power due to99the power hungry frequency multiplication process, which also100requires bulky and heavy waveguide assembly at (sub)-mm-101wave frequencies. These disadvantages dramatically increase102

the payloads of space instruments, rendering us to look for 103better solutions to address the power consumption, size, and 104weight issues. For instance, the architecture shown in Fig. 2(b) 105may consume less power but requires VCO and injection- 106locked divider to run directly at the desired THz frequency and 107faces vital challenges from the VCO and divider designs based 108on any transit-time limited silicon device. First, as summarized 109in Fig. 3(a), the state-of-the-art THz oscillators operating near 110550 GHz can only deliver limited signal power per oscillation 111unit (SiGe: −12 dBm [6], CMOS: −18 dBm [7]), hardly 112able to injection-lock any following divider. Second, even the 113fastest frequency divider can only operate up to 260 GHz with 114less than 1% locking range [8] under such low injection power 115as illustrated in Fig. 3(b). 116

Harmonic oscillator can be used to address the challenges 117from the above architecture. In recent years, multipush oscil- 118lators in silicon technologies have been used to enhance the 119harmonic output power at the THz regime while running at 120a substantially lower fundamental frequency. By incorporat- 121ing it into the THz PLL, the first stage frequency divider 122only needs to run at the fundamental frequency. A popular 123topology is based on a ring-type oscillator scheme with a 124multipush output [2], [12]. Such a topology is compact and 125able to output higher power. However, it cannot be easily 126transitioned to subsequent injection-locked frequency dividers. 127Two schemes were proposed in the past to accomplish such 128purpose. One is by feeding three fundamental currents from 129each ring stage to a three-phase ÷4 ring-type divider via 130three transition stages implemented as varactor-tuned Colpitts 131oscillators [2]. This idea requires very careful design in terms 132of layout symmetry in the ring topology. Another method is 133by magnetically coupling fundamental currents between two 134identical ring oscillators in differential mode via a transformer 135with inductance equivalent to that of the original resonant 136inductor [13], [14]. This concept can be theoretically applied 137between the ring oscillator and the divider, but due to very low 138coupling coefficient of the transformer at such high frequency, 139it can barely couple enough power to injection-lock the divider. 140

To explore new solutions, we have investigated star-type 141multipush oscillators with multiple identical oscillators con- 142nected at a common push node (CPN), where the targeted 143harmonic can be combined in phase. The most popular topol- 144ogy is a push–push type of Colpitts oscillator, which operates 145at half the output frequency but delivers a combined second 146harmonic output power at its CPN. The fundamental frequency 147may be further reduced by extending this idea to triple- 148push, quadrature-push, quintuple-push oscillators, and so on. 149However, once the coupled oscillator number increases, the 150number of unwanted oscillation modes also ramps up to defeat 151the wanted mode [15], [16]. Thus, considering the tradeoff 152between achievable fundamental frequency and oscillation 153mode complexity, we choose to build our PLL with a triple- 154push oscillator (TPO) topology. 155

Having a star-type TPO, the first stage frequency divi- 156sion scheme can be drawn as in Fig. 4. The 560 GHz LO 157signal is obtained from the CPN joined by three identical 158oscillators with a 120° phase shift from each other. Injec- 159tion locking is accomplished by coupling one oscillator’s 160


ZHAO et al.: 0.56 THz PHASE-LOCKED FREQUENCY SYNTHESIZER IN 65 nm CMOS TECHNOLOGY 3

Fig. 3. State-of-the-art works on (a) THz oscillator and (b) frequency divider.

Fig. 4. Problems of injection locking at THz regime.

fundamental (187 GHz) current to the first stage frequency161divider. Due to the divider’s low sensitivity at such high162frequency, a multistage buffer must be used in front, but it163is either power hungry [17], [18] or larger sized [18], [19]164in 65 nm CMOS. Therefore, we adopt a mutual injection165locking scheme originated from [7] where a differential current166coupling structure is implemented to synchronize a 2×4 TPO167array. Oscillators here need not drive any load but share their168fundamental ac currents in differential mode with adjacent169oscillators as depicted in Fig. 5(a), which has no loading effect170on oscillator’s operation and no impact on oscillator’s swing171as the coupling node is virtually grounded. Another advantage172is natural synchronization among all the oscillators without the173need for amplifiers among them. Similarly, we also implement174such idea to synchronize the TPO and frequency divider as175shown in Fig. 5(b). Although their circuits are asymmetric,176a pseudodifferential current coupling can still stand between177them when their frequency mismatch is minor. Also more178importantly, it allows a bidirectional current injection and179supports a much wider frequency locking range than the180conventional one-directional current injection. Such a unique181method on injection locking between two circuits will be182elaborated in Section III.183

III. CIRCUITS DESIGN CONCEPTS184

A. Design of the THz VCO185

As indicated in Fig. 5(b), each of TPO’s oscillators is186required to offer two separate ports for its fundamental oscil-187lation current to enable triple pushing as well as mutual188injection locking. Such TPO cannot be implemented by using189a conventional Colpitts oscillator as shown in Fig. 6(a), which190only allows one port of the fundamental oscillation current191

Fig. 5. Proposed system architecture with new synchronization mechanismbetween oscillator and first stage frequency divider. (a) Differential currentcoupling introduced in [7]. (b) Pseudodifferential current coupling used in thispaper.

Fig. 6. Oscillator comparison. (a) Colpitts oscillator. (b) Modified Colpittsoscillator.

flowing between VDD and the ground through LD and two 192capacitors C1 and C2, while another fundamental current flows 193internally between transistor Q1 and capacitor C2. Instead, 194we use a modified Colpitts oscillator, as shown in Fig. 6(b), 195to fulfill the aforementioned structural needs, in which the 196major resonant inductor (LG) is connected to the gate and 197an auxiliary inductor (L D) is connected to the drain. Two 198capacitors C1 and C2 are relocated to form a positive feedback 199loop. This topology provides the two required ports (VDD and 200VGG) carrying the fundamental ac currents and can fit into our 201system architecture. 202

The oscillator’s frequency can be tuned by varying nMOS 203transistor’s p-type bulk voltage, which is isolated by an 204ion-implanted n-well. As the bulk voltage increases, the 205depletion region width of the source and drain bulk p-n 206junctions decrease, resulting in higher parasitic capacitances 207



Fig. 7. Comparing nMOS bulk voltage tuning with varactor tuning in simulation. (a) Input impedance of bulk voltage tuned Colpitts oscillator. (b) Inputimpedance of varactor tuned Colpitts oscillator. (c) Series input negative resistance versus VCT L . (d) Series input capacitance versus VCT L .

Csb and Cdb. Compared with using a traditional varactor,208such a method enables a wider tuning range and less Q-209factor degradation at the intended fundamental frequency210(187 GHz) and avoids using the dc block capacitor. Its211advantages can be further confirmed by comparing the input212series capacitance and the negative resistance of two running213methods when looking into the gate of the Colpitts core.214Fig. 7(a) and (b) shows two Colpitts VCOs with bulk215voltage and varactor tuning, respectively. C1 is the only216option for using varactor because nMOS internal CGS is217large enough to serve as C2 at such high frequency. For218comparison, Q1 and Cv1 are based on our hybrid model219built in a similar way as in [13] and [14], while LG , LD,220C1, C2, RCTL, LBLK, and CBLK are all ideal with the221same values for both the circuits. In Fig. 7(a), a 1 k�RCTL222limits dc current when nMOS source-bulk and drain-bulk223junctions are forward biased at a high VCTL (>0.8 V).224In Fig. 7(b), the extra CBLK serves as a DC blocker, allowing225VCTL to be applied at the gate of CV1. A stronger negative226resistance (with a real part of ZGin) can be observed in227Fig. 7(c) from the bulk-voltage tuned VCO at the fundamental228frequency. In addition, Fig. 7(d) confirms that a wider tuning229range is offered by the nMOS bulk voltage tuning method.230

Circuit techniques involving the inductor switch are often231used at RF and microwave frequencies to broaden VCO’s232frequency tuning range [20], [21]. However, switches imple-233mented using deep-scaled CMOS devices can significantly234degrade the Q-factor of the inductor and frequency tuning235range at the intended frequency regime due to their high236ON-state channel resistance (RON) and high OFF-state drain237capacitance (COFF). Such problems in the CMOS Colpitts238

oscillator may be circumvented by applying the switch on 239the AC block inductor LBLK at the source with a shunt 240capacitor (C1) to lessen the Q-factor degradation and broaden 241the frequency tuning range. The effectiveness of such a method 242can be validated by comparing two circuit designs with 243transmission-line (T-line) type inductors as shown in Fig. 8. 244The first is the 20 pH gate inductor LG implemented as a 24550 μm-long TLG attached with an nMOS switch in Fig. 8(a); 246the second is the parallel circuit of the 17 fF source capaci- 247tor C1 and the AC block inductor implemented as a 200 μm- 248long (λ/4 at 187 GHz) TLBLK with the same nMOS switch 249as in Fig. 8(a). The comparison will be made by simulating 250the parameter variations, such as the relative inductive and 251capacitive tuning ranges (�L/L and �C/C) and the circuits’ 252Q-factors under the ON and OFF states (QON and QOFF), over 253various switch locations along the T-lines. The simulations are 254carried out by breaking T-lines into multiple series 2 μm T-line 255units whose models have been confirmed by full-wave elec- 256tromagnetic (EM) simulations. Simulation results for the two 257circuits TLG and C1//TLBLK are plotted in Fig. 8(c) and (d), 258respectively, by defining the x-axis “n” as the length ratio 259between TL1 (the T-line section which is short cut by the 260nMOS switch) and the entire T-line. Under a reasonable 261assumption to sustain a minimum Q-factor of 15 for both 262QON and QOFF, we find that the equivalent inductance at 263the gate LG is changed up to 3% at n = 0.08, shifting 264the fundamental oscillation frequency by 1.2 GHz; while the 265equivalent capacitance at the source C1 is changed up to 13% 266at n = 0.065, shifting the fundamental oscillation frequency by 267more than 3.5 GHz. Note that the 47.8 fF COFF, 4.9 �RON, and 2685 pH pin inductance in Fig. 8(a) and (b) are assumed according 269



Fig. 8. Advantage of applying inductor switch on AC-block inductor at source over applying on resonant inductor at gate. (a) Source capacitor C1 parallelto 200 μm-long (λ/4 at 187 GHz) ac-block T-line, which is equivalent to 100 × 2 μm T-lines with a lump model matched to EM simulation. (b) 50 μm-longT-line (20 pH inductor), which is equivalent to 25 × 2 μm T-lines with the same lump model. (c) Simulated relative inductance tuning range �L/L =(LOFF-LON)/[(LOFF+LON)/2], Q-factor at switch OFF and ON states. (d) Simulated relative capacitance tuning range �C/C = (COFF-CON)/[(COFF+CON)/2],Q-factor at switch OFF and ON states. Note: switch transistor is based on RF model with 5 pH parasitic pin inductance.

Fig. 9. Schematic of the THz VCO.

to the model built in the similar way as in [13] and [14].270Also, the ohmic and inductive parasitic of C1 are ignored271here as its Q-factor can easily be >100 when built from two272thin metal layers with an interlayer silicon dioxide dielectric.273As a result, the impact of COFF and RON of the nMOS switch274is mostly alleviated by our proposed switch circuit technique.275

The THz VCO schematic presented in Fig. 9 takes the276above considerations into account. Three identical modified277Colpitts oscillators described in Fig. 6(b) are joined at their278VDD ports in a star topology for the triple push output. In279each Colpitts oscillator branch, a common control voltage280

Fig. 10. Possible connections between TPCO and cross-couple frequencydivider.

Fig. 11. Active load modulation issue. (a) Differential circuit. (b) Nondif-ferential circuit.

VCTL is applied on all the transistors’ bulk contacts, and the 281inductor switches are attached to three AC block inductors to 282boost the simulated frequency tuning range up to 30 GHz. 283



Fig. 12. Codesign of the first stage divider with TPCO. (a) Schematic. (b) Operation mode in vector plot.

Fig. 13. Simulated frequency tuning range alignment between VCOs (primary + auxiliary TPCOs + SECO) and the first stage divider. (a) VSW1 = 0 V andVSW2 = 1 V. (b) VSW1 = 1 V and VSW2 = 2 V.

A matching network matches the CPN node to 50 � at the284third harmonic frequency. The even oscillation mode is not285possible as the designed negative resistance looking into the286drain of each oscillator is weaker than one-third of the 50 �287load at the fundamental frequency.288

B. Codesign of the First Stage Divider With the VCO289

A few obstacles remain for implementation of the mutual290injection locking scheme to conduct the first stage frequency291division proposed in Section II.292

The first issue is the DC voltage mismatch. With VDD 293port shared among three oscillators in Fig. 9, the VGG port 294will be used for locking the first stage divider. As shown 295in Fig. 10, four optional nodes are available in a cross- 296coupled frequency divider to receive the injection signal. For 297options (1) and (3), the dc voltage mismatch to oscillator’s 298VGG (0.5 V) is the primary concern as the divider’s VDD is 2991 V and the common source node is 0.4 V. The DC block 300capacitor is needed, but is hard to design with low insertion 301loss. 302



Fig. 14. Boosting first divider’s locking range by dual-port injection. (a) Equivalent circuits of the divider. (b) Simulated locking range versus phase delaybetween two injection ports.

Fig. 15. Design of second ILFD. (a) Schematic. (b) Simulated locking range.

Fig. 16. Block diagram of the THz PLL front end.

In addition, active load modulation is the second concern,303even for those optional pins without the DC voltages mismatch304issue, such as (2) and (4). Because of a differential topology305

in Fig. 11(a), the single inductor LG is equal to half the total 306differential inductance (assuming zero mutual inductance); but 307if connected with an arbitrary impedance Z L and unbalanced 308



Fig. 17. Simulated performance of the on-chip antenna. (a) Antenna model. (b) Antenna gain radiation pattern (E- and H -planes) with 60% efficiency.(c) S11 of the feed port. Note: the simulation results are for a 4 mm silicon lens with 0.55 mm extension; simulation results on larger lens are not availabledue to limited computation resource.

Fig. 18. Block diagram of the synthesizer system including both front endand back end.

excitations as in Fig. 11(b), the LG and its Q-factor may309be contaminated. This happens when connecting triple-push310Colpitts oscillator’s (TPCO’s) VGG to the divider’s injection311port as the two circuits provide different impedance and312operate on different amplitudes. The divider pulls TPCO into313a wrong oscillation mode as the triple-push topology becomes314asymmetric. Consequently, the fundamental currents from the315

three oscillator branches are not 120° (odd mode) to each 316other anymore, and the third harmonic output power will fade 317dramatically when the in-phase condition is broken. 318

The last issue is the narrow locking range of the divider, 319which limits that of the whole front end. The simulated 320frequency tuning range of TPCO can cover 30 GHz, while that 321of the cross-coupled frequency divider is less than 0.5 GHz 322when it is injection locked through any of four ports by the 323TPCO in Fig. 10. 324

Considering all the issues previously mentioned, we 325codesigned the first stage injection locking frequency 326divider (ILFD) with the TPCO in Fig. 12(a), where two 327extra blocks [an auxiliary TPCO and a single ended Colpitts 328oscillator (SECO)] are inserted between them. The first three 329blocks (the primary, the auxiliary TPCOs, and SECO) are syn- 330chronized by the proposed differential current coupling used 331in [7], while the SECO and the first ILFD are synchronized 332by pseudodifferential current coupling. The auxiliary TPCO 333serves to protect the primary TPCO from being unbalanced 334by the loading effect of the first ILFD due to the active load 335modulation issue mentioned before. For better understanding 336of the protection mechanism, Fig. 12(b) shows the vector plot 337of the primary and auxiliary TPCOs based on simulation. 338



Fig. 19. Block diagram of (a) SSPD. (b) Timing diagram.

Fig. 20. Die photo (1—on-chip antenna; 2—primary TPCO; 3—auxiliaryTPCO; 4—SECO; 5—first ILFD; 6—second ILFD; 7—48–2.9 GHz dividerchain; 8—back end; 9—SPI).

The lower branch of the auxiliary TPCO runs at a smaller339magnitude due to the loading effect of the divider, forcing340the other two branches running at 170° out of phase. Thus341the auxiliary TPCO operates at an irregular mode with no342capability of delivering third harmonic with enhanced power,343but it allows the primary TPCO to work in the wanted mode344with a progressive 120° phase shift. To address the DC voltage345mismatch issue between the VGG of auxiliary TPCO and the346VDD of first ILFD, the SECO is added as a bridge in between.347The auxiliary TPCO and SECO consume 25 and 8.3 mW from3481 V supply, respectively.349

The frequency tuning method in Fig. 12(a) features the350following key techniques. First, the first ILFD’s frequency351is tuned together with TPCOs and SECO by varying their352bulk voltages of cross-coupled devices. Second, a similar353inductor switch Q8 truncates the resonant inductor LT of the354divider, aligning the divider’s tuning curves to that of two355TPCOs + SECO with frequency error less than 1 GHz, as356simulated in Fig. 13(a) and (b) under both the switch ON and357OFF states. Although auxiliary TPCO operates in a different358mode, the locking stability among two TPCOs and SECO is359very robust as they are all based on the identical Colpitts360oscillator core. It is important to note that the lower operation361frequency (94 GHz) of the divider allows a direct application362of switch on the 120 pH resonant LT with an acceptable363

Fig. 21. Measurement setup. (a) Spectrum measurement. (b) Power mea-surement with 1 cm distance.

Q-factor. To avoid the unlocking issue due to the 1 GHz 364frequency error, the third technique enhances the locking range 365of the divider beyond 2 GHz by injection locking it via dual 366ports: one via the center tap of LT and another via the gate 367of a passive switch Q7 [Fig. 12(a)]. The phase delay between 368the two injection ports (nodes A and D) is optimized. In an 369equivalent circuit in Fig. 14(a), the 187 GHz injection current 370IINJ first reaches the center tap of LT (node A), then partially 371flows into two arms of LT , resulting in two in-phase currents 372IIP and IIN near node A. They turn out to be ITP and ITN 373at drains of Q5 and Q6 (nodes B and C) after experiencing 374a phase shift ϕT due to the total parasitic capacitance CT 375and resistance −RC contributed by LT , Q5 and Q6. In the 376meantime, the remaining part of IINJ flows along LS and 377reaches the gate of Q7 (node D) with a phase delay of ϕS, 378then splits into two 187 GHz in-phase currents ISP and ISN 379at nodes B and C through the intrinsic capacitors CGS7 and 380CGD7 of the switch Q7. When ISP(ISN) andILP(ILN) are both 381in phase, the dual-port injections enhance each other, and 382vice versa. A simulation study shows the maximum 4.5 GHz 383locking range at a 180° phase delay between nodes A and 384D in Fig. 14(a). A wider range of phase delay (from 100° 385to 310°) can be chosen to obtain >3 GHz locking range and 386cover the frequency alignment error in Fig. 13. The typical 387issue of phase polarity ambiguity happens at the fundamental 388frequency of ILFD, but does not affect the optimized phase 389delay between two injection ports at the second harmonic 390frequency as the injection currents are at even mode. 391

The second stage ILFD, operating at 1/12 of the output 392THz frequency, was tuned with digital controlled artificial 393



Fig. 22. Measured locking range of the THz synthesizer with corresponding settings of inductor switches and DiCAD.

Fig. 23. Phase noise measurement results, 559.89 GHz tone in (a) 10 MHz span and (b) 10 kHz span. (c) Phase noise curve compared with our 30 GHzPLL [29] (red dashed curve) using the same back end and divider chain from 47 to 2.9 GHz. (d) Simulated phase noise contribution from different blocks.

dielectric (DiCAD) [22] shown in Fig. 15(a), providing a394locking range between 41 and 52 GHz over 32 programmed395subchannels.396

C. Front-End Overview397The front-end design of the proposed THz PLL is depicted398

in Fig. 16, summarizing the aforementioned operation and key399

techniques. The THz LO signal is obtained from the CPN 400of the primary TPCO, protected by the auxiliary TPCO from 401being unbalanced due to the loading effect of the first stage 402ILFD. Between the auxiliary TPCO and the first ILFD, a 403SECO block is inserted to match the DC levels. The first 404stage ILFD lowers the fundamental frequency of TPCOs and 405SECO to 94 GHz with robust mutual injection locking using 406



Fig. 24. Output power measurement. (a) Third harmonic radiation power. (b) FTIR system. (c) Complete spectrum profile showing low leakage of thefundamental and unwanted harmonics.

the dual-port injection locking mechanism. The second stage407ILFD with bandwidth enhanced by DiCAD further lowers the408frequency down to 47 GHz. The frequencies of TPCOs, SECO,409and the first stage ILFD are simultaneously tuned by applying410the common VCTL on the bulk contacts of their core devices, so411that the operation frequency band of the first-stage ILFD can412follow the tuned frequency of the TPCOs and SECO. Also, the413inductor switch techniques are applied to both the oscillators414and dividers to double the overall tuning range of the front415end. The rest of the divided-by-16 chain lowers the frequency416down to 2.9 GHz.417

Additionally, to avoid using expensive THz probe, an on-418chip antenna, based on the single-ended planar ring slot419antennas in [24]–[27], is also integrated to effectively radiate420the THz signal from silicon die to free space. To enhance421the antenna gain in the EM model, the antenna is attached422on a silicon hyperhemispherical lens with a 4 mm diameter423and 0.55 mm extension as shown in Fig. 17(a). A larger424lens will further improve the gain, but simulation becomes425very time-consuming due to the limited computation resource.426The E- and H -plane radiation patterns in Fig. 17(b) suggest427a 20 dBi gain with good impedance matching to 50 � at the428feeding port indicated by Fig. 17(c).429

D. Low Noise Back-End Design 430The synthesizer back end, shown in the overall system block 431

diagram (Fig. 18), consists of an auxiliary frequency locked 432loop (FLL) and a PLL. The FLL contains a multimodulus 433divider (MMD), a phase-frequency detector with a dead zone, 434and a charge pump (CP) to lock the frequency before enabling 435PLL to precisely lock the phase. To eliminate noise from 436the CP and MMD, the PLL is based on a subsampled phase 437detector (SSPD) [23], [29] shown in Fig. 19(a). The output 438of the divide-by-16 stage (2.9 GHz) is directly subsampled 439by the 108 MHz crystal reference signal using a track-and- 440hold circuit, followed by a Gm cell that converts the phase 441error into the current that charges an off-chip loop filter and 442supplies TPCOs’ control voltage VCTL. Fig. 19(b) shows the 443timing diagram of the sampling clocks. The SSPD tracks the 444high-frequency signal during one half of the reference period, 445and then holds the sampled value in the other half period. 446An extra clock signal VSW controls the duty cycle which Gm 447cell charges the loop filter. 448

Additionally, a three-wire digital serial parallel 449interface (SPI) is used to control the 8 b tuning knob 450DACs throughout the synthesizer shown in Fig. 18. These 451DACs set the bias nodes including TPCOs and SECO’s 452



TABLE I

PERFORMANCE COMPARISONS WITH STATE-OF-THE-ART WORKS

VGG and inductor switches VSW1, the first stage ILFD’s tail453current, and tank inductor switch VSW2.454

IV. CIRCUIT IMPLEMENTATION AND CHARACTERIZATION455

The circuit was fabricated in TSMC standard 65 nm CMOS456technology with die size of 1.55 × 1.80 mm2 as shown in457Fig. 20. To radiate THz signals more effectively, the die458is assembled with a silicon hyperhemispherical lens with a45915 mm diameter and 2.6 mm extension on the backside of460the substrate. The spectrum measurement setup is shown in461Fig. 21(a). The radiated THz signal spectrum is measured462using a spectrum analyzer that receives a downconverted463THz signal at IF frequencies from a THz subharmonic mixer464with a WR1.5 horn. To verify the locking range, the chip465was locked to a 100–110 MHz reference signal provided466by Agilent signal generator. To test the phase noise of the467THz signal, the signal generator was replaced by a high-468quality 108 MHz crystal. The radiated power was tested with469a calibrated pyroelectric THz radiometer with a 1 cm distance470to the PLL shown in Fig. 21(b). At such a close distance,471the atmospheric absorption due to humidity can be ignored472according to [28]. The near-field coupling efficiency is not473an issue in this measurement as the collecting aperture of474the radiometer is much larger than the silicon lens. To block475the infrared radiation from the heated die into the radiometer,476we inserted an infrared blocking membrane in between with47795% transparence at 0.2 THz, 67% at 0.5 THz, and478−56 dB/dec rolloff beyond 0.9 THz.479

As shown in Fig. 22, the locked output frequencies span480from 538.67 to 559.89 GHz with tunable reference signals481from 103.9 to 108 MHz, covering six continuous channels482with different settings on DiCAD and inductor switches.483When stabilized by the 108 MHz crystal, a clear tone at484559.89 GHz was captured in Fig. 23(a) and (b) under 10 MHz485and 10 kHz frequency span, respectively. The phase noise at486559.89 GHz was characterized in Fig. 23(c) as −71, −74,487

and −85 dBc/Hz at 100 kHz, 1 MHz, and 10 MHz offset, 488respectively. Fig. 23(c) also compares the measured phase 489noise between this paper and our previous 30 GHz PLL 490work [29] (red dashed curve), both sharing the same PLL back- 491end design and frequency divider chain from 47 to 2.9 GHz. 492Considering the 20log(N) phase noise penalty due to N(=18) 493times frequency multiplication, the 20–30 dB difference in the 494in-band phase noise between the two works suggests that our 495THz front end (TPCOs, SECO, the first and second ILFDs) 496contributes negligible noise to the overall phase noise of the 497THz synthesizer, which is predicted by the simulation results 498shown in Fig. 23(d) with phase noise contribution from major 499blocks, where we can see that the total simulated phase noise 500is dominated by the back end instead of the VCO. The error 501between the simulated and the measured phase noise is about 5025 dB between 10 kHz and 1 MHz offset. Limited visibility 503of the measured phase noise skirt is a result of the high free 504space, mixer, and antenna losses, providing a signal less than 50530 dB above the spectrum analyzer’s noise floor. To further 506improve the phase noise in the future work, on the one hand, 507the back-end phase noise contributed from SSPD and Gm need 508to be reduced; on the other hand, a higher frequency reference 509source can be used to decrease the current frequency multipli- 510cation number (N = 5184) from reference frequency to THz. 511

The measured radiated power varies from −30 to −27 dBm 512over the 21.22 GHz locking band shown in Fig. 24(a). 513The measured power level agrees with that of our previous 514THz source array [7], which radiates −12.1 dBm by eight 515differential TPO pairs, i.e., −24.1 μW from each TPCO 516under 1 V supply. The slightly worse power level in this 517paper is due to the use of inductor switches for boosting the 518operation bandwidth. Considering the 60% simulated antenna 519efficiency, the signal power generated from the PLL core is 520estimated between −27 and −24 dBm. The major concern 521from the results is the limited signal power, which can hardly 522pump most of the existing THz mixers for frequency up- and 523downconversion. However, continuing advances in InP HEMT 524



amplifiers, such as [30], may be an avenue to further increase525the LO power in future THz systems. Another common526concern of the output power from harmonic oscillators is527the leakages of the fundamental and unwanted harmonics.528We have verified the spectrum profile using a Fourier transform529infrared spectroscopy (FTIR) system described in Fig. 24(b)530and obtained the radiation spectrum profile from the funda-531mental up to the ninth harmonic in Fig. 24(c), suggesting532that the fundamental, second and sixth harmonics leakages533are about −20, −15, and −10 dB, respectively.534

The synthesizer prototype consumes 172 mW in total under535separate 1 and 2.5 V power supplies (1 mA/2.5 V for the SPI536and the DAC to set VSW2).537

V. CONCLUSION538

This paper presents a 0.56 THz frequency synthesizer539realized in standard 65 nm CMOS technology. Several key540techniques enable a 21 GHz locking range, including band-541selection inductor switches, simultaneous bulk voltage tuning542over oscillators and divider, mutual injection locking mech-543anism, and dual port injection divider. The phase noise is544characterized as −71 and −74 dBc/Hz at 100 kHz and 1 MHz545frequency offsets, respectively. The overall performance is546compared with the prior works in Table I.547

This paper is aimed at planetary and Earth science applica-548tions, as plenty of spectral absorption lines for scientifically549interested chemical species exist in the operational band.550Compared with MMIC synthesizers used in existing NASA551THz instruments (limited below 100 GHz), our new CMOS552frequency synthesizer can considerably reduce weight, vol-553ume, and power as no III/V multiplication stages are needed.554

ACKNOWLEDGMENT555

The authors would like to thank TSMC for their excellent IC556manufacture and Alcatera LLC for the technical consultation.557

REFERENCES558

[1] M. Seo, M. Urteaga, M. Rodwell, and M.-J. Choe, “A 300 GHz PLL in559an InP HBT technology,” in IEEE MTT-S Int. Microw. Symp. Dig. (MTT),560Baltimore, MD, USA, Jun. 2011, pp. 1–4.561

[2] P. Y. Chiang, Z. Wang, O. Momeni, and P. Heydari, “A silicon-562based 0.3 THz frequency synthesizer with wide locking range,” IEEE563J. Solid-State Circuits, vol. 49, no. 12, pp. 2951–2963, Dec. 2014.564

[3] R. Han et al., “A SiGe terahertz heterodyne imaging transmitter with5653.3 mW radiated power and fully-integrated phase-locked loop,” IEEE566J. Solid-State Circuits, vol. 50, no. 12, pp. 2935–2947, Dec. 2015.567

[4] D. Shim, D. Koukis, D. J. Arenas, D. B. Tanner, and K. K. O, “553-GHz568signal generation in CMOS using a quadruple-push oscillator,” in Proc.569IEEE Symp. VLSI Circuits, Jun. 2011, pp. 154–155.570

[5] W. Steyaert and P. Reynaert, “A 0.54 THz signal generator in 40 nm571bulk CMOS with 22 GHz tuning range and integrated planar antenna,”572IEEE J. Solid-State Circuits, vol. 49, no. 7, pp. 1617–1626, Jul. 2014.573

[6] U. R. Pfeiffer et al., “A 0.53 THz reconfigurable source module574with up to 1 mW radiated power for diffuse illumination in terahertz575imaging applications,” IEEE J. Solid-State Circuits, vol. 49, no. 12,576pp. 2938–2950, Dec. 2014.577

[7] Y. Zhao et al., “A 0.54-0.55 THz 2×4 coherent source array with EIRP578of 24.4 dBm in 65 nm CMOS technology,” in IEEE MTT-S Int. Microw.579Symp. (MTT) Dig., Phoenix, AZ, USA, May 2015, pp. 1–3.580

[8] I.-T. Lee, C.-H. Wang, B.-Y. Lin, and S.-I. Liu, “258.16–259.95 GHz581injection-locked frequency divider,” Electron. Lett., vol. 46, no. 21,582pp. 1438–1439, Oct. 2010.583

[9] T. Chi, J. Luo, S. Hu, and H. Wang, “A multi-phase sub-harmonic 584injection locking technique for bandwidth extension in silicon-based 585THz signal generation,” IEEE J. Solid-State Circuits, vol. 50, no. 8, 586pp. 1861–1873, Aug. 2015. 587

[10] E. Öjefors, J. Grzyb, Y. Zhao, B. Heinemann, B. Tillack, and 588U. R. Pfeiffer, “A 820 GHz SiGe chipset for terahertz active imaging 589applications,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. 590Papers, Feb. 2011, pp. 224–225. 591

[11] Y. Zhao et al., “An integrated 0.56 THz frequency synthesizer with 59221 GHz locking range and −74dBc/Hz phase noise at 1 MHz offset in 59365 nm CMOS,” in Proc. IEEE Int. Solid-State Circuits Conf. (ISSCC), 594Jan./Feb. 2016, pp. 36–37. 595

[12] O. Momeni and E. Afshari, “High power terahertz and millimeter-wave 596oscillator design: A systematic approach,” IEEE J. Solid-State Circuits, 597vol. 46, no. 3, pp. 583–597, Mar. 2011. 598

[13] Y. Zhao, J. Grzyb, and U. R. Pfeiffer, “A 288-GHz lens-integrated 599balanced triple-push source in a 65-nm CMOS technology,” in 600Proc. Eur. Solid-State Circuits Conf., Bordeaux, France, Sep. 2012, 601pp. 289–292. 602

[14] J. Grzyb, Y. Zhao, and U. R. Pfeiffer, “A 288-GHz lens-integrated 603balanced triple-push source in a 65-nm CMOS technology,” IEEE 604J. Solid-State Circuits, vol. 48, no. 7, pp. 1751–1761, Jul. 2013. 605

[15] Y.-L. Tang and H. Wang, “Triple-push oscillator approach: Theory 606and experiments,” IEEE J. Solid-State Circuits, vol. 36, no. 10, 607pp. 1472–1479, Oct. 2001. 608

[16] B. Catli and M. M. Hella, “Triple-push operation for combined oscil- 609lation/divison functionality in millimeter-wave frequency synthesizers,” 610IEEE J. Solid-State Circuits, vol. 45, no. 8, pp. 1575–1589, Aug. 2010. 611

[17] M. Seo et al., “A 1.1V 150 GHz amplifier with 8dB gain and 612+6dBm saturated output power in standard digital 65 nm CMOS using 613dummy-prefilled microstrip lines,” in IEEE Int. Solid-State Circuits 614Conf. (ISSCC) Dig. Tech. Papers, Feb. 2009, pp. 484–485. 615

[18] Z. Xu, Q. J. Gu, and M.-C. F. Chang, “200 GHz CMOS amplifier 616working close to device fT,” Electron. Lett., vol. 47, no. 11, pp. 639–641, 617May 2011. 618

[19] O. Momeni, “A 260GHz amplifier with 9.2dB gain and −3.9dBm 619saturated power in 65nm CMOS,” in IEEE Int. Solid-State Circuits 620Conf. (ISSCC) Dig. Tech. Papers, Feb. 2013, pp. 140–141. 621

[20] F. Tzeng, D. Pi, A. Safarian, and P. Heydari, “Theoretical analysis of 622novel multi-order LC oscillators,” IEEE Trans. Circuits Syst. II, Express 623Briefs, vol. 54, no. 3, pp. 287–291, Mar. 2007. 624

[21] J. Zhang, N. Sharma, and K. K. O, “21.5-to-33.4 GHz voltage- 625controlled oscillator using NMOS switched inductors in CMOS,” 626IEEE Microw. Wireless Compon. Lett., vol. 24, no. 7, pp. 478–480, 627Jul. 2014. 628

[22] T. LaRocca, J. Liu, F. Wang, and F. Chang, “Embedded DiCAD 629linear phase shifter for 57–65 GHz reconfigurable direct frequency 630modulation in 90 nm CMOS,” in Proc. IEEE Symp. Radio Freq. Integr. 631Circuits (RFIC), Jun. 2009, pp. 219–222. 632

[23] X. Gao, E. A. M. Klumperink, M. Bohsali, and B. Nauta, “A low noise 633sub-sampling PLL in which divider noise is eliminated and PD/CP noise 634is not multiplied by N2,” IEEE J. Solid-State Circuits, vol. 44, no. 12, 635pp. 3253–3263, Dec. 2009. 636

[24] H.-J. Song et al., “8 Gbit/s wireless data transmission at 250 GHz,” 637Electron. Lett., vol. 45, no. 22, pp. 1121–1122, Oct. 2009. 638

[25] H.-J. Song et al., “Terahertz wireless communication link at 300 GHz,” 639in Proc. IEEE Topical Meeting Microw. Photon. (MWP), Oct. 2010, 640pp. 42–45. 641

[26] M. Uzunkol, O. D. Gurbuz, F. Golcuk, and G. M. Rebeiz, “A 0.32 642THz SiGe 4 × 4 imaging array using high-efficiency on-chip anten- 643nas,” IEEE J. Solid-State Circuits, vol. 48, no. 9, pp. 2056–2066, 644Sep. 2013. 645

[27] K. Statnikov, E. Öjefors, J. Grzyb, P. Chevalier, and U. R. Pfeiffer, 646“A 0.32 THz FMCW radar system based on low-cost lens-integrated 647SiGe HBT front-ends,” in Proc. ESSCIRC, 2013, pp. 81–84. 648

[28] A. Danylov, “THz laboratory measurements of atmospheric absorption 649between 6% and 52% relative humidity,” Univ. Massachusetts, Lowell 650Submillimeter-Wave Technol. Lab., Lowell, MA, USA, Tech. Rep. 175, 6512006. 652

[29] Z.-Z. Chen et al., “A wide-band 65 nm CMOS 28-34 GHz synthesizer 653module enabling low power heterodyne spectrometers for planetary 654exploration,” in IEEE MTT-S Int. Microw. Symp. (IMS) Dig., Phoenix, 655AZ, USA, May 2015, pp. 1–3. 656

[30] V. Radisic et al., “InP HBT transferred substrate amplifiers operating to 657600 GHz,” in IEEE MTT-S Int. Microw. Symp. Dig., Phoenix, AZ, USA, 658May 2015, pp. 1–3. 659



Yan Zhao (M’09–SM’16) received the M.S. degree660in microwave technology from Northwestern Poly-661technic University, Xi’an, China, in 2002, and the662Ph.D. degree in circuits and systems from Southeast663University, Nanjing, China, in 2009.664

From 2002 to 2005, he was with the ZTE Cor-665poration, Xi’an, China, where he was a Radio666Frequency Engineer on mm-wave transceiver sys-667tem and WCDMA RF system design. From6682009 to 2013, he was with the University of669Wuppertal, Wuppertal, Germany. Since 2013, he has670

been a Senior Development Engineer with the University of California at671Los Angeles, Los Angeles, CA, USA, where he was the first to realize syn-672chronized oscillator array and frequency synthesizer circuits beyond 0.5 THz673in silicon technology. He has over ten years’ experience in mm-wave and674terahertz IC design for communication and imaging applications.675

Dr. Zhao was a co-recipient of the 2012 Jan Van Vessem Award for the676Outstanding European Paper at the IEEE International Solid-State Circuit677Conference and the 2014 Best Antenna Application Paper Award at the6788th European Conference on Antennas and Propagation.679

Zuow-Zun Chen was born in Taipei, Taiwan.680He received the B.S. degree in computer science681and information engineering and the M.S. degree682in electronics engineering from National Taiwan683University, Taipei, in 2005 and 2008, respectively.684He is currently pursuing the Ph.D. degree in electri-685cal engineering with the University of California at686Los Angeles (UCLA), Los Angeles, CA, USA.687

In 2013, he was a Mixed-Signal Intern at Broad-688com Corporation, Irvine, CA, USA. His cur-689rent research interests include mixed-mode and690

RF circuit design.691Mr. Chen was a recipient of the UCLA–Mediatek Fellowship from692

2014 to 2015.693

Yuan Du (S’14) received the B.S. degree (Hons.)694in electrical engineering from Southeast Univer-695sity, Nanjing, China, in 2009, and the M.S. degree696in electrical engineering from the University of697California at Los Angeles, Los Angeles, CA,698USA, in 2012, where he is currently pursuing the699Ph.D. degree.700

His current research interests include the designs701of CMOS RFICs and mixed-signal ICs.702

Mr. Du was a recipient of the Microsoft Research703Asia Young Fellowship in 2008, Southeast Univer-704

sity Chancellor’s Award in 2009, and the Broadcom Fellowship in 2015.705

Yilei Li (S’14) received the B.S. and M.S. degrees in706microelectronics from Fudan University, Shanghai,707China, in 2009 and 2012, respectively. He is cur-708rently pursuing the Ph.D. degree with the University709of California at Los Angeles, Los Angeles, CA,710USA.711

His current research interests include circuit and712system design for emerging applications, including713software-defined radio, multiband RF interconnect,714and terahertz imaging systems.715

Mr. Li was a recipient of the Henry Samueli716Fellowship in 2012 and the Broadcom Fellowship in 2015.717

Richard Al Hadi (S’10–M’14–SM’16) received 718the Engineering Diploma in electronics and applied 719physics from the National Graduate School of Engi- 720neering, Caen, France, the Master’s degree from the 721University of Caen Basse–Normandie, Caen, France, 722in 2009, and the Ph.D. degree (summa cum laude) 723from the University of Wuppertal, Wuppertal, Ger- 724many, in 2014. 725

In 2011, he was a Research Fellow at Korea Uni- 726versity, Seoul, South Korea. He joined the University 727of California at Los Angeles, Los Angeles, CA, 728

USA, in 2015, as a Post-Doctoral Research Fellow. His current research 729interests include terahertz integrated circuits in silicon technologies. 730

Dr. Al Hadi was a co-recipient of the 2012 Jan Van Vessem Award for 731the Outstanding European Paper at the IEEE International Solid-State Circuit 732Conference and the 2014 EuCAP Best Paper Award. 733

Gabriel Virbila received the B.S. and M.S. degrees 734from the University of California at Los Ange- 735les, Los Angeles, CA, USA, in 2011 and 2013, 736respectively. 737

He is currently a Research Staff Member at HRL 738Laboratories, LLC, Malibu, CA, USA. 739

Yinuo Xu received the B.S. degree in electrical 740engineering from the University of California at 741Los Angeles (UCLA), Los Angeles, CA, USA, in 7422016. 743

She is currently a Research Assistant with the 744Center of High Frequency Electronic, UCLA. Her 745current research interests include terahertz and 746mm-wave CMOS circuits as well as their potential 747applications. 748

Yanghyo Kim (S’10) is currently pursuing the 749Ph.D. degree with the University of California at 750Los Angeles, Los Angeles, CA, USA. 751

His current research interests include the mm-wave 752integrated system design and its applications. 753

Adrian Tang (SM’16) has over 15 years of 754CMOS/SiGe IC design experience in both research 755and commercial wireless environments with projects 756ranging from commercial Bluetooth and WLAN 757chipsets to mm-wave and terahertz chipsets for 758communication, radar, and spectrometer systems. 759Since 2013, he has been a Strategic-Researcher 760with Jet Propulsion Laboratory (JPL), Pasadena, CA, 761USA, where he was the first to demonstrate the 762subcentimeter accurate mm-wave imaging radar in 763silicon technology with demonstrations at 144 and 764

155 GHz, the first to demonstrate predistortion in mm-wave sources above 765150 GHz, and the first to demonstrate CMOS-based passive radiometers with 766enough sensitivity to support passive imaging. At JPL, he currently directs 767the space-system-on-chip laboratory and leads the development of a wide 768range of CMOS SoC chipsets for planetary, Earth science, and Astrophysics 769space instruments. His current research interests include the development of 770wideband spectrometer processors to support the spectroscopic exploration 771of the outer planet moons, terahertz radiometers system for exploring the 772Earth’s atmosphere, and fractional frequency synthesizers for a wide range of 773astrophysics and planetary science investigations. 774



Theodore J. Reck (M’04–SM’15) received the775B.S. degree in electrical engineering from the Uni-776versity of Texas at Austin, Austin, TX, USA,777in 2000, and the Ph.D. degree in electrical engineer-778ing from the University of Virginia, Charlottesville,779VA, USA, in 2010.780

From 2010 to 2013, he was a NASA Post-Doctoral781Fellow at the Jet Propulsion Laboratory (JPL),782Pasadena, CA, USA, designing terahertz devices that783utilize silicon micromachining. Currently, he is a784member of the Technical Staff at JPL. His current785

research interests include RF-MEMS, antenna arrays, terahertz metrology, and786cryogenic MMICs.787

Mau-Chung Frank Chang (M’79–SM’94–F’96) 788is currently the President of National Chiao 789Tung University, Hsinchu, Taiwan. He is also the 790Wintek Chair Professor of Electrical Engineering 791with the University of California at Los Angeles, 792Los Angeles, CA, USA. His current research inter- 793ests include the development of high-speed semicon- 794ductor devices and high-frequency integrated circuits 795for radio, radar, and imaging system-on-chip appli- 796cations up to the terahertz frequency regime. 797

Dr. Chang is a member of the U.S. National 798Academy of Engineering, a fellow of the U.S. National Academy of Inventors, 799and an Academician of the Academia Sinica of Taiwan. He was a recipient of 800the IEEE David Sarnoff Award in 2006 for developing and commercializing 801GaAs HBT and BiFET power amplifiers for modern high efficiency and high 802linearity smart-phones in the past 2.5 decades. 803

本文献由“学霸图书馆-文献云下载”收集自网络，仅供学习交流使用。

学霸图书馆（www.xuebalib.com）是一个“整合众多图书馆数据库资源，

提供一站式文献检索和下载服务”的24 小时在线不限IP

图书馆。

图书馆致力于便利、促进学习与科研，提供最强文献下载服务。

图书馆导航：

图书馆首页文献云下载图书馆入口外文数据库大全疑难文献辅助工具

http://www.xuebalib.com/cloud/http://www.xuebalib.com/http://www.xuebalib.com/cloud/http://www.xuebalib.com/http://www.xuebalib.com/vip.htmlhttp://www.xuebalib.com/db.phphttp://www.xuebalib.com/zixun/2014-08-15/44.htmlhttp://www.xuebalib.com/

A 0.56 THz Phase-Locked Frequency Synthesizer in 65 nm CMOS Technology学霸图书馆link:学霸图书馆

Documents

A 0.56 THz Phase-Locked Frequency Synthesizer in 65 nm ...download.xuebalib.com/w0blb8iGv7A.pdf14 architecture for the ﬁrst ILFD. The resultant prototype realizes 15 a 21 GHz frequency