James Lin, Ibuki Mano, Masaya Miyahara

and Akira Matsuzawa

Tokyo Institute of Technology, Japan

A 0.5 V, 420 MSps, 7-bit Flash ADC Using All-Digital Time-Domain

Delay Interpolation

Matsuzawa

& Okada LabMatsuzawa Lab.Tokyo Institute of Technology

2

Outline

• Motivation

• Background

• Circuit Design

• Experimental Results

• Conclusion

3

Motivation

• Ultra-low-voltage operation

– Immediate power saving potential

– Explore new circuit techniques for future technology

[1] ITRS, 2011.

2010 2015 2020 20250.5

0.6

0.7

0.8

0.9

1.0

Su

pp

ly v

olt

ag

e (

V)

Year

Background

• Flash ADC’s advantages

– Shortest latency

Attractive for systems with feedback loops:

clock data recovery (CDR), decision feedback

equalizer (DFE)

• Disadvantages

– With increasing resolution

Exponential increase

4

Power consumption

Area

Input capacitance

Time-Domain Delay Interpolation

5

• Time-domain interpolation can enhance the

resolution of a flash ADC without the severe

trade-offs [2]

TDelay

VREF1

VREF2

Interpolation Point

0

1

CMPN+1’s Delay

CMPN’s Delay

Inp

ut

Sig

na

l (V

IN)

VIN

VREF2

VIN

VREF1

SR Latch for Delay

Interpolation

OUTNN+1

OUTPN+1

OUTNN

OUTPN

OUTNInt

OUTPInt

VIN

VIN

VREF1

VREF2

[2] Y. S. Shu, VLSI Circuits 2012.

Offset voltage vs. ENOB

6

• To limit the ENOB degradation to less than 0.5

bit < 1 mV(s) offset voltage is required

0 1 2 3 4 5 6 7

4.0

4.5

5.0

5.5

6.0

6.5

7.0

EN

OB

(b

it)

Offset voltage (mV(s))

Mismatch Calibration at ULV

7

• Conventional varactor [3] calibration degrades

with supply voltage lowering

• The mismatch of the comparator can be

problematic at the ultra-low supply voltage

Calibration Methods None Current Varactor Time MOM

Offset [mV(s)] 10.1 1.32 5.79 1.77 0.85

Power @ 500 MHz [mW] 14.5 41.3 21.4 24.5 17

Delay [ps] 365 450 756 556 625

[3] V. Giannini, et al., ISSCC 2008.

MOM Calibration

8

• Using MOM capacitors and switches, the

offset voltage can be suppressed to less than

1 mV(s)

MOM

Capacitors

VOUTP / VOUTN

Ca

l_c

od

e<

1>

2C

Ca

l_c

od

e<

2>

4C

Ca

l_c

od

e<

3>

8C1CC

al_

co

de

<0

>

Ca

l_c

od

e<

4>

16CCLK

VINP VINN

VOUTN VOUTP

VDD VDD

Dynamic

Preamplifier

6-bit ADC Core

9

• 6-bit ADC core with delay interpolation using a

modified 5-bit core from [4]

[4] M. Miyahara, A-SSCC 2010.

S/H

6-bit ADC CoreE

rror C

orre

ctio

n C

ircu

it

Th

erm

om

ete

r to B

ina

ry E

nc

od

er

VINP

VINN

DOUT

63 63 6

Re

fere

nc

e L

ad

de

r

S/H

S/H

S/H

CMPX4

CMPX4

CMPX4

Latch

Latch

Latch

U/D CNTX4

U/D CNTX4

U/D CNTX4

Comparator Block

(32 Comparators and

31 Interpolation Latches)2b Interpolation

S/H

ADC Structure

10

• 7-bit ADC block diagram consists of 4×6-bit

cores

7-b

it DF

F

7-bit

MUX6b

ADC3

6b

ADC47b

ADCB

6-b

it Ad

dd

er

6b

ADC1

6b

ADC27b

ADCA

6-b

it Ad

de

r

VIN DOUT

6

6

7

7 7

76

6

Clock DividerCLK

U/D Counters X 32

Comparator X 32

S/H X 9

Bootstrap X 9

Encoder and

Error Correction

Interpolation

Latch X 31

7-bit ADC Core6-bit ADC

CORE

32

5 m

m

1200 mm

6-bit ADC

CORE

Measured DNL and INL

11

0 20 40 60 80 100 120-4

-2

0

2

4

DN

L (

LS

B)

Without Calibration

With Calibration

Digital Code

0 20 40 60 80 100 120-6

-4

-2

0

2

4

6

INL

(L

SB

)

Without Calibration

With Calibration

Digital Code

DNL

±1.6 LSB ±0.95 LSB

INL

±1.4 LSB ±0.68 LSB

(Operating at 100 MSps with a 0.5 V supply)

Measured SFDR and SNDR

12

• SFDR and SNDR vs. sampling frequency

• SNDR vs. input frequency

(b)(a)

0 50 100 150 20025

30

35

40

SN

DR

(d

B)

Input Frequency (MHz)

ADCA

ADCB

Interleaved ADC

0 200 400 600 800

20

30

40

50

SN

DR

& S

FD

R (

dB

)

Sampling Frequency (MHz)

SFDR

SNDR

Performance Comparison

[5] [6] [7] This Work

Architecture Subrange Subrange Pipeline Flash

Resolution [bit] 7 7 10 7

fs [MSps] 2200 (4 ch) 300 (1 ch) 10 (1 ch) 420 (2 ch) 210 (1 ch)

Process [nm] 65 65 90 90

Supply [V] 1 1.2 0.5 0.5 (VBS = 0.5)

SNDR [dB] 36.1 40.5 48.1 35 36

Power [mW] 40 2.3 2.4 4.1 2.1

FoM [fJ/c.-s.] 280 88 940 906 195

13

[5] I. N. Ku, et al., CICC 2011.

[6] U. F. Chio, et al., ESSCIRC 2011.

[7] J. Shen, et al., JSSC 2008.

Conclusion

14

• All-digital time-domain delay interpolation

enhances the resolution of a flash ADC

without the undesirable trade-offs

• MOM calibration is effective for ultra-low-

voltage circuits

• Ultra-low-voltage proves to be a promising

method to reduce power consumption

15

Thank you

for your interest!

James Lin,

james@ssc.pe.titech.ac.jp