A 0.4-To-3 GHz Digital PLL With PVT Insensitive Supply Noise Cancellation Using Deter Minis Tic Background Calibration

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 46, NO. 12, DECEMBER 2011 2759

A 0.4-to-3 GHz Digital PLL With PVT InsensitiveSupply Noise Cancellation Using Deterministic

Background CalibrationAmr Elshazly, Student Member, IEEE, Rajesh Inti, Student Member, IEEE, Wenjing Yin, Student Member, IEEE,

Brian Young, Student Member, IEEE, and Pavan Kumar Hanumolu, Member, IEEE

Abstract—A digital phase-locked loop (DPLL) employs noisecancellation to mitigate performance degradation due to noise onthe ring oscillator supply voltage. A deterministic test signal-baseddigital background calibration is used to accurately set thecancellation gain and thus achieve accurate cancellation underdifferent process, voltage, temperature, and operating frequencyconditions. A hybrid, linear proportional control and bang–bangdigital integral control, is used to obviate the need for a high-reso-lution time-to-digital converter and reduce jitter due to frequencyquantization error. Fabricated in 0.13 m CMOS technology, theDPLL operates from a 1.0 V supply and achieves an operatingrange of 0.4-to-3 GHz. At 1.5 GHz, the DPLL consumes 2.65 mWpower wherein the cancellation circuitry consumes about 280 W.The proposed noise cancellation scheme reduces the DPLL’speak-to-peak jitter from 330 to 50 ps in the presence of a 30 mV��

10 MHz supply noise tone, and the DPLL peak-to-peak jitter is50 ps in the absence of any supply noise. The DPLL occupies anactive die area of 0.08 mm�, of which the calibration logic andcancellation circuitry occupy only 12.5%.

Index Terms—Area efficient, background calibration, calibra-tion, delta-sigma DAC, deterministic test signal, digital PLL, digi-tally controlled oscillators (DCOs), hybrid loop filter, noise cancel-lation, phase-locked loops (PLLs), power supply noise, PVT insen-sitive, ring oscillator, self-calibrated.

I. INTRODUCTION

D IGITAL PHASE-LOCKED LOOPs (DPLLs) haverecently emerged as a viable alternative to classical

charge-pump analog PLLs [1]–[7]. A conventional DPLL blockdiagram is shown in Fig. 1. It consists of a time-to-digitalconverter (TDC), digital loop filter (DLF), digitally controlledoscillator (DCO), and feedback divider. The TDC generatesa digital word proportional to the phase error between thereference clock (REF), and the feedback divider output. TheDLF is a proportional-integral filter realizing the Type-II PLLresponse. A digital-to-analog converter (DAC) interfaces theDLF to the voltage controlled oscillator (VCO).

Manuscript received April 16, 2011; revised June 16, 2011; accepted July 15,2011. Date of publication August 22, 2011; date of current version November23, 2011. This paper was approved by Guest Editor Jafar Savoj. This work wassupported in part by the Center for Design of Analog-Digital Integrated Cir-cuit (CDADIC) and the National Science Foundation under CAREER EECS-0954969.

The authors are with the School of Electrical Engineering and Computer Sci-ence, Oregon State University, Corvallis, OR 97331 USA (e-mail: [email protected]).

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/JSSC.2011.2162912

Fig. 1. Block diagram of a conventional DPLL.

By obviating the need for a large loop filter capacitor andhigh performance charge-pump, DPLLs offer area savings; widerange of operating conditions; immunity to process, voltage, andtemperature (PVT) variations; and easier scalability to newerprocesses. The ability to reconfigure the digital loop filter dy-namically offers flexibility in setting the loop response and helpsto optimize the locking behavior of the DPLL [6]. While thesefeatures are attractive, DPLLs suffer from unique bandwidth,operating range, and noise tradeoffs.

Conflicting bandwidth requirements to simultaneously sup-press TDC quantization error and oscillator phase noise man-date low DPLL bandwidth and a low phase noise oscillator tominimize jitter [7]. In view of this, an LC-based DCO with ex-cellent phase noise is combined with a very low DPLL band-width to suppress the TDC quantization error [1]. The DCO fre-quency quantization error imposes a DPLL operating range-res-olution tradeoff. For a given hardware complexity, DCO reso-lution can be improved only by limiting its tuning range. A rea-sonably wide tuning range is achieved using a ring-DCO at theexpense of larger output clock jitter [2], [3], while a high-reso-lution DCO with narrow tuning range has been used to achievegood jitter performance [1]. Because of these difficulties, de-signing a low jitter wide tuning range digital PLL requires op-timization of conflicting design parameters. Further, much likeanalog PLLs, when integrated into a large digital system, thering oscillator is susceptible to supply noise, which especiallylimits the jitter performance of a DPLL. The focus of our workis on mitigating supply noise in ring oscillator-based DPLLs.Further, the ring oscillator is the most sensitive block, we willfocus on system and circuit design techniques that desensitizethe DCO to supply noise.

Supply regulation techniques primarily focussing on sup-pressing the supply noise in the ring oscillator have beenemployed [8]–[11]. A general representation of a classicalsupply regulated charge-pump PLL is depicted in Fig. 2.It consists of a three-state phase-frequency detector (PFD),charge-pump, low-pass loop filter, VCO, and feedback divider.

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2760 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 46, NO. 12, DECEMBER 2011

Fig. 2. Conventional supply regulated PLL.

The VCO control voltage is applied to its supply througha low-dropout regulator, depicted as a buffer in Fig. 2. Thelow-dropout regulator shields the VCO from supply noiseand prevents it from reaching the internal VCO supply at theexpense of additional area and power, and reduced voltageheadroom [12]. In practice, the regulator fails to completelyisolate supply noise from the output due to various circuitnon-idealities such as the finite transistor output impedanceand insufficient regulator bandwidth. While commonly used,the supply regulation approach has several drawbacks. First,the power supply noise rejection of the regulated-PLL greatlydepends on the regulator to PLL bandwidth ratio (BWR). Forreasonable suppression, the regulator bandwidth must be mademuch larger than the PLL bandwidth. For instance, for a modest8 dB of worst-case power supply noise rejection (PSNR), theregulator bandwidth must be 50 times the PLL bandwidth [8].Designing the regulator for such a wide bandwidth increasespower dissipation. On the other hand, because VCO phasenoise is high-pass filtered by the feedback loop, increasingBWR by reducing the PLL bandwidth exacerbates jitter dueto oscillator phase noise. Second, the dropout voltage of theregulator limits the maximum control voltage of the VCO andreduces its tuning range. A lower dropout voltage increasesthe operating range of the VCO but compromises its PSNR.Finally, a large decoupling capacitor is needed in the design ofall regulators [8], [9].

In view of these drawbacks, our work focuses on supply noisecancellation techniques to mitigate supply noise. In contrast tosupply regulation, supply noise cancellation techniques can op-erate at a lower supply voltage and have the potential to achieveexcellent supply noise immunity without using a large decou-pling capacitor. However, in a practical implementation, theeffectiveness of this approach is greatly reduced by process,voltage, and temperature variations [13], [14].

In this paper, we present a deterministic test signal-based con-tinuous background calibration scheme that leverages the highlydigital nature of the DPLL to adaptively cancel the supply noisein the DCO. The proposed DPLL seeks to achieve low jitter, lowpower, and wide tuning range over a wide range of operatingconditions and supply noise. The prototype DPLL fabricated in0.13 m CMOS process achieves accurate supply noise can-cellation over an output frequency range of 0.4 GHz-to-3 GHz.The cancellation circuitry reduces peak-to-peak jitter from 330to 50 ps in the presence of 30 mV supply noise. At 1.5 GHz,the DPLL consumes 2.65 mW from a 1.0 V supply.

The rest of this paper is organized as follows. The conceptof noise cancellation along with a brief review of conventionalsupply noise cancellation techniques are presented in Section II.The proposed DPLL architecture is described in Section III, and

Fig. 3. Illustration of noise cancellation concept.

Fig. 4. PLL architecture employing open loop supply noise cancellation witha fixed cancellation gain �� [13].

the circuit design details of important building blocks are pre-sented in Section IV. Section V shows the experimental resultsobtained from the prototype integrated circuit. A detailed dis-cussion of the design tradeoffs involved in regulation and can-cellation schemes is presented in Section VI. Finally, key con-tributions of this paper are summarized in Section VII.

II. SUPPLY NOISE CANCELLATION

The general concept of noise cancellation is pictorially de-picted in Fig. 3. It is based on the fact that a sensitive circuitcan be desensitized to noise by canceling the noise before it ap-pears at the output. Conceptually, this can be achieved by sub-tracting the appropriately scaled noise from the output of thesensitive circuit. While its simplicity is appealing, the effective-ness of this approach greatly depends on the accuracy of thecancellation gain . Ideally, must be equal to the intrinsicnoise sensitivity of the circuit . Under this condition, the esti-mated output noise, , completely cancels the output in-duced noise, . In practice, the sensitivity of to PVTvariations poses a challenge in setting appropriately. Whilethe concept of noise cancellation can be applied in many ap-plications, the focus of our work is in the context of cancellingsupply noise in a VCO. To this end, we present a digital back-ground calibration algorithm that determines optimal underall operating conditions and helps achieve robust cancellation ofsupply noise in the VCO.

Several attempts have been already made to cancel the effectof supply noise in the VCO [13], [14]. In [13], as shown inFig. 4, the additional current induced by supply noise is can-celled at the output of the voltage-to-current (V-to-I) converter.The noise cancellation gain, , that best matches the V-to-Isensitivity was determined from transistor-level simulations.Ideally, with complete cancellation, the current-controlledoscillator frequency becomes independent of supply noise.

ELSHAZLY et al.: A 0.4-TO-3 GHZ DIGITAL PLL WITH PVT INSENSITIVE SUPPLY NOISE CANCELLATION 2761

Fig. 5. Simulated VCO supply sensitivity for different process corners at 27 Ctemperature.

Fig. 6. Simulated VCO supply sensitivity at different temperatures.

However, in practice, process and temperature variations se-verely impact the VCO supply noise sensitivity,1 as shown inFigs. 5 and 6. This illustrates that the supply sensitivity varieswith process corners, DC level of supply voltage, and operatingtemperature. Thus, using a fixed cancellation gain as in [13] isgrossly suboptimal. Therefore, it is necessary to calibrate thecancellation gain.

An analog foreground calibration was proposed in [14] to de-termine the optimal cancellation gain. On power up, once thePLL is locked, a known step voltage is applied to the VCOsupply, as illustrated in Fig. 7(a). Using the loop’s response tothis known perturbation, the foreground calibration circuitry es-timates VCO supply noise sensitivity and determines the de-sired cancellation gain. Once the foreground calibration algo-rithm converges to the desired cancellation gain, , the PLLis switched back to operate in its normal mode of operation, asshown in Fig. 7(b), and the cancellation gain remains fixed at

. While this technique successfully mitigates process depen-dence, it is susceptible to variations in operating conditions, be-cause of its foreground nature. As illustrated by the simulated re-sults in Fig. 8 and validated by measured results in Section V, thesupply sensitivity greatly depends on the oscillation frequencyand the supply voltage DC value. This dependence makes anyforeground approach ineffective in a practical setting. Further-more, this technique relies on accurately probing the analog con-

1The supply noise sensitivity is defined as the percentage change in theVCO oscillating frequency to the percentage change in the supply voltage, i.e.,�� %�� %��.

Fig. 7. Analog foreground calibration scheme [14]. (a) Calibration mode.(b) Normal PLL mode.

Fig. 8. Simulated VCO supply sensitivity for operating frequencies from400 MHz to 3 GHz at different process corners.

trol voltage, and hence it is susceptible to analog circuit im-perfections. To overcome these drawbacks, we present a digitalbackground calibration scheme that seeks to determine the op-timal cancellation gain in the presence of process, voltage, tem-perature, and oscillation frequency variations.

III. PROPOSED DPLL ARCHITECTURE

The detailed block diagram of the proposed DPLL is shownin Fig. 9 [15]. It consists of separate proportional and digitalintegral paths, feedback divider, supply noise cancellationgain calibration logic, and supply noise insensitive DCO. Theproportional control is implemented using a three-state PFDthat directly drives the oscillator through a three-level cur-rent-mode DAC, thus eliminating TDC quantization error in theproportional path. A flip-flop (FF) acts as an early/late detectoron PFD outputs and drives the digital accumulator with thesign of the phase error. A low bandwidth digital integral pathsuppresses the phase quantization error of the FF. Separatingthe proportional and integral path helps in extending the DPLLoperating range without degrading either the quantizationerror induced deterministic jitter or the thermal noise induced


Fig. 9. Block diagram of the proposed DPLL using deterministic background calibration of the supply noise cancellation gain.

random jitter [16], [17]. A 1-to-4 demultiplexer is used to easethe speed requirements of the fully-synthesized digital controllogic. The digital delta-sigma modulator truncates the 14-bitaccumulator output, , to 15-levels and drives a current-modeDAC. A second-order passive low-pass filter suppresses theout-of-band quantization error and drives the integral controlvoltage input of the oscillator.

The DCO supply noise immunity is improved greatly, as dis-cussed earlier, by intentionally injecting at the oscillator outputan appropriate magnitude cancellation current, , in proportionto the supply noise. Because the optimal value of dependson PVT variations and oscillator frequency, a test signal-baseddigital background calibration scheme is employed to determinethe compensation gain accurately and achieve excellent broad-band supply noise immunity under all operating conditions. Byinjecting a test signal into the oscillator supply and correlating itwith the digital integral path output, the digital background cal-ibration engine estimates the cancellation gain and desen-sitizes the oscillator to supply noise. As with foreground cali-bration, the effectiveness of this background calibration methodgreatly depends on the accuracy with which can be esti-mated. Before examining the process of estimation, it is in-structive to evaluate the dynamics of the DPLL loop.

A. DPLL Loop Dynamics

The proposed DPLL was designed to have a heavily over-damped Type-II response, wherein the digital integral path has aminimal affect on the loop dynamics. The s-domain closed-looptransfer function of the DPLL is given by

(1)

where N is the feedback divide ratio, and denote thecumulative gain through the proportional and the integral path,respectively, and is the VCO gain from the supply node.The proportional and integral path gains are

(2)

(3)

Comparing (1) to the standard second order transfer functionrepresented in control theory notation leads to

(4)

where the damping factor can be calculated to be

(5)

In the proposed DPLL, was chosen to be much smallerthan in order to minimize dithering jitter caused bybang–bang phase detector nonlinearity and DCO quantizationerror. As a consequence, the DPLL exhibits an overdampedresponse, wherein its two poles, zero, and 3 dB bandwidth are

(6)

(7)

(8)

Because remains valid over the entire operating fre-quency range, DPLL remains overdamped variation hasnegligible impact on loop stability.

B. Estimating the Cancellation Gain

As has been discussed, accurate calibration of the cancel-lation gain is vital to the performance of any supply noisecancellation technique, which can be viewed as an applicationof adaptive control as described in the Appendix [18]. In theproposed background calibration approach, we hypothesizethat by adding a low-frequency test signal to the supply of theoscillator, as illustrated in Fig. 9, and adjusting until thetest signal completely disappears at the accumulator outputleads to convergence of to the optimum value. Intuitively,if the noise cancelling circuit accurately cancels the injectedtest signal, then the accumulator output should not change in


Fig. 10. DCO supply node transfer functions to: (a) DPLL output and(b) accumulator output � .

steady-state. A low-frequency, deterministic digital test signal,, is converted to an analog voltage and added to the DCO

supply voltage. Because the supply noise cancellation circuit isindiscriminate of the noise source, adjusting the cancellationgain to cancel also suppresses supply noise.

To understand the process of calibration, it is instructiveto first consider the transfer functions associated with the DCOsupply node. The magnitude response of the DCO supply to thePLL phase output transfer function is given by

(9)

and its magnitude response exhibits the well known bandpasstransfer characteristic, shown in Fig. 10(a). In other words thatboth the low- and high-frequency supply perturbations are sup-pressed at the PLL output.

On the other hand, the low-pass shape of the DCO supply tothe accumulator output transfer function, given by

(10)

illustrates that low-frequency disturbances on the supply voltageappear at the accumulator output while high-frequency distur-bances are attenuated by the loop, shown in Fig. 10(b). Basedon these observations, a low-frequency test signal was chosen tocalibrate the cancellation gain (see Fig. 11) under the assump-tion that the cancellation gain is independent of the supply noisefrequency. This assumption is validated by the measurement re-sults in Section V.

Note that in an overdamped DPLL, the bandwidth and thecenter frequency of the transfer functionsand are equal to the lower and thehigher of the two closed-loop poles, respectively. Con-sequently, a test signal (whose frequency is lower than )appears at the accumulator output with little attenuation, whileit is heavily suppressed at the DPLL output. In other words, alow-frequency test signal injected into DCO supply does notdegrade the output jitter and presence of the test signal in theaccumulator output provides a measure of VCO supply noisesensitivity. Therefore, the accumulator output is used to contin-uously calibrate the cancellation gain.

Fig. 11. Illustration in the design criterion in the choice of test signal frequency.

Fig. 12. Time-domain waveforms illustrating the evolution of the accumulatoroutput � . (a) Without cancellation. (b) With cancellation.

Shown in Fig. 12 is the time domain waveform of thecalibration code , the test signal , and theaccumulator output . In the absence of supply noise can-cellation and owing to the low-pass characteristic of

, a scaled version of the test signal appearsat the accumulator output, as shown in Fig. 12(a). When thecalibration is enabled, the cancellation gain is adjusted untilthe test signal completely disappears at the accumulator output,as shown in Fig. 12(b). Under this condition, both the testsignal and the supply noise are accurately cancelled at theDCO output, and the DPLL becomes insensitive to noise onthe ring oscillator supply. Because the DPLL output phase isnot disturbed by supply noise and assuming the absence of anyother noise sources, the accumulator output remains fixed.

IV. BUILDING BLOCKS

In this section, the transistor-level implementation of keybuilding blocks is discussed. The PFD is implemented using the


Fig. 13. Schematic of the proposed ring oscillator with supply noisecancellation.

well-known three-state architecture and is implemented usingthe pass transistor structure [19]. A sense-amplifier flip-flopis used as the bang–bang phase detector in the digital integralpath [20], and all digital building blocks are synthesized usingstandard cells. The design details of the supply noise insensitiveDCO and the proportional and integral path DACs are discussedin the following.

A. Supply Noise Insensitive DCO

The schematic of the ring oscillator, including test signalinjection and supply noise cancellation circuitry, is shown inFig. 13. Because the test signal and supply noise must have thesame transfer function, the test signal is directly injected intothe VCO supply using a digitally controlled resistor .A fixed resistor provides the nominal VCO supply current,while controls the supply resistance and varies the in-ternal VCO supply [21]. To minimize the headroompenalty, voltage drop across the variable resistor is designed tobe less than 20 mV at 1.5 GHz output frequency, and less than30 mV under all operating conditions.

The three-stage ring oscillator is composed of pseudo-dif-ferential delay cells, as shown in Fig. 13. The cross-coupledPMOS transistors guarantee differential operation of the delaycells without using a tail-current bias [22]. The integral and pro-portional controls are implemented by tuning the strength of thelatch load and the output time constant, respectively. To min-imize supply noise coupling, integral control voltage iscoupled to instead of ground. However, the ofthe latch-load PMOS transistors varies with the supply voltage,causing the current in the delay cell to change. An increase in thesupply voltage leads to an increase in the current, and thereforean increase in the oscillation frequency. Since the supply noiseinjects additional current into the VCO, adding cancellation cir-cuitry to sink the same amount of current eliminates the noise

Fig. 14. Block diagram of the complete supply noise insensitive DCO.

Fig. 15. Circuit implementation of the proportional path DAC used to generate� .

appearing at the output. In other words, this oscillator and thecancellation circuitry exhibit positive and negative supply noisesensitivities, respectively. After calibration, these sensitivitiescancel, and the VCO has ideally zero supply voltage sensitivity.The injected test signal along with supply noise is cancelled byusing transistors, , at delay cell outputs in the VCO,as shown in Fig. 13. Transistor couples supply noise to thegates of the cancelling transistors with a digitally calibrated gainthat is set by current . Intuitively, when the supply voltage in-creases, the current in the oscillator increases leading to an in-crease in the oscillation frequency. At the same time, voltage

also increases due to transistor , causing the cancellingtransistors to sink more current to ground. This reduces the os-cillator frequency thus compensating for the increase in the os-cillation frequency due to increased supply voltage. The cir-cuit schematic of the complete supply noise insensitive DCO isshown in Fig. 14. It consists of a three-level DAC and a 15-levelDAC to implement the proportional and integral control, respec-tively; variable resistor to inject the supply noise; and noise can-celling transistors that sinks the noise cancellation currentfrom the output of the oscillator. Simulations indicate that thenoise cancelling transistors, , degrade phase noise byabout 3 dB at 1 MHz offset. Because the phase noise contribu-tion from scales inversely with the calibration code


Fig. 16. Concept of bandwidth variation in the proportional path.

Fig. 17. Block diagram of the delta-sigma DAC used in the integral path.

, varying the proportional path bias current accordingly in-creases the PLL bandwidth and mitigates jitter degradation.

B. Proportional Path DAC

The circuit schematic of the DAC employed in the propor-tional path is shown in Fig. 15. Its inputs are driven by pulse-width modulated PFD output signals, Dn and Up, and is imple-mented with a three-level current source. As illustrated by thetruth table in Fig. 15, the three PFD states, Up, Reset, and Dnare mapped to , and currents, respectively, where isthe bias current. This unipolar implementation of the propor-tional control minimizes current mismatch compared to a con-ventional bipolar charge-pump [23]. A diode connected tran-sistor converts the DAC output current to a voltage. It is impor-tant to note that the cancellation of noise on the PDAC supplynode is only effective to the extent that the noise is correlated tothe VCO supply.

To alleviate the phase noise degradation due to noise can-celing transistors, the PLL loop bandwidth is scaled, withoutchanging the center frequency of the oscillator, by varying thedigitally controlled current . Decreasing the calibrationcode increases , which increases the proportionalgain, thus increasing PLL bandwidth. This mechanism isillustrated in Fig. 16. A biasing circuit is used to generate therequired voltages, and (see Fig. 15). Under phase lockcondition, both Up and Dn signals are identical and the currentDAC output . The current in addition to sets thenominal current , such that . The currentthrough the I-to-V converter determines the nominal propor-tional control voltage, . The biasing circuit ensuresthat is constant, thus keeping the center frequency fixed,while varying the bandwidth.

C. Integral Path DAC

The block diagram of the digital-to-analog converter used inthe integral path is shown in Fig. 17. A 14-bit second-orderdigital delta-sigma modulator (DSM) truncates the accumulator

Fig. 18. Circuit schematic of the 15-level current mode DAC and post filter.

Fig. 19. Prototype DPLL die photograph.

14-bit digital word, , to 15-levels and drives a 15-element cur-rent mode DAC. A current-mode DAC, consisting of 15 nom-inally matched current sources, converts the digital input to anequivalent output current, as shown in Fig. 18. Resistor R con-verts the DAC output current to voltage. A second-order passivelow-pass filter (LPF), with a 500 kHz bandwidth, suppressesout-of-band quantization error and generates the integral controlvoltage of the oscillator, . The delta-sigma DAC architectureeases hardware requirements, but the phase shift introduced byLPF increases loop latency and degrades the jitter performance.In the proposed DPLL, dithering jitter is suppressed by ignoringthe lower four least significant bits of the accumulator outputand passing only the 14 most significant bits to the DAC.

V. EXPERIMENTAL RESULTS

The proposed DPLL was fabricated in a 0.13 m CMOSprocess, and the die photograph of the prototype chip isshown in Fig. 19. It occupies an active area of 0.08 mm(200 m 400 m). The analog portion occupies 50% (4%for the VCO and 46% for the remaining analog circuits); thedigital portion occupies 37.5%; while the test signal generation,


Fig. 20. DPLL measurement setup.

Fig. 21. Measured long-term jitter histograms (50 k hits) at 1.5 GHz outputfrequency for 20 mV white Gaussian supply noise.

calibration logic, and cancellation circuitry occupy only 12.5%of the overall DPLL area.

The measurement setup used to characterize the prototypeIC is shown in Fig. 20. The supply noise measurements wereperformed by modulating the VCO supply with either a whiteGaussian noise or a sinusoidal tone. An arbitrary waveformgenerator (Tektronix AWG7122B) was used to inject whitenoise, while an RF signal generator (Fluke 6062A) was usedto introduce sinusoidal noise tones on the VCO supply. Anintegrated supply noise monitor (implemented using a widebandwidth voltage follower) was used to measure the amountof on-chip VCO supply noise and guarantee the fidelity of allsupply noise measurements. The input reference clock wasgenerated using the same arbitrary waveform generator. Sincethe prototype chip’s feedback divide ratio is fixed at four, thedesired output frequency was obtained by varying the refer-ence frequency. A communication signal analyzer (TektronixCSA8200) was used for the time-domain long-term absolutejitter measurements.

A wide range of measurements were performed to evaluatethe performance of the prototype chip and validate the pro-posed deterministic background supply noise calibration tech-nique. All measurements were performed at an output frequencyof 1.5 GHz unless otherwise specified. Fig. 21 shows the mea-sured jitter histograms of four different test signal and supplynoise conditions. In the absence of both the supply noise andtest signal, the measured absolute peak-to-peak jitter with 50 khits is 47 ps. When a 10 mV test signal is added, minimal jitter

Fig. 22. Measured long term jitter histograms (50 k hits) at 1.5 GHz outputfrequency for 30 mV , 10 MHz single tone supply noise.

Fig. 23. Measured peak-to-peak jitter as a function of supply noise frequencyat 1.5 GHz output frequency.

degradation is observed with the peak-to-peak jitter increasingby only 3 ps. When a 20 mV white Gaussian supply noise isadditionally superimposed on the supply voltage, the peak-to-peak jitter increases to 170 ps, indicating the high supply noisesensitivity of the oscillator. When cancellation is enabled, thecalibration loop converges to the digital code 4, and the outputjitter is reduced from 170 to 50 ps, thus illustrating the effec-tive cancellation achieved by the proposed architecture. Becausethe VCO is most sensitive to supply noise tones in the vicinityof the DPLL bandwidth (see Fig. 10), jitter degradation is atits worst under this condition. To characterize the jitter perfor-mance under this worse-case condition, a 30 mV , 10 MHznoise tone is injected on the VCO supply, and the peak-to-peakjitter without and with cancellation was measured to be 330 and50 ps, respectively (see Fig. 22).

To evaluate the effective cancellation bandwidth of theproposed scheme, the supply noise frequency is swept from0.1 MHz-to-2 GHz, and the measured peak-to-peak jitter isplotted in Fig. 23. Since the noise on the DCO supply is band-pass filtered by the PLL, the supply noise sensitivity is highestaround the PLL bandwidth (approximately 10 MHz). Whencancellation is enabled, the jitter degradation is mitigated overa wide range of supply noise frequencies, thus illustrating thevery wide cancellation bandwidth of the proposed scheme.

To ensure that the on-chip digital self-calibration algorithmconverged to the optimal cancellation gain, the calibration codewas set externally and the measured rms jitter is plotted inFig. 24 under different supply noise conditions. The optimal


Fig. 24. Measured rms jitter for different supply noise conditions.

Fig. 25. Measured rms jitter as a function of the 5-bit calibration code at 1.5and 2 GHz output frequencies.

calibration code is equal to 4 and is independent of supplynoise frequency. The calibration loop always converged to thesame calibration code of 4 under the same set of conditions.Thus, it can be concluded that the supply noise sensitivity isindependent of the supply noise frequency, which validatesour earlier assumption that the cancellation gain calibrated ata single test signal frequency is optimal at all supply noisefrequencies.

The measured rms jitter, plotted as a function of the 5-bitcalibration code at 1.5 GHz and 2 GHz output frequencies inFig. 25, illustrates that the supply noise sensitivity is a functionof DCO frequency. In both cases, the on-chip calibration loopsconverged to the optimum codes of 4 and 16, respectively.

The effect of DC level variation of the supply voltage is ob-tained by varying the supply voltage by . The rms jitterwith three different supply voltages is plotted as a function ofthe calibration code in Fig. 26. The results show that the supplynoise sensitivity is also a function of the DC level of the supplyvoltage. As with different supply noise frequencies, and dif-ferent operating frequencies, the calibration loop converged tothe optimum code for these different supply voltages.

The range of the proposed background cancellation schemeis evaluated by plotting the measured worst-case peak-to-peakjitter over the entire range of DPLL output frequencies, asshown in Fig. 27. With a 30 mV , 10 MHz sinusoidalsupply noise tone, accurate cancellation is achieved over

Fig. 26. Measured rms jitter at three different supply voltages.

Fig. 27. The worst-case peak-to-peak jitter versus DPLL output frequency fora 30 mV , 10 MHz supply noise tone.

Fig. 28. Optimum calibration code versus output frequency, illustrating thecancellation range as 0.8–2.5 GHz.

800 MHz-to-2.5 GHz output frequencies, while only partialcancellation is achieved outside this range. This is due to thedynamic range limitation of the cancellation circuitry. Theoptimum calibration code saturates outside the cancellationrange, resulting in only partial cancellation of supply noise (seeFig. 28). The cancellation range can be further extended eitherby increasing the dynamic range of the calibration current orincreasing the size of noise cancelling transistors – orboth. It is worth mentioning that in the presence of 20 mVwhite Gaussian noise ( mV ), the peak-to-peak jitter


Fig. 29. The measured power supply noise rejection (PSNR) performance.

TABLE IDPLL PERFORMANCE SUMMARY

did not degrade over the entire range of operating frequencies,400 MHz-to-3 GHz. The relatively high jitter floor limits theability to measure the actual effectiveness of the cancellationscheme, therefore, frequency-domain measurements using atest setup similar to that outlined in [8] were performed. Thepower supply noise rejection (PSNR) curve obtained withsupply noise amplitude of 30 mV is plotted in Fig. 29.The worst-case PSNR of dB with cancellation enabledrepresents an improvement of 32 dB over the PSNR withoutcancellation.

The measured power consumption of the proposed DPLLover the entire range of output frequencies is plotted in Fig. 30.The cancellation circuitry (including noise cancelling transis-tors, on-chip test signal generation, and background calibrationlogic) consumes less than 340 W which amounts to only 9.5%of total DPLL power dissipation at 1.5 GHz output frequency.

The performance of the prototype DPLL is summarized inTable I and compared with the state-of-the-art PLLs in Table II.Compared to PLLs with supply noise cancellation, the normal-

ized power of the proposed DPLL is six times lower. The worst-case supply noise rejection is better than dB without usingany decoupling capacitor.

VI. DISCUSSION: CANCELLATION VERSUS REGULATION

Within the scope of phase-locked loops there are twocommon methods used to mitigate power supply noise. Onetechnique is supply noise cancellation (with advancement ofthis technique being the focus of this paper), while the otheris supply noise regulation. The proposed noise cancellationtechnique proved to be effective, with minimal power and areapenalties. When area is a premium, the proposed cancellationtechnique may be preferred because it does not require a largecapacitor. However, the addition of supply noise cancellingtransistors may increase phase noise. In this section, the pro-posed supply noise cancellation technique is compared withregulation technique, including highlights of common PLLdesign constraints and tradeoffs.

A. Phase Noise

To analyze each technique’s impact on phase noise, the pro-posed ring oscillator was simulated across process corners at1.5 GHz oscillation frequency. Simulation results demonstratethat the cancellation technique (with all noise cancellationtransistor active) incurs 1 dBc/Hz additional phase noise ascompared to the regulation technique with 200 mV dropoutvoltage. However, when all noise cancellation transistors areinactive, phase noise is 1 dBc/Hz less than the regulationtechnique. These results demonstrate a correlation betweensupply noise and oscillator phase noise for the implementedoscillator architecture. Note that in the implemented oscillatorarchitecture, supply noise sensitivity decreases as oscillationfrequency increases, resulting in a lower phase noise penalty athigher frequencies.

B. Tuning Range

Both supply noise cancellation and regulation techniqueslimit the maximum oscillation frequency due to additionaldelay stage loading with noise canceling transistors and re-duced supply voltage, respectively. To quantify the tuning rangelimitation in both cases, transistor-level simulation results forthe tuning ranges of the implemented oscillator across processcorners (operating at 1 V supply) are given below.

1) Without noise canceling transistors and without test signalheadroom penalty: 0.4–3.9 GHz.

2) With the noise canceling transistors and with test signal:0.2–3.2 GHz.

a) With all noise canceling transistors active, the rangeis 0.2–3.0 GHz.

b) With all noise canceling transistors inactive, the rangeis 0.3–3.2 GHz.Note that because the optimal calibration code in-creases with increasing operating frequency, the min-imum operating frequency will correspond to the casewhen all canceling transistors are active (0.2 GHz),while the maximum operating frequency will corre-spond to the case when all the canceling transistorsare inactive (3.2 GHz).


Fig. 30. Measured power consumption at output frequencies ranging from 400 MHz-to-3 GHz.

TABLE IIPERFORMANCE COMPARISON OF THE PROPOSED DPLL WITH STATE-OF-THE-ART DESIGNS

3) When the oscillator supply is regulated with a 200 mVdropout voltage regulator, the operating range is reducedto 0.2–2.4 GHz.

It is difficult to determine which of the two supply noise mit-igation methods will offer the most advantageous solution in ageneral sense. Oscillator speed and phase noise will depend onthe required tuning range, process, regulator design, and amountof noise suppression required, as well as the ring oscillator ar-chitecture. Combining supply noise cancellation with regula-tion may assist relaxation of the tradeoffs of each of the twotechniques.

VII. CONCLUSION

Supply noise cancellation is proposed as an attractive al-ternative to conventional suppression techniques implementedusing supply-regulated architectures. A digital phase-locked

loop (DPLL) that employs noise cancellation to mitigate per-formance degradation due to noise on the ring oscillator supplyvoltage is presented. A deterministic test signal-based digitalbackground calibration is used to accurately set the cancella-tion gain and thus achieve accurate cancellation under differentprocess, voltage, temperature, and frequency conditions. Ahybrid, linear proportional control and bang–bang digital inte-gral control, is used to obviate the need for a high-resolutiontime-to-digital converter and reduce jitter due to frequencyquantization error. Fabricated in 0.13 m CMOS technology,the DPLL operates from a 1.0 V supply and achieves an oper-ating range of 0.4–3 GHz. At 1.5 GHz, the DPLL consumes2.65 mW power of which the cancellation circuitry consumesabout 280 W. The proposed noise cancellation scheme re-duces the DPLL’s peak-to-peak jitter from 330 to 50 ps inthe presence of 30 mV , 10 MHz supply noise tone. The


DPLL occupies an active die area of 0.08 mm , of which thecalibration logic and cancellation circuitry occupy only 12.5%.

APPENDIX

The proposed deterministic test signal-based digital back-ground calibration can be viewed as an application of adaptivecontrol [18]. The background calibration estimates the supplynoise gain, , and sets the cancellation gain,accurately to track . In the proposed implementation

(11)

(12)

where and are the DC gains of and, and and are the normalized transfer func-

tions, of the noise gain and the cancellation gain, respectively.The adaptive system will be stable if these transfer functions,

and , are strictly positive real (SPR) [18]. In theproposed implementation, the transfer functions can be approx-imated as

(13)

(14)

where is the nominal cancellation gain and is thecorrection factor to achieve optimal cancellation gain. Byvirtue of our circuit implementation, and exhibitnominally identical single pole low-pass transfer characteris-tics with a bandwidth much greater than the PLL bandwidth.Consequently, they satisfy the SPR conditions, thus guaran-teeing system stability. In steady-state, the correction factor

converges to , resulting in , as desired.Large mismatch between the transfer functions, and

, manifests as unmodeled dynamics and could lead toconvergence failure or suboptimal cancellation gain [18]. Thetest signal (sometimes referred to as training signal) was chosento not affect the loop dynamics and to simplify the hardwarerequirements. A sinusoidal test signal is easier to analyze, butit is more complicated to generate digitally. A pseudorandombinary sequence (PRBS), can also be used as a test signal.However, this will degrade the phase noise performance andalso increases the hardware complexity of the correlator. Inview of these tradeoffs, a low-frequency triangular test signalwas employed in the prototype chip. The choice of test signalfrequency will determine the calibration convergence time.Since the test signal needs to be at a lower frequency than PLLloop bandwidth, its frequency was chosen to be 100 kHz. At1.5 GHz output frequency, the calibration converges in fourcalibration cycles, approximately 40 s. Due to the use of 5-bitcalibration code, the startup time can be up to 31 cycles, or 310

s. Note that, once steady-state is reached, the calibration loopcontinuously tracks slow variations in process, temperature,and DC supply voltage.

ACKNOWLEDGMENT

The authors would like to thank Dongbu HiTek for pro-viding the IC fabrication; and T. Musah, G. Balamurugan, andF. O’Mahony of Intel Laboratories for useful discussion. They

would also like to thank the anonymous reviewers for providingconstructive suggestions to improve the quality of this paper.

REFERENCES

[1] R. B. Staszewski, J. L. Wallberg, S. Rezeq, C.-M. Hung, O. E. Eliezer,S. K. Vemulapalli, C. Fernando, K. Maggio, R. Staszewski, N. Barton,M.-C. Lee, P. Cruise, M. Entezari, K. Muhammad, and D. Leipold,“All-digital PLL and transmitter for mobile phones,” IEEE J. Solid-State Circuits, vol. 40, no. 12, pp. 2469–2482, Dec. 2005.

[2] J. Lin, B. Haroun, T. Foo, J.-S. Wang, B. Helmick, S. Randall, T. May-hugh, C. Barr, and J. Kirkpatrick, “A PVT tolerant 0.18 MHz to 600MHz self-calibrated digital PLL in 90 nm CMOS process,” in ISSCCDig. Tech. Papers, Feb. 2004, pp. 488–489.

[3] M. Song, Y.-H. Kwak, S. Ahn, W. Kim, B. Park, and C. Kim, “A 10MHz to 315 MHz cascaded hybrid PLL with piecewise linear calibratedTDC,” in Proc. IEEE Custom Int. Circuits Conf. (CICC), Sep. 2009, pp.243–246.

[4] J. A. Tierno, A. V. Rylyakov, and D. J. Friedman, “A wide powersupply range, wide tuning range, all static CMOS all digital PLL in65 nm SOI,” IEEE J. Solid-State Circuits, vol. 43, no. 1, pp. 42–51,Jan. 2008.

[5] P. Hanumolu, G.-Y. Wei, U. Moon, and K. Mayaram, “Digitally-en-hanced phase-locking circuits,” in Proc. IEEE Custom Int. CircuitsConf. (CICC), Sep. 2007, pp. 361–368.

[6] S.-Y. Yang and W.-Z. Chen, “A 7.1 mW 10 GHz all-digital frequencysynthesizer with dynamically reconfigurable digital loop filter in 90 nmCMOS,” in ISSCC Dig. Tech. Papers, Feb. 2009, pp. 90–91.

[7] C.-M. Hsu, M. Z. Straayer, and M. H. Perrott, “A low-noise, wide-BW3.6 GHz digital �� fractional-N frequency synthesizer with a noise-shaping time-to-digital converter and quantization noise cancellation,”in ISSCC Dig. Tech. Papers, Feb. 2008, pp. 340–341.

[8] A. Arakali, S. Gondi, and P. Hanumolu, “Low-power supply-regulationtechniques for ring oscillators in phase-locked loops using a split-tunedarchitectur,” IEEE J. Solid-State Circuits, vol. 44, no. 8, pp. 2169–2181,Aug. 2009.

[9] K.-Y. K. Chang, J. Wei, C. Huang, S. Li, K. Donnelly, M. Horowitz,Y. Li, and S. Sidiropoulos, “A 0.44-Gb/s CMOS quad transceiver cellusing on-chip regulated dual-loop PLLs,” IEEE J. Solid-State Circuits,vol. 38, no. 5, pp. 747–754, May 2003.

[10] S. Sidiropoulos, D. Liu, J. Kim, G.-Y. Wei, and M. Horowitz, “Adap-tive bandwidth DLLs and PLLs using regulated supply CMOS buffers,”in Proc. IEEE Symp. VLSI Circuits, Jun. 2000, pp. 124–127.

[11] E. Alon, J. Kim, S. Pamarti, K. Chang, and M. Horowitz, “Replica com-pensated linear regulators for supply-regulated phase-locked loops,”IEEE J. Solid-State Circuits, vol. 41, no. 2, pp. 413–424, Feb. 2006.

[12] W. Grollitsch, R. Nonis, and N. Da Dalt, “A 1.4 psrms-period-jitterTDC-less fractional-N digital PLL with digitally controlled ring oscil-lator in 65 nm CMOS,” in ISSCC Dig. Tech. Papers, Feb. 2010, pp.478–479.

[13] M. Mansuri and C.-K. K. Yang, “A low-power adaptive bandwidth plland clock buffer with supply-noise compensation,” IEEE J. Solid-StateCircuits, vol. 38, no. 11, pp. 1804–1812, Nov. 2003.

[14] T. Wu, K. Mayaram, and U. Moon, “An on-chip calibration techniquefor reducing supply voltage sensitivity in ring oscillators,” IEEE J.Solid-State Circuits, vol. 42, no. 4, pp. 775–783, Apr. 2007.

[15] A. Elshazly, R. Inti, W. Yin, B. Young, and P. Hanumolu, “A 0.4-to-3GHz digital PLL with supply-noise cancellation using deterministicbackground calibration,” in ISSCC Dig. Tech. Papers, Feb. 2011, pp.92–93.

[16] W. Yin, R. Inti, A. Elshazly, B. Young, and P. Hanumolu, “A 0.7-to-3.5GHz 0.6-to-2.8 mW highly digital phase-locked loop with bandwidthtracking,” IEEE J. Solid-State Circuits, vol. 46, no. 8, pp. 1870–1880,Aug. 2011.

[17] P.-Y. Wang, J.-H. C. Zhan, H.-H. Chang, and H.-M. S. Chang, “Adigital intensive fractional-N PLL and all-digital self-calibrationschemes,” IEEE J. Solid-State Circuits, vol. 44, no. 8, pp. 2182–2192,Aug. 2009.

[18] K. J. Åström and B. Wittenmark, Adaptive Control Second Edition.Reading, MA: Addison-Wesley, 1995.

[19] M. Mansuri, D. Liu, and C.-K. K. Yang, “Fast frequency acquisitionphase-frequency detectors for Gsamples/s phase-locked loops,” IEEEJ. Solid-State Circuits, vol. 37, no. 10, pp. 1331–1345, Oct. 2002.

[20] B. Nikolic, V. G. Oklobdzija, V. Stojanovic, W. Jia, J. K.-S. Chiu, andM. Leung, “Improved sense-amplifier-based flip-flop: Design and mea-surements,” IEEE J. Solid-State Circuits, vol. 35, no. 6, pp. 876–884,Jun. 2000.


[21] D.-H. Oh, D.-S. Kim, S. Kim, D.-K. Jeong, and W. Kim, “A 2.8 Gb/sall-digital CDR with a 10 b monotonic DCO,” in ISSCC Dig. Tech.Papers, Feb. 2007, pp. 222–598.

[22] J. Lee and B. Kim, “A low-noise fast-lock phase-locked loop with adap-tive bandwidth control,” IEEE J. Solid-State Circuits, vol. 35, no. 8, pp.1137–1145, Aug. 2000.

[23] P. Hanumolu, M. Kim, G.-Y. Wei, and U. Moon, “A 1.6 Gbps digitalclock and data recovery circuit,” in Proc. IEEE Custom Int. CircuitsConf. (CICC), Sep. 2006, pp. 603–606.

[24] J. Crossley, E. Naviasky, and E. Alon, “An energy-efficient ring-oscil-lator digital PLL,” in Proc. IEEE Custom Int. Circuits Conf. (CICC),Sep. 2010.

Amr Elshazly (S’04) received the B.Sc. (Hons) andM.Sc. degrees in electrical engineering from AinShams University, Cairo, Egypt, in 2003 and 2007,respectively. Currently, he is working towards thePh.D. degree in electrical engineering at the OregonState University, Corvallis.

From 2004 to 2006, he was a part-time VLSI Cir-cuit Design Engineer at AIAT, Inc. working on the de-sign of several RF building blocks such as PLLs, FMreceivers, and LNAs. From 2006 to 2007, he was withMentor Graphics, Inc., Cairo, designing multistan-

dard clock and data recovery circuits for high speed-serial links. His researchinterests include frequency synthesizers, digital phase-locked loops, clock anddata recovery circuits, high-speed serial links, and low-voltage mixed-signalcircuits.

Mr. Elshazly received the Analog Devices Outstanding Student DesignerAward in 2011.

Rajesh Inti (S’11) received the B.E. degree fromthe National Institute of Technology, Tiruchirapalli,India, in 2003 and the M.S. degree from the IndianInstitute of Technology, Madras, in 2007. Currently,he is working towards the Ph.D. degree in electricalengineering at Oregon State University, Corvallis.

From 2003 to 2005, he was a Design Engineer atAnalog Devices, India. His current research inter-ests include high-speed and low-power serial linktransceivers, clock and data recovery circuits, digitalphase-locked loops and data-conversion circuits.

Mr. Inti received the 2011 Analog Devices Outstanding Student DesignerAward.

Wenjing Yin (S’09) received the B.Sc. and M.Sc.degrees in microelectronics from Fudan University,Shanghai, China, in 2004 and 2007, respectively,and the Ph.D. degree in electrical engineering fromOregon State University, Corvallis, in 2010.

She was a Research Assistant at Fudan Univer-sity until 2007, where she focused on pipelinedanalog-to-digital convertor and mixed-signal circuitstechniques. She was also a Research Assistant atthe School of Electrical Engineering and ComputerScience, Oregon State University, from 2007 to

2010, where she developed circuits and architectures for digital-assistedphase-locked loop and clock and data recovery for high-speed I/O interfaces.She is currently a Senior Design Engineer in the R&D Division of KawasakiMicroelectronics America, working on high-speed I/O interfaces and digitalequivalent implementation of analog circuits.

Dr. Yin received the Intel Student Scholarship Award at the 2010 Custom In-tegrated Circuits (CICC) conference. She serves as a Reviewer for the IEEEJOURNAL OF SOLID-STATE CIRCUITS, the IEEE TRANSACTIONS ON CIRCUITS

AND SYSTEMS I and II, and the IEEE TRANSACTIONS ON VERY LARGE SCALE

INTEGRATION SYSTEMS.

Brian Young (S’10) received the B.S. degree inelectrical engineering from the Pennsylvania StateUniversity, University Park, in 2000. Currently, heis working towards the Ph.D. degree in electricalengineering at Oregon State University, Corvallis.

From 2000 to 2003, he was a Design Engineer withthe Timing Solutions Operation of Motorola. From2003 to 2007, he was a mixed-signal design engineerwith AMI Semiconductor. His research interests in-clude low-voltage mixed-signal circuits, time-to-dig-ital converters, digital phase-locked loops, and time-

based ADCs.Mr. Young received the 2010 Analog Devices Outstanding Student Designer

Award.

Pavan Kumar Hanumolu (S’99–M’07) receivedthe B.E. (Hons) degree from the Birla Institute ofTechnology and Science, Pilani, India, in 1998,the M.S. degree from the Worcester PolytechnicInstitute, Worcester, MA, in 2001, and the Ph.D.degree from the Oregon State University, Corvallis,in 2006.

He is currently an Assistant Professor at theSchool of Electrical Engineering and Computer Sci-ence, Oregon State University. His research interestsinclude high-speed, low-power I/O interfaces, digital

techniques to compensate for analog circuit imperfections, time-based signalprocessing, and power-management circuits.

Dr. Hanumolu received the National Science Foundation CAREER Award in2010, the Engelbrecht Young Faculty Award in 2009, the Professor of the YearAward in 2008, and the Faculty of the Year Award in 2011 from the Collegeof Engineering and the School of Electrical Engineering and Computer Science(EECS), Oregon State University. He was a corecipient of the Custom IntegratedCircuits Conference (CICC) 2006 Best Student Paper Award. He was an Asso-ciate Editor of the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS-II: ExpressBriefs, from 2008 to 2010, and a Guest Editor of the JOURNAL OF SOLID-STATE

CIRCUITS from 2009 to 2011. He currently serves as an Associate Editor ofthe IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION SYSTEMS, as amember of the IEEE Custom Integrated Circuits Conference Technical ProgramCommittee and Analog Signal Processing Program Committee of the IEEE In-ternational Symposium on Circuits and Systems.

Documents

A 0.4-To-3 GHz Digital PLL With PVT Insensitive Supply Noise Cancellation Using Deter Minis Tic Background Calibration