8.5 New Physical Insight and Modeling of Second Breakdown (It2) Phenomenon in Advanced ESD Protection DevicesNew Physical Insight and Modeling of Second Breakdown (It2) Phenomenon in Advanced ESD Protection Devices
Amitabh Chatterjee, Charvaka Duvvury* and Kaustav Banerjee Department of Electrical and Computer Engineering, University of California, Santa Barbara, CA 93106
*Silicon Technology Development, Texas Instruments, Dallas, TX 75243
Abstract Second breakdown phenomenon in advanced NMOS ESD
protection devices has remained an enigma due to the complex electrical and thermal effects that are responsible for its triggering. For the first time, we present a critical study of the high current phenomenon in ultra short-time scale to understand the physics of instability in protection devices around the second breakdown region. It is demonstrated that for advanced protection devices, carrier heating in the high field drain region causes a fall in the saturation drift velocity, which increases the transit time of carriers through the depletion region. This in turn, causes greater impact ionization due to higher accumulation of avalanche-generated carriers; leading to the formation of a propagating ionizing wave front, which culminates in a regenerative avalanche injection induced second breakdown failure.
Introduction Accurate modeling and simulation framework for optimal
ESD protection device design is a critical need for ULSI circuits [1,2,3]. With ever-changing technology and competition in the market, one way to reduce the developmental cycle is to develop accurate simulation capability through good physical insight of the phenomenon causing the failure of the ESD protection devices. While present ESD simulation tools [2,3] have been able to accurately model the MOS snapback region caused by avalanche breakdown in the typical high-current I-V characteristics (defined by It1), second breakdown (It2) phenomenon that effectively determines the robustness of MOS based ESD protection devices, has remained relatively less understood. It has been traditionally linked to rise of temperature, which causes the intrinsic carrier concentration to equal the background doping concentration [4] and takes the device into a negative differential resistance (NDR) mode [5]. In the NDR mode, the voltage and current are unstable, and the voltage decreases until a stable bias condition is reached. This stable bias condition has been shown to be a micro-plasma formed due to the constriction of current into a filament and which subsequently results in collapse of voltage across the device [2, 5]. Although this macroscopic model, which is based on the critical temperature rise, has also been correlated with critical power dissipation through 1-D analytical electro-thermal model, the physical mechanisms behind the current controlled NDR are not clear, making it rather ineffective for predictive modeling [2]. Also, while computationally intensive electro- thermal device simulations and related mixed-mode simulations have shown that this critical temperature triggering the second breakdown peaks at the sidewall junction at the drain end, their role as a predictive tool is rather limited due to the problems of numerical convergence [2, 3]. The macroscopic understanding has also been implemented through circuit models, which involve solving for the current and voltage boundary conditions that cause the critical power dissipation to trigger second
breakdown of the device [6]. This methodology evaluates the full functionality of the ESD protection circuit along with the rest of the design which it is protecting by solving the coupled analytical expressions around the snapback region (It1), which involves extracted SPICE parameters like the gain (β) of lateral n/p/n transistor, multiplication factor (M), and substrate resistance (Rsub) [2, 6]. In this technique, the collapse of voltage is explained due to the thermal generation of holes, which is required to support the base current in the parasitic lateral bipolar transistor. However, this technique can only restrictively predict few process related variations of second breakdown characteristics of the device e.g., dependence on the channel length [6]. Thus, absence of microscopic understanding behind the second breakdown phenomenon has so far hindered the development of useful models having strong correlation with experiments, and thereby restricted the optimization of process and device design for advanced ESD protection circuits. For the first time, we present a critical study of the high current phenomenon in ultra short-time scale and propose a microscopic model to understand the physics of instability in protection devices around the second breakdown region.
Experimental Setup We have recently developed a new controlled technique of
applying variable speed ultra-fast high voltage pulses (ranging from 100s of volts to a few KV) across devices [7]. The new pulsing technique (Fig. 1a) involves two stages where the external trigger pulse applied to the stage 1 transistor (T1) causes a negative voltage pulse to appear across the transistor (T2) in stage 2 due to the discharging of the capacitor C1. The rise time of the pulses (100 ps to a few µs) can be controlled using the circuit elements shown in Fig. 1a. It was observed that for very high speed ramps (300 V/1ns) the device under test (T2: the p/n-
/n+ structure shown in Fig. 1b – for which we used commercially available BJTs and shorted the base and emitter junction) exhibited collapse of voltage or second breakdown phenomenon, which is encountered during triggering of ESD protection devices. However, for wide range of intermediate ramp speeds (400 V ramped in a range of 700 ns to 10 ns), the device was indeterminate whether to go to second breakdown mode or the normal avalanche breakdown mode and hence exhibited erratic nature as shown in Fig. 2. Since the basic physics behind the second breakdown phenomenon remains similar for all the devices, we have first used non-isothermal transient 2-D simulation using current boundary condition [8] in these lowly doped p/n-/n+ – large area diode structures (Fig. 3).
The experimentally observed erratic choice of breakdown could be explained only due to a sensitive non-linear ionizing wave front traveling across the depletion region. This ionizing wave front, which is initiated due to a sudden build up of very high breakdown field at the p/n- diode junction, causes an excessive accumulation of mobile carriers in the depletion region. The transient build up of these mobile carriers
0-7803-9269-8/05/$20.00 (c) 2005 IEEE
modulating the space charge distribution is shown in Fig. 4a causing a shock wave like pattern due to a propagating breakdown field (Fig. 4b). The avalanche injection instability [9], which is caused due to this space charge build-up, has been analyzed through variation of saturated drift velocity (Vsat) of charge carriers. I-V curve (Fig. 5) for the device shows that for higher values of Vsat, mobile carriers could not accumulate, and hence the avalanche injection induced instability was not observed. However, for lower values of Vsat, excessive build up of space charge due to accumulation of mobile carriers leads to regenerative avalanche injection phenomenon as the front travels to the n-/n+ junction causing the second breakdown. Though thermal effects on Vsat were negligibly small for such fast ramps in these large area structures but with the shrinkage of the device size they were found to play a pivotal role in causing the second breakdown as discussed in the following section.
Electro-Thermal Simulation and Modeling of It2 Phenomenon
2-D electro-thermal simulations were performed to study the avalanche injection induced instability around high electric field drain region for an advanced NMOS protection device, as shown in Fig. 6. Fig. 7 shows that for lower values of ramp speed, It2 remains similar. However, it begins to show variations for very fast rising ramps. Fig. 8 shows that as current continues to increase beyond the snapback region, maximum value of temperature distribution (Tmax) in the device begins to increase, which causes the saturated drift velocity Vsat (that has a strong dependence on local thermal properties) to fall. The fall in saturation velocity Vsat causes an accumulation of mobile carriers. Thus, increase in transit time of the mobile carriers plays a critical role in giving them more time to stay in the high field drain region, leading to their excessive impact ionization, thus triggering a propagating instability due to build up of electric field from the mobile charge carriers. Thus in brief, avalanche generated mobile carriers have a dual role of first causing increased impact ionization, and secondly the redistribution of these generated mobile charges causes a space charge build up, which modifies the electric field. Accumulation of avalanche-generated electrons in the high field drain region (shown in Fig. 9a) leads to enhanced impact ionization as the space charge (shown in Fig. 9b) generated instability builds up. Increased impact ionization (shown in Fig. 9c) and subsequent redistribution of generated mobile carriers causes fall in the electric field (due to the ionized dopants) in some regions (shown in Fig. 9d) while it enhances the electric field at other regions where these mobile charges accumulate. The avalanche injection induced instability gains further strength as it propagates and leads to the accumulation of mobile carriers at the junction of lowly doped drain (LDD) region (n-) and highly doped drain region (n+). This can explain the experimentally observed role of both the effective drain diffusion depth below the salicide and substrate resistance in determining the ESD robustness, a phenomenon analogous to avalanche injection induced instability in p/n-/n+ structure [9,10].
Thus the saturated drift velocity (Vsat) is the key physical factor in this complex electro-thermal behavior of avalanche carrier transport which decides the average time carriers spend in the high field region causing the onset of avalanche injection induced second breakdown phenomenon. Through simulations, the role of saturated drift velocity was critically evaluated using PMI (physical model interface) accessible Canali’s model in the
simulator (as shown in Fig.10) [8]. Analysis of shock wave (the non linear ionizing wave front) during second breakdown through simulations involving parametric variations of device (e.g. channel length, doping concentration, etc.) exhibited that the triggering of second breakdown has strong dependence on field distribution in the drain region.
Finally, simulations were performed to study the impact of fast rising pulses on advanced SOI (Silicon on Insulator) structures with same channel length as that of the bulk device (Fig. 6b). In these devices, collapse of voltage is primarily due to the lateral triggering of the n/p/n bipolar structure, which is caused due to the floating nature of the substrate [2]. We believe that the collapse of voltage in this mechanism is fundamentally different from the avalanche injection induced second breakdown. Moreover, the lateral triggering in these devices leads to slower collapse (as shown by change in electron concentration around drain and source region - (Fig. 11)) in voltage when compared to the abrupt second breakdown phenomenon in the bulk NMOS devices. The lower thermal conductivity (κ) of the buried oxide plays a critical role in triggering the lateral n/p/n transistor, and simulations show that while lower κ can very easily trigger the lateral device, for higher κ the device exhibits oscillations and indeterminacy at the snapback region as shown in Fig. 12. The rise in temperature accentuates the regenerative turning ‘on’ of the B-E junction of the lateral parasitic BJT due to the charge collection in the floating body. While at higher thermal conductivities, this regenerative turning ‘on’ of the lateral device is prevented through better regulation of the device temperature and, in the process, exhibits small oscillations in the snapback region.
Conclusion In conclusion, the role of avalanche injection induced
instability leading to second breakdown has been modeled. We demonstrated, using rigorous simulations, that for advanced NMOS protection devices, carrier heating in the high field drain region causes a fall in the saturation drift velocity, which increases the transit time of carriers. This in turn, causes greater impact ionization due to higher accumulation of avalanche- generated carriers leading to the formation of a propagating ionizing wave front which culminates in a regenerative avalanche injection induced second breakdown failure. The regenerative mechanism occurs due to the mobile carrier generation and the induced high electric field that they produce. In this work, we have correlated the new model with earlier experimental works. The new physical insight into onset of the It2 (second breakdown) phenomenon will have significant implications for understanding the robustness of ESD protection devices, especially in the MUGFET in PDSOI devices through development of computer-aided design tools for optimized process, device and circuit design.
References [1] C. Duvvury et. al., IEDM, 2004, pp. 933-936. [2] A. Amersekera and C. Duvvury, Wiley & Sons, 2nd Edition, 2001. [3] K. Esmark, PhD Thesis, ETH, 2001. [4] H. A. Schafft et. al., TED, 1966, pp 613 – 615. [5] B. K. Ridley, Proc. Phys. Society, p. 954, 1963. [6] A. Amerasekera et. al., Proc IRPS, 1999, pp. 159 - 166. [7] A. Chatterjee et. al., J. of Applied Physics, Vol. 97 (8), 2005. [8] DESSIS Manual, ISE – TCAD, Zurich (2003). [9] P. Hower, TED, pp. 320-335, 1970. [10] A. Amerasekera et al., IEDM, 1996, pp. 893-896.
a
Fig. 7: Variation of second breakdown phenomenon with the ramp speed for the bulk NMOS device. For lower ramp speeds, the value of It2 tends to remain unchanged (observed experimentally using CDM-ESD model [1]). The variation of It2 for higher ramp speed can be a key issue that has to be considered for the robustness of ESD circuits with the scaling of technology.
Fig. 2: Voltage waveform across p/n-/n+ structure formed by a BJT (whose base emitter has been shorted) across which ultra fast ramp is applied. For an intermediate value of ramp rate (400V ramped in range of 700 ns to 10 ns) the device exhibits indeterminacy in choosing either of two breakdown states (avalanche or second breakdown) [7].
Fig. 4(b): Electric field distribution (through cut-line generation X=-3.5µm w.r.t Fig. 3) showing how modulation due to mobile carriers causes a prominent avalanche injection phenomenon as the ionizing wave front reaches n-/n+ junction and leads to collapse of voltage due to sustained and regenerative avalanche injection.
Fig. 4(a): Distribution of Space Charge (through cut line generation X=-3.5µm w.r.t Fig. 3). Avalanche generated carriers modify the space charge forming a shock wave pattern as the electrons move towards the n+ contact with a saturated drift velocity Vsat.
0
0.2
0.4
0.6
0.8
1.2
1.0
Temperature
0
0.2
0.4
0.6
0.8
1.2
1.0
Temperature
0
0.2
0.4
0.6
0.8
1.2
1.0
Temperature
-2 -1 0 1 20.5
Fig. 6 (a): Temperature distribution across the cross section of a 130 nm bulk NMOS structure used for transient simulation to understand the second breakdown phenomenon. (b) Temperature distribution in 130 nm SOI structure used for simulation.
-4
8 -10 -5 0
3.1×102 K 3.0×102 K 3.0×102 K 3.0×102 K 3.0×102 K
Lattice Temperature
8 -10 -5 0
3.1×102 K 3.0×102 K 3.0×102 K 3.0×102 K 3.0×102 K
Lattice Temperature
Fig. 3: Temperature distribution in the 2D structure of BJT used in the simulation whose base and emitter has been shorted.
(a)
rbb
Fig. 1: (a) Schematic showing a new controllable technique for applying variable speed ultra-fast high voltage pulses across devices [7]. (b) Shorting the base-emitter junction of the BJT (T2) allows pulse to be applied across p/n-/n+ structure in the device.
Fig. 5: Simulation illustrating that for similar ramp speed across the device (p/n-
/n+), lower values of Vsat show collapse of voltage due to regenerative avalanche injection induced instability as the ionizing wave front reaches n-/n+ junction. Vse and Vsh are the saturated drift velocities of electrons and holes.
Fig. 12: I-V characteristics of SOI devices showing a gradual second snapback compared to abrupt second breakdown, which is due to the slow turning ‘on’ of the lateral parasitic n/p/n BJT (which has been observed experimentally). Note that, (D)-decrease, (I)-increase.
Fig. 11: The distribution of electron concentration (through cut-line generation at Y=0.023µm w.r.t to Fig. 6b) in SOI device showing a gradual rise as the parasitic lateral n/p/n device in the floating substrate is turned ‘on’, which leads to the fall in device voltage as shown by change in drain and source electron concentration.
Fig. 9(c): Enhanced impact ionization (through cut-line generation at Y=0.015µm w.r.t to Fig. 6a) due to increase in mobile carriers and their subsequent redistribution causes it to peak around the heavily doped drain (n+) and lowly doped LDD (n-) region.
Fig. 10: I-V characteristics of NMOS showing the second breakdown phenomenon for different models. The models were dynamically changed as the device reached the second breakdown trigger point. The simulation showed that It2 is very sensitive to the factor Vsat,exp in the Canali model. Note that, (D) – decrease, (I) – increase.
Fig. 9(b): Distribution of space charge (through cut-line generation at Y=0.015µm w.r.t to Fig. 6a) build up due to electro-thermal instability resulting from fall in Vsat. This causes modulation of the mobile carrier induced space charge around the junction of heavily doped drain (n+) and lowly doped LDD region (n-).
Fig. 9(d): Electric field distribution (through cut-line generation at Y=0.015µm w.r.t to Fig. 6a) showing its fall due to elecro-thermally generated carriers (around AA’ region) and subsequently the distribution peaks around the junction of heavily doped drain (n+) and lowly doped LDD (n-) region.
Fig. 9(a): Distribution of electron concentration (through cut-line generation at Y=0.015µm w.r.t to Fig. 6a) rises due to fall in the Vsat and subsequent enhanced impact ionization, leading to the regenerative avalanche injection induced second breakdown (around AA′), and shifts the peak by around the junction of heavily doped drain (n+) and lowly doped LDD (n-) region.
Canali Model
lowF