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VLSI TechnologyVLSI Technologys ScalingScaling

s Moores LawMoores Laws 3D3D VLSIVLSI

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The beginningThe beginning

Microprocessors are essential to many of theMicroprocessors are essential to many of theproducts we use every day such as TVs, cars, radios,products we use every day such as TVs, cars, radios,

home appliances and of course, computers.home appliances and of course, computers.

Transistors are the main components ofTransistors are the main components of

microprocessors.microprocessors.

At their most basic level, transistors may seemAt their most basic level, transistors may seem

simple. But their development actually requiredsimple. But their development actually required

many years of painstaking research. Beforemany years of painstaking research. Before

transistors, computers relied on slow, inefficienttransistors, computers relied on slow, inefficient

vacuum tubes and mechanical switches to processvacuum tubes and mechanical switches to process

information. In 1958, engineersinformation. In 1958, engineers managed to put twomanaged to put two

transistors onto atransistors onto a SiliconSilicon crystal and create the firstcrystal and create the first

integrated circuit, whichintegrated circuit, which subsequentlysubsequently led to theled to the firstfirst

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Transistor Size ScalingTransistor Size Scaling

MOSFETperformanceimproves as size isdecreased:

shorter switchingtime, lower powerconsumption.

2 orders of magnitude reduction in transistor size in

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Significant BreakthroughsSignificant Breakthroughs

Transistor size: Intels research labs have recently shown the worlds smallest

transistor, with a gate length of 15nm. We continue to build smaller and smallertransistors that are faster and faster. We've reduced the size from 70 nanometer to 30

nanometer to 20 nanometer, and now to 15 nanometer gates.

Manufacturing process: A new manufacturing process called 130 nanometer

process technology (a nanometer is a billionth of a meter) allows Intel today to

manufacture chips with circuitry so small it would take almost 1,000 of these "wires"

placed side-by-side to equal the width of a human hair. This new 130-nanometer

process has 60nm gate-length transistors and six layers of copper interconnect. This

process is producing microprocessors today with millions of transistors and running

at multi-gigahertz clock speeds.

Wafer size: Wafers, which are round polished disks made of silicon, provide the base

on which chips are manufactured. Use a bigger wafer and you can reduce

manufacturing costs. Intel has begun using a 300 millimeter (about 12 inches)

diameter silicon wafer size, up from the previous wafer size of 200mm (about 8

inches).

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Major Design ChallengesMajor Design Challengess Microscopic issuesMicroscopic issues

ultra-high speedsultra-high speeds power dissipation andpower dissipation and

supply rail dropsupply rail drop

growing importance ofgrowing importance of

interconnectinterconnect

noise, crosstalknoise, crosstalk reliability,reliability,

manufacturabilitymanufacturability

clock distributionclock distribution

s Macroscopic issuesMacroscopic issues

time-to-markettime-to-market

design complexity (millionsdesign complexity (millions

of gates)of gates)

high levels of abstractionshigh levels of abstractions

design for testdesign for test

reuse and IP, portabilityreuse and IP, portability

systems on a chip (SoC)systems on a chip (SoC)

tool interoperabilitytool interoperability

Year Tech. Complexity Frequency Staff Size Staff Costs

1997 0.35 13 M Tr. 400 MHz 210 $90 M

1998 0.25 20 M Tr. 500 MHz 270 $120 M

1999 0.18 32 M Tr. 600 MHz 360 $160 M

2002 0.13 130 M Tr. 800 MHz 800 $360 M

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Integrated CircuitsIntegrated Circuitss Digital logic is implemented usingDigital logic is implemented using transistorstransistors inin integrated circuitsintegrated circuits

containing many gates.containing many gates. small-scale integrated circuits (SSI) contain 10 gates or lesssmall-scale integrated circuits (SSI) contain 10 gates or less medium-scale integrated circuits (MSI) contain 10-100 gatesmedium-scale integrated circuits (MSI) contain 10-100 gates large-scale integrated circuits (LSI) contain up to 10large-scale integrated circuits (LSI) contain up to 1044 gatesgates very large-scale integrated circuits (VLSI) contain >10very large-scale integrated circuits (VLSI) contain >1044 gatesgates

s Improvements in manufacturing lead to ever smaller transistorsImprovements in manufacturing lead to ever smaller transistorsallowing more per chip.allowing more per chip. >10>1077 gates/chip now possible; doubles every 18 months or sogates/chip now possible; doubles every 18 months or so

s Variety of logic familiesVariety of logic families

TTL - transistor-transistor logicTTL - transistor-transistor logic CMOS - complementary metal-oxide semiconductorCMOS - complementary metal-oxide semiconductor ECL - emitter-coupled logicECL - emitter-coupled logic GaAs - gallium arsenideGaAs - gallium arsenide

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What are shown on previous diagrams cover only the so called front endWhat are shown on previous diagrams cover only the so called front end

processing fabrication steps that go towards forming the devices andprocessing fabrication steps that go towards forming the devices and

inter connections between these devices to produce the functioning IC's. Theinter connections between these devices to produce the functioning IC's. The

end result are wafers each containing a regular array of the same IC chip orend result are wafers each containing a regular array of the same IC chip or

die. The wafer then has to be tested and the chips diced up and the good chipsdie. The wafer then has to be tested and the chips diced up and the good chips

mounted and wire bonded in different types of IC package and tested againmounted and wire bonded in different types of IC package and tested again

before being shipped out.before being shipped out.

From Howe, Sodini: Microelectronics:An

Integrated Approach, Prentice Hall

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MooresMoores LawLaw

s Gordon E. Moore - Chairman Emeritus of Intel CorporationGordon E. Moore - Chairman Emeritus of Intel Corporation

s

1965 - observed trends in industry -1965 - observed trends in industry - ## of transistors on ICs vs. release datesof transistors on ICs vs. release dates:: Noticed number of transistors doubling with release of each newNoticed number of transistors doubling with release of each newIC generationIC generation

release dates (separate generations) were all 18-24 months apartrelease dates (separate generations) were all 18-24 months aparts Moores LawMoores Law::

The number of transistors on an integrated circuit will doubleThe number of transistors on an integrated circuit will doubleevery 18 monthsevery 18 months

s The level of integration of silicon technology as measured in terms of numberThe level of integration of silicon technology as measured in terms of numberof devices perof devices perICIC

s

This comes about in two ways size reduction of the individual devices andThis comes about in two ways size reduction of the individual devices andincrease in the chip or dice sizeincrease in the chip or dice sizes As an indication of size reduction, it is interesting to note that feature size wasAs an indication of size reduction, it is interesting to note that feature size was

measured in mils (1/1000 inch, 1 mil = 25 mm) up to early 1970s, whereasmeasured in mils (1/1000 inch, 1 mil = 25 mm) up to early 1970s, whereasnow all features are measured in mms (1 mm = 10now all features are measured in mms (1 mm = 10 -6-6 m or 10m or 10-4-4 cm)cm)

s Semiconductor industry has followed this prediction with surprising accuracySemiconductor industry has followed this prediction with surprising accuracy

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In 1965, Gordon Moore predicted that the number of transistors that can beIn 1965, Gordon Moore predicted that the number of transistors that can be

integrated on a die would double every 18 to 14 monthsintegrated on a die would double every 18 to 14 months i.e., grow exponentially with timei.e., grow exponentially with time

Amazing visionary million transistor/chip barrier was crossed in the 1980s.Amazing visionary million transistor/chip barrier was crossed in the 1980s.

2300 transistors, 1 MHz clock (Intel 4004) - 19712300 transistors, 1 MHz clock (Intel 4004) - 1971

42 Million, 2 GHz clock (Intel P4) - 200142 Million, 2 GHz clock (Intel P4) - 2001

140 Million transistor (HP PA-8500)140 Million transistor (HP PA-8500)

Moores LawMoores Law

Source: Intel web page (www.intel.com)

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Moores LawMoores Law

s From Intels 4040 (2300 transistors) to Pentium IIFrom Intels 4040 (2300 transistors) to Pentium II(7,500,000 transistors) and beyond(7,500,000 transistors) and beyond

Relative sizes of ICs in graph

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Ever since the invention of integrated circuit, the smallest feature size has beenEver since the invention of integrated circuit, the smallest feature size has been

reducing every year. Currently (2002) the smallest feature size is about 0.13reducing every year. Currently (2002) the smallest feature size is about 0.13

micron. At the same time the number transistors per chip is increasing due tomicron. At the same time the number transistors per chip is increasing due to

feature size reduction and increase in chip area. Classic example is the case offeature size reduction and increase in chip area. Classic example is the case of

memory chips: Gordon Moore of Intel in early 1970s found that: density (bits permemory chips: Gordon Moore of Intel in early 1970s found that: density (bits per

chip) growing at the rate of four times in 3 to 4 years - often referred to as Mooreschip) growing at the rate of four times in 3 to 4 years - often referred to as MooresLaw. In subsequent years, the pace slowed down a bit,Law. In subsequent years, the pace slowed down a bit, data density has doubleddata density has doubled

approximately every 18 months current definition of Moores Lawapproximately every 18 months current definition of Moores Law..

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Limits of Moores Law?Limits of Moores Law?

s Growth expected until 30 nm gate length (currently: 180 nm)Growth expected until 30 nm gate length (currently: 180 nm)

size halved every 18 mos. - reached insize halved every 18 mos. - reached in

2001 + 1.5 log2001 + 1.5 log22((180/30)((180/30)22) =) = 20092009

what then?what then?s Paradigm shift needed in fabrication processParadigm shift needed in fabrication process

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Technological Background of theTechnological Background of theMoores LawMoores Law

s To accommodate this change, the size of the siliconTo accommodate this change, the size of the siliconwafers on which the integrated circuits are fabricatedwafers on which the integrated circuits are fabricatedhave also increased by a very significant factor fromhave also increased by a very significant factor fromthe 2 and 3 in diameter wafers to the 8 inthe 2 and 3 in diameter wafers to the 8 in (200 mm) and(200 mm) and

12 in (300 mm) diameter wafers12 in (300 mm) diameter waferss The latest catch phrase in semiconductor technology (asThe latest catch phrase in semiconductor technology (as

well as in other material science) is nanotechnology well as in other material science) is nanotechnology usually referring to GaAs devices based on quantumusually referring to GaAs devices based on quantum

mechanical phenomenamechanical phenomenas These devices have feature size (such as film thickness,These devices have feature size (such as film thickness,line width etc) measured in nanometres or 10line width etc) measured in nanometres or 10-9-9 metresmetres

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Recurring CostsRecurring Costscost of die + cost of die test + cost of packagingcost of die + cost of die test + cost of packaging

variable cost =variable cost =--------------------------------------------------------------------------------------------------------------------------------

final test yieldfinal test yieldcost of wafercost of wafer

cost of die = -----------------------------------cost of die = -----------------------------------dies per waferdies per wafer die yielddie yield

(wafer diameter/2)2 waferdiameter

dies per wafer= ---------------------------------- ---------------------------die area 2 die area

die yield = (1 + (defects per unit area die area)/ )-

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Yield ExampleYield Example Example

q wafer size of 12 inches, die size of 2.5 cm2, 1 defects/cm2, = 3 (measure of manufacturing process complexity)

q 252 dies/wafer (remember, wafers round & dies square)

q die yield of16%

q 252 x 16% = only 40 dies/wafer die yield !

Die cost is strong function of die area

proportional to the third or fourth power of the die area

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Intel 4004 MicroprocessorIntel 4004 Microprocessor

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Intel Pentium (IV) MicroprocessorIntel Pentium (IV) Microprocessor

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Die Size GrowthDie Size Growth

4004

8008

80808085

8086286

386486 Pentium proc

P6

1

10

100

1970 1980 1990 2000 2010

Year

Diesize(mm

)

~7% growth per year

~2X growth in 10 years

Die size grows by 14% to satisfy Moores LawDie size grows by 14% to satisfy Moores Law

Courtesy, Intel

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Clock FrequencyClock Frequency

Lead microprocessors frequency doubles every 2 yearsLead microprocessors frequency doubles every 2 years

P6

Pentium proc486

3862868086

8085

8080

8008

40040.1

1

10

100

1000

10000

1970 1980 1990 2000 2010

Year

Frequency(M

hz)

2X every 2 years

Courtesy, Intel

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VLSIVLSI

s Very Large Scale IntegrationVery Large Scale Integration

design/manufacturing of extremely small, complex circuitrydesign/manufacturing of extremely small, complex circuitry

using modified semiconductor materialusing modified semiconductor material

integrated circuit (IC) may contain millions of transistors,integrated circuit (IC) may contain millions of transistors,

each a feweach a few m in sizem in size applications wide ranging: most electronic logic devicesapplications wide ranging: most electronic logic devices

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Origins of VLSIOrigins of VLSI

s Much development motivated by WWII need for improvedMuch development motivated by WWII need for improvedelectronics, especially for radarelectronics, especially for radar

s 1940 - Russell Ohl (Bell Laboratories) - first pn junction1940 - Russell Ohl (Bell Laboratories) - first pn junction

s 1948 - Shockley, Bardeen, Brattain (Bell Laboratories) -1948 - Shockley, Bardeen, Brattain (Bell Laboratories) -

first transistorfirst transistor 1956 Nobel Physics Prize1956 Nobel Physics Prize

s Late 1950s - purification of Si advances to acceptableLate 1950s - purification of Si advances to acceptable

levels for use in electronicslevels for use in electronics

s 1958 - Seymour Cray (Control Data Corporation) - first1958 - Seymour Cray (Control Data Corporation) - firsttransistorized computer - CDC 1604transistorized computer - CDC 1604

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Origins of VLSIOrigins of VLSI (Cont.)(Cont.)

s 1959 - Jack St. Claire Kilby (Texas Instruments) - first1959 - Jack St. Claire Kilby (Texas Instruments) - first

integrated circuit - 10 components on 9 mmintegrated circuit - 10 components on 9 mm22

s 1959 - Robert Norton Noyce (founder, Fairchild1959 - Robert Norton Noyce (founder, Fairchild

Semiconductor) - improved integrated circuitSemiconductor) - improved integrated circuit

s 1968 - Noyce, Gordon E. Moore found Intel1968 - Noyce, Gordon E. Moore found Intel

s 1971 - Ted Hoff (Intel) - first microprocessor (4004) - 23001971 - Ted Hoff (Intel) - first microprocessor (4004) - 2300

transistors on 9 mmtransistors on 9 mm22

s Since then - continued improvement in technology hasSince then - continued improvement in technology has

allowed for increased performance as predicted by Mooresallowed for increased performance as predicted by Moores

LawLaw

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Three Dimensional VLSIThree Dimensional VLSI

s The fabrication of a single integrated circuit whose functionalThe fabrication of a single integrated circuit whose functional

parts (transistors, etc) extend in three dimensionsparts (transistors, etc) extend in three dimensions

s The vertical orientation of several bare integrated circuits in aThe vertical orientation of several bare integrated circuits in a

single packagesingle package

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Advantages of 3D VLSIAdvantages of 3D VLSI

s Speed - the time required for a signal to travel between the functional circuitSpeed - the time required for a signal to travel between the functional circuit

blocks in a system (delay) reduced.blocks in a system (delay) reduced.

Delay depends on resistance/capacitance of interconnectionsDelay depends on resistance/capacitance of interconnections

resistance proportional to interconnection lengthresistance proportional to interconnection length

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Advantages of 3D VLSIAdvantages of 3D VLSI

s Noise - unwanted disturbances on a useful signalNoise - unwanted disturbances on a useful signal

reflection noise (varying impedance along interconnect)reflection noise (varying impedance along interconnect)

crosstalk noise (interference between interconnects)crosstalk noise (interference between interconnects)

electromagnetic interference (EMI) (caused by current in pins)electromagnetic interference (EMI) (caused by current in pins)s 3D chips3D chips

fewer, shorter interconnectsfewer, shorter interconnects

fewer pinsfewer pins

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Advantages of 3D VLSIAdvantages of 3D VLSI

s Power consumptionPower consumption

power used charging an interconnect capacitancepower used charging an interconnect capacitance

P = fCV2

power dissipated through resistive materialpower dissipated through resistive material

P = V2/R

capacitance/resistance proportional to lengthcapacitance/resistance proportional to length

reduced interconnect lengths will reduce powerreduced interconnect lengths will reduce power

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Advantages of 3D VLSIAdvantages of 3D VLSI

s Interconnect capacity (connectivity)Interconnect capacity (connectivity)

more connections between chipsmore connections between chips

increased functionality, ease of designincreased functionality, ease of design

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Advantages of 3D VLSIAdvantages of 3D VLSI

s Printed circuit board size/weightPrinted circuit board size/weight

planar size of PCB reduced with negligible IC height increaseplanar size of PCB reduced with negligible IC height increase

weight reduction due to more circuitry per package/smaller PCBsweight reduction due to more circuitry per package/smaller PCBs

estimated 40-50 times reduction in size/weightestimated 40-50 times reduction in size/weight

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3D VLSI - Challenges and Solutions3D VLSI - Challenges and Solutions

s Challenge: Thermal managementChallenge: Thermal management

smaller packagessmaller packages

increased circuit densityincreased circuit density

increased power densityincreased power density

s Solutions:Solutions:

circuit layout (design stage)circuit layout (design stage)

high power sections uniformly distributed

advancement in cooling techniquesadvancement in cooling techniques (heat pipes)(heat pipes)

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Influential Participants - IndustryInfluential Participants - Industry

s Mitsubishi, TI, Intel, CTS Microelectronics, Hitachi, Irvine Sensors, others...Mitsubishi, TI, Intel, CTS Microelectronics, Hitachi, Irvine Sensors, others...

high density memorieshigh density memories

s AT&TAT&T

high density multiprocessorhigh density multiprocessor

s Many other applications/participantsMany other applications/participants

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Three Dimensional VLSIThree Dimensional VLSI

s Moores Law approaching physical limitMoores Law approaching physical limit

s Increased performance expected by marketIncreased performance expected by market

s Paradigm shift needed - 3D VLSIParadigm shift needed - 3D VLSI

many advantages over 2D VLSImany advantages over 2D VLSI

economic limitations of fabrication overhaul will be overcome by market demandeconomic limitations of fabrication overhaul will be overcome by market demand

s Three Dimensional VLSI may be the savior of Moores LawThree Dimensional VLSI may be the savior of Moores Law