8086 Pins & Functions - WordPress.com · 8086 modes of operation •8086 can operate in two modes(MN/ 𝑋): • Minimum mode: In this mode 8086 processor works in a single processor

8086 Pins & Functions

By

Dr. Sikder Sunbeam Islam

Department of EEE

IIUC

8086 modes of operation

• 8086 can operate in two modes(MN/𝑀𝑋):

• Minimum mode: In this mode 8086

processor works in a single processor

environment. All control signals for

memory and I/O are generated by the

microprocessor.

• Maximum mode : When 8086 works in a

multiprocessor environment. Control

signals for memory and I/O are generated

by an external BUS Controller (e.g. Intel

8288)

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8086 modes of operation (continue)

• There are 40 pins in 8086

microprocessor. They are divided as:

Common Pins, Maximum Mode Pins

and Minimum Mode Pins.

• Out of 40 pins, 32 pins have same

function in minimum and maximum

mode.

• Remaining 8 pins having different

functions in minimum and maximum

mode.

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Pin Diagram of 8086

Maximum

mode

Minimum

mode

4

8086 Pins

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8086 Pin Functions(Common Pins)

Power supply

• It uses 5V DC supply at VCC pin 40, and uses ground at VSS pin 1

and 20 for its operation.

Clock signal

• Clock signal is provided through Pin-19. It provides timing to the

processor for operations.

• In microprocessor, a time to fetch and execute an entire instruction

is referred to as an ‘Instruction cycle’. An instruction cycle

consists of one or more ‘machine cycle’. Like, reading a byte from

memory is read machine cycle. Each cycle contains 4 T states

(periods).

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AD15-AD0 (Address/Data Bus) and ALE (Address latch enable)

• The 8086 address/data bus lines compose the multiplexed address/data bus on the 8086. These lines contains address bits when ALE=1 and data bits when ALE=0. ALE at pin number 25.

• AD0-AD7 carries low order byte data and AD8-AD15 carries higher order byte data. During the first clock cycle, it carries 16-bit address and after that it carries 16-bit data.

A19/S6 – A16/S3 (Address/ Status bus)

• Other 4 address lines (addresses are 20 bits) are the A16/S3, A17/S4, A18/S5 and A19/S6 (Multiplexed with status lines).

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8086 Pin Functions(Common Pins) A19/S6 – A16/S3 (Address/ Status bus)

Continue… • During the first clock period of bus cycle (read or write cycle), the entire 20-

bit address is available on these lines. During all other clock cycles for memory and I/O operations, AD15 – AD0 contain the 16 bit data and S3, S4, S5 and S6 become status lines. S3 and S4 lines are decoded as follows(during memory operation):

During I/O operation:

• A18/S5 and A19/S6 will stay low during the first clock period.

•During all other cycles, A18/S5 indicates the status of the 8086 interrupt

enable flag and A19/S6 become low, a low A19/S6 pin indicates that the

8086 is on the bus.

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𝑩𝑯𝑬/𝑺𝟕 (Bus High Enable) The 8086 outputs a low on this pin during read, write and interrupt

acknowledge cycles in which data are to be transferred in a high order byte (AD15-AD8) of the data bus. BHE can be used in conjunction with AD0 to select memory banks.

𝑹𝑫 (Read Signal, 32 no. pin)

•This pin is low (RD=0), the data bus receives (reads) data from the memory or I/O devices.

READY

•If READY =0 , the microprocessor enters into wait states and remains idle. The READY input is controlled to insert wait states into the timing of the microprocessor

•If the READY pin=1 , it has no effect on the operation of the microprocessor.

𝑻𝑬𝑺𝑻

•The 𝑻𝑬𝑺𝑻 pin is an input that is tested by the WAIT instruction.

•If 𝑇𝐸𝑆𝑇 is a logic 0, the wait instruction functions as a NOP and if 𝑇𝐸𝑆𝑇 is logic 1, the wait instruction waits for 𝑇𝐸𝑆𝑇 to become a logic zero.

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INTR (Pin 18)

Interrupt request is used to request a hardware interrupt. If INTR is held high when IF=1 the 8086 enters an interrupt acknowledge cycle (INTA becomes active).

NMI (Pin 17)

The Non-maskable interrupt input is similar to INTR except that the NMI interrupt does not check to see whether the IF flag bit is a logic 1. It is activated by leading edge. If NMI is activated, this interrupt input uses interrupt vector 2.

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RESET

The RESET input causes the microprocessor to reset itself if this pin is

held high for a minimum of four clocking period. It causes the 8086 to

initialize register DS, SS, ES, IP and flags to all zeros and CS to FFFFH.

MN/M͞X

The minimum/maximum mode pin selects either minimum mode or

maximum mode operation for the microprocessor. If minimum mode is

selected, the MN/M͞X pin must be connected directly to +5.0 V.

M/͞IO

• This pin selects memory or I/O.

• When the 8086 executes an I/O instruction such as IN or OUT, it outputs

a LOW on M/IO͞ .

• On the other hand, the 8086 outputs HIGH on the pin when it executes a

memory reference instruction such as MOV AX, [SI].

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8086 Pin Functions (Minimum Mode Pins ) ͞WR͞

When 𝑾𝑹 =0, the processor is performing a write memory or write

I/O operation depending on the M/𝑰𝑶 signal.

𝑰𝑵𝑻𝑨

• The interrupt acknowledge signal is a response to the INTR input pin.

• The 𝑰𝑵𝑻𝑨 pin is normally used to gate the interrupt vector number

onto the data bus in response to an interrupt request.

ALE (Address latch enable)

Used to multiplex the AD0-AD15 into A0-A15 (when ALE=1)and

D0-D15 (when ALE=0).

𝑫𝑻/𝑹 (Data Transmit/receive)

• The data transmit/receive signal shows that the microprocessor data

bus is transmitting (𝑫𝑻/𝑹 =1) or receiving (𝑫𝑻/𝑹 =𝟎) data.

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8086 Pin Functions (Minimum Mode Pins )

DEN (Data bus enable)

Data bus enable activates external data bus buffers. (e.g. Data bus buffer

of 8255A)

HOLD

• High on HOLD pin indicates that another master is requesting to take

over the system bus.

• The processor tri-states the system bus when receives Low on HOLD

pin.

HALDA (Hold Acknowledgement)

Hold acknowledgement (High) indicates that the 8086 has entered the

hold state.

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8086 Maximum Mode Pins(continue)

𝑺𝟐,𝑺𝟏,𝒂𝒏𝒅 𝑺𝟎

8086 Maximum Mode Pins 𝑺𝟐,𝑺𝟏, 𝒂𝒏𝒅 𝑺𝟎 The status bits indicate the function

of the current bus cycle. These signals are normally decoded by the 8288 bus

controller. Table shows the function of these three status bits in the maximum

mode.

𝑺𝟐 𝑺𝟏 𝑺𝟎 Function

0 0 0 Interrupt acknowledge

0 0 1 I/O Read

0 1 0 I/O Write

0 1 1 Halt

1 0 0 Opcode Fetch

1 0 1 Memory Read

1 1 0 Memory write

1 1 1 Passive

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𝐑𝐐/𝐆𝐓𝐈 and 𝐑𝐐/𝐆𝐓𝟎

• The request/grant pins request direct memory accesses (DMA) during

maximum mode operation. These lines are bidirectional and are used to

both request and grant a DMA operation.

• [DMA: Direct memory access normally occurs between an I/O device and

memory without the use of microprocessor.]

The request /grant function of 8086 works as follows-

• A pulse (one clock wide) from another local bus master (𝐑𝐐/𝐆𝐓𝐈 and 𝐑𝐐/𝐆𝐓𝟎 pins) indicates a local bus request to 8086.

• At the end of 8086 current bus cycle, a pulse from 8086 to the requesting

master indicates that 8086 has relinquish the system bus and tri-states the

output. Then the new bus master sub sequently relinquishes the control of

the system bus by sending a low on 𝐑𝐐/𝐆𝐓𝐈 and 𝐑𝐐/𝐆𝐓𝟎 pins. The

8086 then regain the bus control.

•

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QS1 and QS0

The 8086 outputs to QS1 and QS0 pins to provide status to allow

external tracking of the internal 8086 instruction queue as follows-

QS1 QS0 Function

0 0 No operation

0 1 First byte of opcode from queue

1 0 Empty the queue

1 1 Subsequent byte from queue

𝑳𝑶𝑪𝑲

• The 8086 outputs LOW on the 𝐿𝑂𝐶𝐾 pin to prevent other bus

masters from gaining control of the system bus.

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Clock Generator (8284A): Pin functions (Cont.)

The 8284A provides the following basic

functions or signals:

•Clock Generation.

•RESET synchronization.

•READY synchronization and

•A TTL level peripheral clock signal.

Pin Functions: The 8284A is an 18-pin integrated circuit

designed specially for use with the 8086/8088

microprocessor. The following is a list of each

pin and its function.

The address enable pins are provided to qualify the bus ready signals, RDY1 and

RDY2, respectively. Wait states are generated by the READY pin of the

8088/8086 microprocessor, which is controlled by these two pins. 17


The bus ready inputs are provided from a device located on the system data

bus, in conjunction with the AEN1 and AEN2, pins, to cause wait state in

an 8086/8088- based system.

READY

READY is an output pin that connects to the 8086/8088 READY input.

This signal is synchronized with the RDY1 and RDY2 inputs.

Ready synchronization selection input selects either one or two stages of

synchronization for the RDY1 and RDY2 inputs. When it is low, two stages

of ready synchronization are provided. When it is high, a stage of ready

synchronization is provided.

The crystal oscillator pins connect to an external crystal used as the timing

source for the clock generator and all its functions.

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F/C

Frequency/Crystal select input chooses the

clocking source for the 8284A. If this pin is

high, clock is supplied from external source

connected to EFI pin. If this pin is low, clock is

supplied from crystal oscillator.

EFI

External frequency input is an input pin to provide

external clock pulse for the 8086/8088

microprocessor. The input external clock should be

three times greater than the desired output clock.

CLK

The clock output pin provides the CLK input signal to the 8086/8088

microprocessor and other components in the system. The CLK has an output

signal that is one-third of the crystal or EFI input frequency, and has a 33% duty

cycle, which is required by the 8086/8088.

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The reset output is connected to the 8086/8088 RESET input pin.

The reset input is an active low input to the 8284A which is used to

generate RESET signal of microprocessor.

The PCLK (peripheral clock signal ) output provides a clock signal to the

peripheral equipment in the system.

OSC The OSC output provides an EFI input to other 8284A clock generators

in some multiple processor system.

CSYNC

The clock synchronization pin is used whenever the EFI input provides

synchronization in systems with multiple processor.

VCC and GND GND is connected to ground and Vcc to +5V with tolerance of ±10%

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Thank You

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8086 Pins & Functions - WordPress.com · 8086 modes of operation •8086 can operate in two modes(MN/ 𝑋): • Minimum mode: In this mode 8086 processor works in a single processor