8086 Interfacing-chap 5

8/18/2019 8086 Interfacing-chap 5

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8086 INTERFACING

DK DEPT OF TCE, APSCE Page 1

8086 INTERFACING.DIFFERENCE BETWEEN 8088 AND 8086

8088

1. has 8 bit data bus and thus, 8 bit ALU.2. The address bus A8-A15 is notmultiplexed and hence no need to belatched.3. Since the data is only 8 bit, the memoryis not organized into lower and higher banks and hence the signal BHE is notrequired.4. For word operation, the memory isaccessed twice. Thus there is increase inexecution time.

5. The size of instruction queue is 4 bytes.6. The data through data bus is bufferedusing 1 transceiver (bidirectional buffers).7. Memory or IO device is identified byIO/M bar signal.8. BHE pin is not present, instead the pin isnamed as SS0 bar

8086

1. has 16 bit data bus and hence 16 bitALU.2. The higher order data bus is multiplexedwith address lines (AD8-AD15)3. To realize 16 bit data, the externalmemory is organized into lower and higher banks. These banks are selected using A0and BHE respectively.4. If the address is even, 16 bit data can beaccessed in 1 bus cycle.5. The size of instruction queue is 6 bytes.

6. The data through data bus is bufferedusing 2 transceivers (bidirectional buffers)7. The corresponding signal is M/IO bar.

8. BHE is used to select higher bank of thememory.

DELAY CALCULATION

clock cycles requiredmov cx, count 4

back: dec cx 2 jnz back 16/4

Total clock cycles required to execute the given program:1

st instruction----- 4 clk cycles

in loop, 2nd & 3rd instructions---------- (count – 1)(2 + 16) clk cycleslast loop--------------- (2 + 4) clk cycles= 4 + 2(count) + 16(count – 1) +4 = [18(count)-8] clk cycles

Number of required clk cycles=cycleclk1fortime

delay timeRequired

count=18

8+cycleclkrequired

Let clock frequency= 10MHz, i.e. time period= 0.1 μs. Total time= [18(count)-8]X(0.1μs)In the above eg, [18(count)-8](0.1 X 10-6 s) = 20 X 10-3 s18(count)-8= 200000, count= 200008/ 18= 11112 = 2B68H


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TIMER DELAY USING NESTED LOOP

mov bx, c1 loop1: mov cx, c2 loop2: dec cx

jnz loop2dec bx jnz loop1

Total clock cycles required to execute the given program:4+4c1+[2c2+(c2-1)16+4]c1 +2c1+(c1-1)16+4= 18c1c2+10c1-8

If c1=50, c2=100, Total clock cycles required = 18c1c2+10c1-8 = 18(100)(50)+10(50)-8=90492Total time= 90492 X 1μs=90.492 ms

DIFFERENT METHODS OF INTERFACING I/O DEVICES

I/O mapped I/O (Isolated I/O): It is the most common I/O data transfer technique. Theterm isolated indicates that the I/O locations are isolated from the memory system in aseparate I/O address space. The address for the I/O ports is separate from the memory andis 8 or 16 bit. It is 8 bit for direct addressing, and 16 bit for indirect (variable) addressing.

Separate control signals for I/O read and I/O write are generated, 0/,, = IO M WR RD in

minimum mode configuration of 8086 and IOWC IORC , generated by 8288 in maximum

mode configuration of 8086. Maximum number of I/O devices that can be connected are256 for direct and 65536 for indirect addressing. This scheme requires decoding of 8 or16 address lines and hence comparatively less hardware is required. Memory can beexpanded to its full size but the disadvantage of this scheme is that data is transferred between 8086 and I/O device only by IN and OUT instructions.Memory mapped I/O: In this scheme, the address of I/O devices is 20 bits and isconnected as if it is a memory location. Any instruction that transfers data between 8086and memory can be used for transferring data between 8086 and I/O devices. The samecontrol signals used for accessing the memory are used for accessing the I/O devices,

1/,, = IO M WR RD in minimum mode configuration of 8086 and MWTC MRDC ,

generated by 8288 in maximum mode configuration of 8086. Theoretically, maximumnumber of I/O devices that can be accessed is 1M byte. This scheme requires decodingof 20 address lines and hence more hardware is required. The main disadvantage of this

scheme is that a portion of memory is used as the I/O map. This reduces the amount ofmemory available forapplications.

(Generation of IOR andIOW in minimum mode)


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DIFFERENCE BETWEEN I/O MAPPED I/O AND MEMORY MAPPED I/O

DEVICES

I/O mapped I/O (Isolated I/O)

1. The address for the I/O ports is separatefrom the memory and is 8 or 16 bit. It is 8 bit for direct addressing, and 16 bit forindirect (variable) addressing.2. In this IN and OUT instructions are usedto transfer data through I/O ports.3. I/O device is activated or selected when

IO M

/ is low.4. Number of I/O devices that can beconnected are 256 for direct and 65536 forindirect addressing.5. This scheme requires decoding of 8 or16 address lines and hence comparativelyless hardware is required.

Memory mapped I/O

1. In this scheme, the address of I/Odevices is 20 bits and is connected as if it isa memory location.

2. All memory related instructions can beused to access I/O device.3. I/O device is activated or selected when

IO M

/ is high.4. Maximum number of I/O devicesconnected can be 1M theoretically.

5. This scheme requires decoding of 20address lines and hence more hardware isrequired.

PROGRAMMABLE PERIPHERAL INTERFACE (PPI) 8255

The parallel input-output port chip 8255 is also called as programmable peripheral input- output port. The Intel’s 8255 is designed for use with Intel’s 8- bit, 16-bit and highercapability microprocessors.It has 24 input/output lines which may be individually programmed in two groups oftwelve lines each, or three groups of eight lines.The two groups of I/O pins are named as Group A and Group B. Each of these twogroups contains a subgroup of eight I/O lines called as 8-bit port and another subgroup offour lines or a 4-bit port. Thus Group A contains an 8-bit port A along with a 4-bit port Cupper.


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The port A lines are identified by symbols PA0-PA7 while the port C lines are identifiedas PC4-PC7. Similarly, Group B contains an 8-bit port B, containing lines PB0-PB7 anda 4-bit port C with lower bits PC0- PC3. The port C upper and port C lower can be usedin combination as an 8-bit port C.Both the port C are assigned the same address. Thus one may have either three 8-bit I/O ports or two 8-bit and two 4-bit ports from 8255. All of these ports can function

independently either as input or as output ports. This can be achieved by programmingthe bits of an internal register of 8255 called as control word register ( CWR ).It has a 40 pins of 4 groups.

1. Data bus buffer2. Read Write control logic3. Group A and Group B controls4. Port A, B and C

Data bus buffer: This is a tristate bidirectional buffer used to interface the 8255 tosystem databus. Data is transmitted or received by the buffer on execution of input oroutput instruction by the CPU. Control word and status information are also transferredthrough this unit.

Read/Write control logic: This unit accepts control signals (RD, WR) and also inputsfrom address bus and issues commands to individual group of control blocks (Group A,Group B).It has the following pins:

a) CS – Chip select: A low on this PIN enables the communication between CPUand 8255.b) RD (Read) – A low on this pin enables the CPU to read the data in the ports orthe status word through data bus buffer.c) WR (Write): A low on this pin, the CPU can write data on to the ports or on tothe control register through the data bus buffer.d) RESET: A high on this pin clears the control register and all ports are set to the

input modee) A0 and A1 (Address pins ): These pins in conjunction with RD and WR pinscontrol the selection of one of the 3 ports.

Group A and Group B controls : These block receive control from the CPU and issuescommands to their respective ports.

Group A - PA and PCU ( PC7 –PC4)Group B - PCL ( PC3 – PC0)

Control word register can only be written into no read operation of the CW register isallowed.

a) Port A: This has an 8 bit latched/buffered O/P and 8 bit input latch. It can be programmed in 3 modes – mode 0, mode 1, mode 2.

b) Port B: This has an 8 bit latched / buffered O/P and 8 bit input latch. It can be programmed in mode 0, mode1.c) Port C : This has an 8 bit latched input buffer and 8 bit out put latched/buffer.This port can be divided into two 4 bit ports and can be used as control signals for port A and port B. it can be programmed in mode 0.


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BLOCK DIAGRAM

CONTROL WORD


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PIN DETAILS

This buffer receives or transmits data upon the execution of input or output instructions by the microprocessor. The control words orstatus information is also transferred through the

buffer.The signal description of 8255 is briefly presented as follows:

PA7-PA0: These are eight port A lines that

acts as either latched output or buffered inputlines depending upon the control word loadedinto the control word register.PC7-PC4: Upper nibble of port C lines. They

may act as either output latches or input bufferslines. This port also can be used for generation

of handshake lines in mode 1 or mode 2.PC3-PC0: These are the lower port C lines,other details are the same as PC7-PC4 lines.PB0-PB7: These are the eight port B lines

which are used as latched output lines or buffered input lines in the same way as port A.

RD: This is the input line driven by the microprocessor and should be low to indicateread operation to 8255.WR: This is an input line driven by the microprocessor. A low on this line indicateswrite operation.CS: This is a chip select line. If this line goes

low, it enables the 8255 to respond to RD and WRsignals, otherwise RD and WR signal areneglected.A1-A0: These are the address input lines and

are driven by the microprocessor. These addresslines are used for addressing any one of the fourregisters, i.e. three ports and a control wordregister. In case of 8086 systems, if the 8255 is to be interfaced with lower order data bus, the A0and A1 pins of 8255 are connected with A1 andA2 respectively.

D0-D7: These are the data bus lines those carrydata or control word to/from the microprocessor.RESET: A logic high on this line clears the

control word register of 8255. All ports are set asinput ports by default after reset.


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MODE 1

MODE 1 INPUT


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MODE 1 OUTPUT


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MODE 2


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MODE SUMMARY

STATUS WORD


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MODE 1 STATUS WORD

MODE 2 STATUS WORD

INTERFACING A MICROPROCESSOR TO KEYBOARDS

KEYBOARD TYPES

1. MECHANICAL KEY SWITCHES:

When key is pressed, two pieces of metal are pushed together. The actual switch elements

are often made of a phosphor bronze alloy with gold plating on the contact areas. The keyswitch usually contains a spring to return the key to the non pressed position and perhapsa small piece of foam to help damp out bouncing. Some mechanical key switches nowconsist of a molded silicone dome with a small piece of conductive rubber on theunderside. When a key is pressed, the rubber foam shorts two traces on the printed circuit board to produce the key pressed signal. Higher quality mechanical switches typicallyhave a rated lifetime of about 1 million keystrokes. The silicone dome type typically last25 million keystrokes.


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Disadvantages: They suffer from contact bounce.A pressed key may make and break contactseveral times before it makes solid contact. Thecontacts may become oxidized or dirty with age,so they no longer make a dependable connection.

2. MEMBRANE KEYSWITCHES:These are a special type of mechanical switch.They consist of a three layer plastic or rubbersandwich. The top layer has a conductive line ofsilver ink running under each row of keys. Themiddle layer has a hole under each key position.The bottom layer has a conductive line of silverink running under each column of keys. Whenkey is pressed, it pushes the top ink line throughthe hole to contact the bottom ink line.

Advantage: They can be made as very thin,sealed units.

3. CAPACITIVE KEY SWITCHES:It has 2 small metal plates on the printed circuit board and another metal plate on the bottom of a piece of foam. When key is pressed, the movable plate is pushed closer to thefixed plate. This changes the capacitance between the fixed plates. Sense amplifiercircuitry detects this change in capacitance and produces a logic level signal thatindicates a key has been pressed.Advantage: These have a rated lifetime of about 20 million keystrokes.Disadvantages: Specialized circuitry is needed to detect the change in capacitance.

4. HALL EFFECT KEY SWITCHES:It takes advantage of the deflection of a moving charge by amagnetic field. A reference circuit is passed through asemiconductor crystal between two opposing faces. When akey is pressed, the crystal is moved through a magnetic fieldwhich has its flux lines perpendicular to the direction of currentflow in the crystal. Moving the crystal through the magneticfield causes a small voltage to be developed between two of theother opposing faces of the crystal. This voltage is amplifiedand used to indicate that a key has been pressed.

Disadvantage: Hall Effect keyboards are more expensive because of the more complex switch mechanismAdvantage: They are very dependable and have typical ratedlifetime of 100 million or more keystrokes.

KEYBOARD CIRCUIT CONNECTIONS AND INTERFACING

In most keyboards, the key switches are connected in a matrix of rows and columns.Getting meaningful data from a keyboard requires 3 major tasks.


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1. Detect a key pressed.2. Debounce the key pressed3. Encode the key pressed (produce a standard code for the pressed key)

The three tasks can be done with hardware, software or a combination of both dependingon application.

DEBOUNCER CIRCUIT

A key is a type of push button switch, toggle switch, or electromechanical relay, havingspring contacts. Whenever a mechanical push-button is pressed or released once, themechanical component of the key do not change the position smoothly, rather, itgenerates a transient response. These transient variations may be interpreted as themultiple key pressures and responded accordingly by the microprocessor system.

To avoid this problem, there are two schemes:1. HARDWARE DEBOUNCING METHOD: A bistable multivibrator or a latch is

used at the output of the key debounce.In the above circuit, output of flipflop is logic 1 when key is at position A(unpressed) and logic 0 when key is at position B. When key is between A and B,

output does not change, preventing bouncing of key output. Thus output does notchange during transition period, eliminating key bouncing.2. SOFTWARE DEBOUNCING METHOD: The microprocessor should be made to

wait for transient period so that transient response settles down and reaches steadystate.


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SOFTWARE KEYBOARD INTERFACING

Hexadecimal keypad can be connected to acouple of microcomputer ports. Rows of thematrix are connected to 4 output port lines.Column lines of the matrix are connected to

4 input port lines. Row lines are alsoconnected to 4 input lines.When no keys are pressed, the column linesare held high by the pull up resistorsconnected to +5V. Pressing a key connect arow to a column. If a low is output on a rowand a key in that row is pressed, then thelow will appear on the column whichcontains that key and can be detected on theinput port.

In the algorithm, first output lows to all therows and check the columns over and overuntil the columns are all high. This is doneto make sure that previous key has beenreleased before looking for the next one.This is called two-key lock out.


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pressed

in al, dxand al, 0fhcmp al, 0fh je wait_press

pop bx popfretkeybrd endpend

Q. Interface a 4 * 4 keyboard with 8086 using 8255 and write an ALP for detecting a

key closure and return the key code in AL. The debounce period for a key is 10ms.

Use software debouncing technique. The address of port A and port B will

respectively 8000H and 8002H while address of CWR will be 8006H.

ADDRESS A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

PORT A 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PORT B 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0

PORT C 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0

CWR 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0


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.model small

.data pa dw 8000h pb dw 8002h

pc dw 8004hcr dw 8006h.code.startupmov dx, crmov al, 82h ; port A o/p, port B i/pout dx, al

mov bl, 0xor ax, ax

mov dx, paout dx, al

mov dx, pbwait: in al, dxand al, 0fhcmp al, 0fh jz wait

call debounce

mov al, 7fh ; to activate a row, send 0mov bh, 4 ; set row counternxtrow: rol al, 1mov ch, almov dx, paout dx, pamov dx, pbin al, dxand al, 0fhmov cl, 4 ; set column counternxtcol: ror al, 1

jnc codekey ; key closure is found when CF=0inc bl ; increment bl for next binary key codedec cl

jnz nxtcolmov al, chdec bh

jnz nxtrow


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jmp waitcodekey: mov al, bl.exitdebounce proc nearmoc cl, count ; count=0e2h back: nop

dec cl jnz backretdebounce endp

end

Q. Scan the 4x4 keypad for key closure and to store the code of the key pressed in a

memory location or display on the screen. Also display row and column numbers of

the key pressed.

(In the given program, one row is enabled by sending logic 1 through port C. If a key is pressed logic 1 is read through port A.)

LAB PROGRAM (no. of rows=4, no. of

columns=4)

disp macro msglea dx, msgmov ah, 09hint 21hendm

.model small

.stack

.data pa equ ___; address of port A pb equ __; address of port B pc equ ____; address of port Ccr equ__; address of control registercw equ 90h; port A i/p, port C o/p

m1 db 13,10,'entered key is:','$'m2 db 13,10,'row number is:','$'

m3 db 13,10,'column number is:','$'m4 db 13,10,'press c to continue:','$'

row db ?col db ?

.codestart1:mov ax, @data

mov ds, ax

SIMPLE PROGRAM TO READ KEY

PRESSED IN MEMORY

.model small.stack.data pa equ ___; address of port A pb equ __; address of port B pc equ ____; address of port C

cr equ__; address of control registercw equ 90h; port A i/p, port C o/prow db ?col db ?key db ?

.codestart1:mov ax, @data

mov ds, ax

mov al,cw

mov dx, crout dx, al

start: mov al, 80hmov row, 1mov col, 1mov ch, 0mov bl, 4


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mov al,cwmov dx, crout dx, al

start: mov al, 80h

mov row, 1mov col, 1mov ch, 0mov bl, 4

nextrow: rol al, 1mov bh, almov dx, pcout dx, al ; enable one rowmov cl, 4mov dx, pa

in al, dx

nextcol: ror al, 1 jc displayinc chinc coldec cl jnz nextcolmov col, 1

inc row

mov al, bh

dec bl jnz nextrow

x: jmp start

display:disp m1mov dl, chcmp dl, 0ah jc digitadd dl, 07h

digit: add dl, 30hmov ah,2int 21hadd row, 30hadd col, 30h

disp m2

nextrow: rol al, 1mov bh, almov dx, pcout dx, al ; enable one rowmov cl, 4

mov dx, pain al, dx

nextcol: ror al, 1 jc displayinc chinc coldec cl jnz nextcolmov col, 1

inc rowmov al, bh

dec bl jnz nextrow

display:mov key, ch

mov ah, 4chint 21h

end


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mov dl, rowmov ah, 2int 21h

disp m3mov dl, col

mov ah, 2int 21h

disp m4mov ah, 8int 21hcmp al, 'c' jz x

mov ah, 4chint 21h

end

INTERFACING TO ALPHANUMERIC DISPLAYS

Seven segment displays consists of eight LED segments and are available in a singledual-in-line package (DIP). There is one pin for each segment named from ‘a’ to ‘g’ andanother LED for decimal point (‘dp’ or h). One pin for power supply is available.

There are two types of seven segment displays- common cathode and common anode.In common anode type of display, the anodes of all the LEDs is connected together. To

illuminate a segment, the common anode is connected to power supply and segmentinputs ‘a’ to ‘g’ is connected to logic 0 or low-level voltage.In common cathode type of display, the cathodes of all the LEDs is connected together.To illuminate a segment, the common cathode is connected to ground and segment inputs‘a’ to ‘g’ is connected to logic 1 or high-level voltage. This forward biases the LEDs andilluminates them.


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DIRECTLY DRIVING LED DISPLAYS (STATIC DISPLAY)

The BCD to seven segmentdisplay decoder IC 7447converts 4-bit BCD codeapplied at its input into the patterns required to displaythe BCD number in a seven

segment LED. The patternsgenerated are active lowoutputs, i.e. logic 0 is given asoutput. To illuminate theseven segment LEDs,common anode display is

suitable for use with IC 7447. This circuit connection is referred to as static display because current is being passed through the display at all times.


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Each segment requires a current between 5 to 30mA to light the LED.Assume current = 20mA.Drop across LED when lit= 1.5VThe o/p low voltage for 7447 is a maximum of 0.4V at 40mAFor 20mA, drop= 0.2V

Voltage across current limiting resistor= 5-1.5-0.2= 3.3V = IR

Ω== 16820

3.3

mA

V R (Standard value= 220Ω)

This scheme has problem when more displays need to be used.

1. Power consumption is moreIf 8 seven segment displays are connected and all are LEDs are glowing. Totalcurrent= 7 LEDs X 8 displays X 20mA = 1.12A

2. Second problem of the static approach is that each display digit requires a

separate 7447 decoder, each of which uses 13mA (assume). The current used bydecoders and LED displays will be several times the current required by the restof the circuitry in the instrument.

To solve the problems of static display approach, multiplex method is used.

Q. Assume the port addresses 40h, 42h, 44h and 46h assigned to port a, b, c and

control register of 8255, respectively. Write a program to display the data ‘7’ in the

seven segment display.

.model small

.data

pa equ 40h pb equ 42h pc equ 44hcr equ 46hcw equ 80h; port A is output port..code.startupmov al, cwout cr, almov al, 07h

out pa, al.exitend


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MULTIPLEXED DISPLAY

4 seven segment LED displays are connected. Common anode type LEDs are used (Logic0 to the segment indicates it is enabled or ON). Anodes of the seven segment displays areconnected to +5V through transistors. Cathodes are connected in parallel and then to o/pof 7447 IC through resistors.

In multiplexed display, segment information is sent to all seven segment displays through

same lines, but only one seven segment is turned ON at a time. The PNP transistorsconnected in series with common anode of each seven segment act as an ON and OFFswitch for that display. If a low (logic 0) is sent through port B to the base of a particularPNP transistor, that transistor would turn ON and connect the common anodes of thatseven segment display to +5V. The segment information sent from port A through 7447IC would then be displayed on the selected display unit.After a certain delay (say 2ms), the digit being displayed in turned OFF and then nextdigit segment information is sent through port A and next PNP transistor is turned ON.This process is continued.


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Q. Interface an 8255 with 8086 at 80h as an I/O address of port A. Interface five 7

segment displays with 8255. Write a sequence of instructions to display 1, 2, 3, 4, 5

over the five displays continuously as per their positions starting with 1 at the least

significant position.

In the above diagram, NPN transistors are used. The seven segment displays are commoncathode type. Logic 1 or active high to the base of transistor turns it ON.ADDRESS A7 A6 A5 A4 A3 A2 A1 A0

PORT A 80h 1 0 0 0 0 0 0 0PORT B 82h 1 0 0 0 0 0 1 0

PORT C 84h 1 0 0 0 0 1 0 0

CWR 86h 1 0 0 0 0 1 1 0

Logic 1 to the segment indicates it is enabled or ON (common cathode type display)

.model small

.data pa equ 80h pb equ 82h pc equ 84hcr equ 86h


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cw equ 80h ; port A and port B as o/p portstable db 0cfh, 92h, 86h, 0cch, 0a4h.code.startupagain: lea bx, table

mov cl, 5

mov ch, 1 ; 1st

number to be dispalyedmov al, cwout cr, al

mov dl, 1 ; enable code for least significant 7-seg displaynxtdgt: mov al, ch

xlatout pa, almov al, dlout pb, alrol dl

inc chdec cl jnz nxt dgt jmp again

.exitend

Q. Display messages APSC with flickering effects on a 7 segment display

interface for a suitable period of time. Ensure a flashing rate that makes it

easy to read both the messages.

For the program below, a non multiplexed seven segment display interfacing is provided by a set of shift registers and their corresponding common anode seven segment display.


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.model small

.data pa equ 20c0h ; ADDRESS OF PORT A pb equ 20c1h; ADDRESS OF PORT B pc equ 20c2h; ADDRESS OF PORT Ccr equ 20c3h; ADDRESS OF CONTROL REGISTER

first db 0C6H, 92H, 8CH, 88H

.code begin: mov ax, @data

mov ds, ax

mov al, 80hmov dx, crout dx, al

mov cx, 05h

next: lea si, firstcall flashcall delaycall delay

loop next

mov ah, 4chint 21h

flash proc near push cx push bxmov cx, 04h

loop1: mov bl, 08hmov al, [si]

loop2: rol al, 1mov dx, pbout dx, al push ax

mov dx, pcmov al, 0ffhout dx, almov al, 00hout dx, al

pop axdec bl jz next1


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jmp loop2

next1: inc siloop loop1 pop bx pop cx

retflash endp

delay proc near push cx push bxmov cx, 08fffh

l1: mov bx, 0fffhl2: dec bx

jnz l2loop l1

pop bx pop cxretdelay endp

end

Q. With necessary hardware and software, show an interface of seven segment led

display to 8086 processor. Port A provides the segment data input to the display and

port B provides a digit driver code function selecting a particular seven segment

display. Display ‘good’.

Common anode type of LEDs is used in the above multiplexed display. Port A outputsthe data to be displayed and port B outputs data to select one seven segment display. PNP


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modes will result in full stepping, but the full step positions are shifted one half of a fullstep.Half stepping:If these two drive modes are combined and correct sequences are fed into the windingsthe rotor can be made to align at all positions i.e. 1, 2, 3, 4, and so on. This is referred toas “half step mode”

The main advantage of half-step is the increased resolution. The main disadvantage ofhalf step operation is that in the half-step state the motor has only about 70% of thetorque as when driven to the full-step state. This is the direct result of lower flux densityin the stator. In the full-step state the magnetic vector generated by the stator is the vectorsum of the magnetic vectors of the two coils. When both coils are excited evenly, thevector sum of the two is at a 45° angle and has a magnitude of √2 times the magnitude ofeach individual vector. When only one coil is driven, as in the half-step states, the totalmagnetic vector is only the vector for one coil. This results in a 30% reduction in torquefor the half-steps. The reduction in torque can be compensated for by increasing thecurrent in the one driven coil for the half-steps.

A stepper motor is a special motor that rotates in incremental steps, unlike other motorsthat run continuously. They find application in printers, plotters, robots, etc. They areexcited by pulses to get incremental displacements. The common step size of steppermotor ranges from 0.9 to 30 degrees. They are made of permanent magnet rotors withstatic field excitation. Two phase excitation and four phase excitation are common. A 4- phase motor has 4 stator poles, which are excited by pulses. Each pole winding can beexcited such that the pole can be made either North Pole or a south pole. The number ofteeth or number of poles in the rotor will decide the minimum incremental step anglewhen a particular phase is excited. In this arrangement, the poles should be properlyexcited in a particular sequence so that the rotor rotates in a particular direction. If the


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excitation is reversed, the rotor rotates in the reverse direction. A typical stepper motorhas a step angle of 1.8 degrees. This motor has 50 teeth on rotor and 8 poles on stator.

The interfacing of 4-phase stepper motor to8086 through the 8255 is shown. The steppermotor has six terminals- 4 terminals A, B, C,D for excitation and two more terminals for power supply. The 4 terminals A, B, C, D areconnected to 8255 ports through transistordrivers. The transistor drivers or buffers areessential as the port pins cannot directly sourcethe current required for the motor drive. Themotor terminals have to be excited in a propersequence so that the rotor rotates continuously

in one direction. Two types of excitations are possible with 4-phase motor- one-phaseexcitation (only one phase of the stepper motor is excited at a time) and two-phaseexcitation (two phases are excited at a time). The exciting sequence is fixed for a rotationin a particular direction. The excitation sequence for the interface diagram shown is in thetable below. The table also shows hexadecimal values to be given to port A assuminghigher order 4 bots of the data are zero.

WAP to drive the stepper motor continuously at 60 rpm. Assume the addresses 80H,

82H, 84H and 86H are assigned to port A, B, C and Control register of 8255

respectively.


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1 minute= 60 seconds-------------N revolutions1 second----------------------------- N/60 revolution

1 revolution (=360 degrees) ----------------------60/ N second1.8 degrees-------------------------------------------- 60 X 1.8/360N = 0.3/N second

For N=60, time delay= 0.3/60= 5ms


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WAP to drive the stepper motor by 180 degrees. Assume the addresses 80H, 82H,

84H and 86H are assigned to port A, B, C and Control register of 8255 respectively.

The motor coils have to be excited by two-phase excitation method and for anti-

clockwise rotation.


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Full step excitation:

1 coil excitation: 01h, 02h, 04h, 08h

2 coil excitation: 03h, 06h, 0ch, 09hHalf step mode: combine both the excitations

03h, 01h, 06h, 02h, 0ch, 04h, 09h, 08h

WAP to rotate stepper motor for 270 degrees in anticlockwise direction 1.8 degrees-------- 1 step360 degrees ------- 200 steps270 degrees-------150 steps

.model small.data

pa equ _________ ; ADDRESS OF PORT A pb equ _________; ADDRESS OF PORT B pc equ _________; ADDRESS OF PORT Ccr equ _________; ADDRESS OF CONTROL REGISTER

.codemov dx, crmov al, 80hout dx, almov cx, 150mov dx, pcmov al, 88h

l1: out dx, alcall delayrol al, 1loop l1mov ah, 4chint 21h

delay proc near


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push cxmov cx, 0fffh

l2: mov bx, 0fffhl3: dec bx

jnz l3loop l2

pop cxretdelay endpend

WAP to rotate stepper motor in clockwise direction 5 rotations

1 rotation---360 degrees-----200 steps5 rotations----------------------1000 steps

.model small.data

pa equ _________ ; ADDRESS OF PORT A pb equ _________; ADDRESS OF PORT B pc equ _________; ADDRESS OF PORT Ccr equ _________; ADDRESS OF CONTROL REGISTER

.codemov dx, crmov al, 80hout dx, almov cx, 1000mov dx, pc

mov al, 88h

l1: out dx, alcall delayrol al, 1 ;for anticlockwiseloop l1

mov cx, 1000mov dx, pcmov al, 88h

l2: out dx, alcall delayror al, 1 ; for clockwiseloop l2mov ah, 4chint 21h

delay proc near push cx


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mov cx, 0fffhl2: mov bx, 0fffhl3: dec bx

jnz l3loop l2

pop cxretdelay endp

end

WAP to drive the stepper motor continuously at 60 rpm. 1 minute= 60 seconds-------------N revolutions1 second----------------------------- N/60 revolution

1 revolution (=360 degrees) ----------------------60/ N second

1.8 degrees-------------------------------------------- 60 X 1.8/360N = 0.3/N second

For N=60, time delay= 0.3/60= 5ms. Calculate the delay for 5ms

WAP to rotate a motor for 64 degrees in clockwise direction. The motor has step

angle of 2 degrees. Use 4 step sequence (2 coils ON at same time) 2 degrees-------- 1 step360 degrees ------- 180 steps64 degrees-------32 stepsfor movement of 64 degrees, send 8 consecutive 4 step sequences i.e 32 steps.Excitation: 03h, 06h, 0ch, 09h

WAP to rotate a motor for 180 degrees in anticlockwise direction. The motor has

step angle of 1.8 degrees. Use 4 step sequence (2 coils ON at same time) 1.8 degrees-------- 1 step360 degrees ------- 200 steps180 degrees-------100 stepsfor movement of 180 degrees, send 25 consecutive 4 step sequences i.e 100 steps.Excitation: 09h, 0ch, 06h, 03h

Write an algorithm and program for 8086 procedure to drive the stepper motor.

Assume the desired direction of rotation is passed to the procedure in AL (AL=1 isclockwise, AL=0 is counter clockwise) and the number of steps is passed to the

procedure in CX. Also assume full step mode and delay of 20ms between each step.

.model small.data

pa equ _________ ; ADDRESS OF PORT A pb equ _________; ADDRESS OF PORT B pc equ _________; ADDRESS OF PORT C


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cr equ _________; ADDRESS OF CONTROL REGISTER

.codemov dx, crmov al, 80hout dx, al

mov cx, 200mov al, 1call stepmov cx, 200mov al, 0call stepmov ah, 4chint 21h

step proc near

mov dx, pccmp al, 1 je clkwise

mov al, 88hl1: out dx, al

call delayrol al, 1loop l1 jmp fwd

clkwise: mov al, 88hl2: out dx, alcall delayror al, 1loop l2

fwd: retstep endp

delay proc near push cx

mov cx, 2B68Hl3: loop l3 pop cxret

delay endp

end

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8086 Interfacing-chap 5