Memory Interface

Introduction• Simple or complex, every microprocessor-based system has

a memory system. • Almost all systems contain two main types of memory:

read-only memory (ROM) and random access memory (RAM) or read/write memory.

• This chapter explains how to interface both memory types to the Intel family of microprocessors.

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ObjectivesUpon completion of this chapter, you will be able to:

• Decode the memory address and use the outputs of the decoder to select various memory components.

• Explain how to interface both RAM and ROM to a microprocessor.

• Interface memory to an 8-, 16-bit data bus.• Interface dynamic RAM to the microprocessor.

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MEMORY DEVICES

• Before attempting to interface memory to the microprocessor, it is essential to understand the operation of memory components.

• In this section, we explain functions of thefour common types of memory:

– read-only memory (ROM) – Static random access memory (SRAM)

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Memory Pin Connections

– address inputs– data outputs or

input/outputs– some type of

selection input– at least one control

input to select a read or write operation

Figure   A pseudomemory component illustrating the address, data, and control connections

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Address Connections• Memory devices have address inputs to

select a memory location within the device. • Almost always labeled from A0, the least significant address

input, to An – where subscript n can be any value– always labeled as one less than total number

of address pins• A memory device with 10 address pins has

its address pins labeled from A0 to A9. • The number of address pins on a memory device is

determined by the number of memory locations found within it.

• Today, common memory devices have between 1K (1024) to 1G (1,073,741,824) memory locations.

– with 4G and larger devices on the horizon• A 1K memory device has ……. address pins.

– therefore, 10 address inputs are required toselect any of its 1024 memory locations

• It takes a 10-bit binary number to select any single location on a 1024-location device.

– 1024 different combinations– if a device has ….. address connections, it

has 2048 (2K) internal memory locations• The number of memory locations can be extrapolated from

the number of pins.

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Data Connections• All memory devices have a set of data outputs or

input/outputs.– today, many devices have bidirectional

common I/O pins– data connections are points at which data are entered

for storage or extracted for reading• Data pins on memory devices are labeled D0 through D7 for

an 8-bit-wide memory device. • An 8-bit-wide memory device is often called a byte-wide

memory. – most devices are currently 8 bits wide, – some are 16 bits, 4 bits, or just 1 bit wide

• Catalog listings of memory devices often refer to memory locations times bits per location.

– a memory device with 1K memory locationsand 8 bits in each location is often listed asa 1K ´ 8 by the manufacturer

• Memory devices are often classified according to total bit capacity.

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Selection Connections• Each memory device has an input that selects or enables the

memory device. – sometimes more than one

• This type of input is most often called a chip select (G2A) chip enable (CE) or simply select (S) input.

• RAM memory generally has at least one or input, and ROM has at least one

• If more than one CE connection is present,all must be activated to read or write data.

Control Connections• All memory devices have some form of control input or

inputs. – ROM usually has one control input, while RAM often

has one or two control inputs • Control input often found on ROM is the output enable or

gate connection, which allows data flow from output data pins.

• The OE connection enables and disables a set of three-state buffers located in the device and must be active to read data.

• RAM has either one or two control inputs. – if one control input, it is often called R/W

• If the RAM has two control inputs, they are usually labeled WE (or W ), and OE (or G ).

– write enable must be active to perform memory write, and OE active to perform a memory read

– when the two controls are present, they must never both be active at the same time

• If both inputs are inactive, data are neither written nor read.– the connections are at their high-impedance state

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ROM Memory• Read-only memory (ROM) permanently stores

programs/data resident to the system. – and must not change when power disconnected

• Often called nonvolatile memory, because its contents do not change even if power is disconnected.

• A device we call a ROM is purchased in mass quantities from a manufacturer.

– programmed during fabrication at the factory• The EPROM (erasable programmable read-only

memory) is commonly used when software must be changed often.

– or when low demand makes ROM uneconomical– for ROM to be practical at least 10,000 devices

must be sold to recoup factory charges • An EPROM is programmed in the field on a device

called an EPROM programmer.• Also erasable if exposed to high-intensity ultraviolet

light.– depending on the type of EPROM

• PROM memory devices are also available, although they are not as common today.

• The PROM (programmable read-only memory) is also programmed in the field by burning open tiny NI-chrome or silicon oxide fuses.

• Once it is programmed, it cannot be erased. • A newer type of read-mostly memory (RMM) is called

the flash memory. – also often called an EEPROM (electrically erasable

programmable ROM)– EAROM (electrically alterable ROM)– or a NOVRAM (nonvolatile RAM)

• Electrically erasable in the system, but they require more time to erase than normal RAM.

• The flash memory device is used to store setup information for systems such as the video card in the computer.

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• Flash has all but replaced the EPROM in most computer systems for the BIOS.

– some systems contain a password storedin the flash memory device

• Flash memory has its biggest impact in memory cards for digital cameras and memory in MP3 audio players.

• Figure 10–2 illustrates the 2716 EPROM, which is representative of most common EPROMs.

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– One important piece of information provided by the timing diagram and data sheet is the memory access time

– that is the time it takes the memory to read information

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Static RAM (SRAM) Devices• Static RAM memory devices retain data for as long as DC

power is applied. • Because no special action is required to retain data, these

devices are called static memory. – also called volatile memory because they will

not retain data without power• The main difference between ROM and RAM is that RAM

is written under normal operation, whereas ROM is programmed outside the computer and normally is only read.

FIGURE 7-8 Basic six-transistor static memory cell. (From J. Uffenbeck, Microcomputers and Microprocessors: The 8080, 8085, and Z-80. Prentice Hall, Englewood Cliffs, NJ, 1991.)

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• Fig 10–4 illustrates the 4016 SRAM, – a 2K ´ 8 read/write memory

• This device is representative of all SRAM devices.– except for the number of address and data connections.

• The control inputs of this RAM are slightly different from those presented earlier.

– however the control pins function exactly the same as those outlined previously

• Found under part numbers 2016 and 6116.

– SRAM is used when the size of the read/write memory is relatively small

– today, a small memory is less than 1M byte

Figure 10–4  The pin-out of the TMS4016, 2K ´ 8 static RAM (SRAM). (Courtesy of Texas Instruments Incorporated.)

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Dynamic RAM (DRAM) Memory

• Available up to 256M ´ 8 (2G bits). • DRAM is essentially the same as SRAM, except that it

retains data for only 2 or 4 mson an integrated capacitor.

••••••••••••••••••••••••••••FIGURE 7-9 Dynamic RAMs use an MOS transistor and capacitor as the basic storage cell. Particular cells are selected via a row and column address.

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•• After 2 or 4 ms, the contents of the DRAM must be

completely rewritten (refreshed).– because the capacitors, which store a logic 1

or logic 0, lose their charges• In DRAM, the entire contents are refreshed with 256 reads

in a 2- or 4-ms interval. – also occurs during a write, a read, or during a special

refresh cycle• DRAM requires so many address pins that manufacturers

multiplexed address inputs. • Figure 10–7 illustrates a 64K ´ 4 DRAM, the TMS4464,

which stores 256K bits of data. – note it contains only eight address inputs where

it should contain 16—the number required to address 64K memory locations

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SRAM Interface Examples

To interface means to connect in a compatible manner. When interfacing memory, all the three system buses – the address, control and data buses – are involved.

Interfacing the HM62864

FIGURE Specifications for the HM62864 64K x 8 SRAM.

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Interfacing the 8088 procesor

FIGURE 64K x 8 8088 SRAM interface. Only a single memory chip is required.

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ADDRESS DECODING• In order to attach a memory device to the microprocessor, it

is necessary to decode the address sent from the microprocessor.

• Decoding makes the memory function at a unique section or partition of the memory map.

• Without an address decoder, only one memory device can be connected to a microprocessor, which would make it virtually useless.

Why Decode Memory?• The 8088 has 20 address connections and the HM62864 has

16 connections.• The 8088 sends out a 20-bit memory address whenever it

reads or writes data. – because the HM62864 has only 16 address pins,

there is a mismatch that must be corrected• The decoder corrects the mismatch by decoding address pins

that do not connect to the memory component.

Simple NAND Gate Decoder• When the 64K ´ 8 SRAM is used, address connections A15–

A0 of 8088 are connected to address inputs A15–A0 of the SRAM.

– the remaining four address pins (A19–A16) are connected to a NAND gate decoder

• The decoder selects the SRAM from one of the 64K-byte sections of the 1M-byte memory system in the 8088 microprocessor.

• In this circuit a NAND gate decodes the memory address, as seen in the following figure.

• If the 20-bit binary address, decoded by the NAND gate, is written so that the leftmost nine bits are 1s and the rightmost 11 bits are don’t cares (X), the actual address range of the SRAM can be determined.

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– a don’t care is a logic 1 or a logic 0, whicheveris appropriate

• Because of the excessive cost of the NAND gate decoder and inverters often required, this option requires an alternate be found.

FIGURE Example of an address decoder for the 8088 memory interface in previous figure. The memory will be enabled only when A19-A16 = 1110.

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FIGURE Memory map for the 8088 interface and decoder. The 64K SRAM is mapped to the address range E0000H to EFFFFH.

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FIGURE Decoder to map the SRAM to the range C0000-CFFFFH.

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Interface between memory and 8086

Even and Odd Memory BanksTwo SRAMs are needed. One stores the even bytes and connects to D0-D7, the other stores the odd bytes and connects to D8-D15 .

FIGURE 128K x 8 8086 SRAM interface.

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The 3-to-8 Line Decoder (74LS138)

Figure The 74LS138 3-to-8 line decoder and function table.

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Sample Decoder Circuit

Figure  A circuit that uses eight 2764 EPROMs for a 8K ´ 8 section of memory in an 8088 microprocessor-based system. The addresses selected in this circuit are F0000H–FFFFFH

• The outputs of the decoder in the figure, are connected to eight different 2764 EPROM memory devices.

• The decoder selects eight 8K-byte blocks of memory for a total capacity of 64K bytes.

• This figure also illustrates the address range of each memory device and the common connections to the memory devices.

• all address connections from the 8088 are connected to this circuit. • the decoder’s outputs are connected to the CE inputs of the EPROMs, • the RD signal from the 8088 is connected to the OE inputs of the

EPROMs • In this circuit, a three-input NAND gate is connected to address bits A19–A17. • When all three address inputs are high, the output of this NAND gate goes low

and enables input G2B of the 74LS138. • Input G1 is connected directly to A16. • In order to enable this decoder, the first four address connections (A19–A16) must

all be high. • Address inputs C, B, and A connect to microprocessor address pins A15–A13. • These three address inputs determine which output pin goes low and which

EPROM is selected whenever 8088 outputs a memory address within this range to the memory system.

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Figure Separate bank decoders.( BLE is A0)

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The Dual 2-to-4 Line Decoder (74LS139)• Figure illustrates both the pin-out and the truth table for the

74LS139 dual 2-to-4line decoder.

• 74LS139 contains two separate 2-to-4 line decoders—each with its own address, enable, and output connections.

• A more complicated decoder using the 74LS139 decoder appears in the figure.

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Example

Draw an address map for the memory interface in Figure 7.17, assuming the decoder is as shown in Figure 7.18. From this map determine the range of addresses occupied by the memory interface,

Solution

The address map shows the range of addresses, in binary, that enable the memory interface. This is shown below.

Because A19-A16 must always equal 1110 (to chip-select the memory), the 64K RAM is effectively mapped to the address range E0000H-EFFFFH. This is shown in the 8088 memory map in Figure 7.19.

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As you can see by studying Figure 7.19, there are 16 different 64K blocks in the 8088's memory address space. By modifying the decoder, we can map the interface to any one of these 16 ranges.

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ExampleShow the decoder required to map the 64K memory interface in Figure 7.17 to the address range C0000H to CFFFFH.

Solution The circuit is shown in Figure 7.20. Only when address lines A19-A16 = 1100 will the memory interface be enabled.

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The decoder verifies that the high-order address lines match the address assigned to this circuit.

A0 and BHE are then used to enable the even (A0 = 0) or odd (BHE = 0) SRAM chip.

Both chips are enabled for a word access. Note that this implies that words must begin at an even memory

address (that is, an address with A0 = 0). Words that begin at an odd address will require two memory cycles:

one to access the odd byte, the second to access the even byte.

We can view the 20 address lines (and BHE control signal) output by the processor as follows:

Example

Assume the decoder in Figure 7.21 is a three-input NAND gate and determine the range of addresses occupied by this interface.

Solution

The starting and ending addresses are:

Start: 1110 0000 0000 0000 0000 ;E0000HEnd: 1111 1111 1111 1111 1111 ;FFFFFH

128K total bytes of memory are provided. The chip marked “even” stores the even bytes over this range; the chip marked “odd” stores the odd bytes over this range.

Isolated And Memory-Mapped I/O

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In the isolated I/O scheme, the IN and OUT instructions transfer data between the microprocessor’s accumulator and I/O device.In the memory-mapped I/O scheme, any instruction that references memory can accomplish the transfer.

Isolated I/O

Control signals IORD and IOWR indicate that the address present on the address bus is used to select an I/O device

Memory-Mapped I/O A Memory-Mapped I/O device is treated as a memory location in the memory map.

Any memory transfer instruction can be use to access the I/O device. A portion of the memory system is used as the I/O map.

1M x 8 64K x 8

I/O

Memory

I/O

Memory + I/O

00000

FFFFF

00000

FFFFF

FFFF

0000

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Basic Input and Output Interfaces

The basic input device is a set of three-state buffers. The basic output device is a set of data latches.

The Basic Input Interface. Three-state buffers are used to construct the 8-bit input port depicted

in Figure 11-3. The circuit of Figure 11-3 allows the microprocessor to read the

contents of the 8 switches that connect to any 8-bit section of the data bus when the select signal SEL becomes a logic 0.

When the microprocessor executes an IN instruction, the I/O port address is decoded to generate the logic 0 on SEL .

A low placed on the output control inputs (1G and 2G) of the 74ALS244 buffer causes the data input connections (A) to be connected to the data output (Y) connections.

If a high is placed on the output control inputs of the 74ALS244 buffer, the device enters the three-state high-impedance mode that effectively disconnects the switches from the data bus.

To interface 16 bits of data, the circuit in Figure 11-3 is doubled to include two 74ALS244 buffers that connect 16 bits of input data to the 16-bit data bus.

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The Basic Output Interface. The basic output interface receives data from the microprocessor and must usually hold it for some external device. It latches or flip-flops, like the buffers found in the input device, are often built into the I/0 device.

Figure 11-4 shows how eight simple light-emitting diodes (LEDs) connect to the microprocessor through a set of eight data latches.

The latch stores the number output by the microprocessor from the data bus so that the LEDs can be lit with any 8-bit binary number.

Latches are needed to hold the data because when the microprocessor executes an OUT instruction, the data are only present on the data bus for less than 1.0 s. Without a latch, the viewer would never see the LEDs illuminate.

When the OUT instruction executes, the data from AL or AX are transferred to the latch via the data bus. Here, the D inputs of a 74ALS374 octal latch are connected to the data bus to capture the output data and the Q outputs of the latch are attached to the LEDs. When a Q output becomes low, the LED lights.

Each time that the OUT instruction executes, the SEL signal to the latch activates, capturing the data output to the latch from any 8-bit section of the data bus.

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The data are held until the next OUT instruction executes. Thus, whenever the output instruction is executed in this circuit, the data from the AL register appear on the LEDs.

Designing a Parallel Input Port

The figure shows a 16-bit input port. Sixteen switches are used to simulate the input data. IC1 and IC2 decode the ( direct) port address on AB1-AB7. The

output of IC2 is the port select signal SEL30-31H. IC3a combines this signal with IORB to generate the device select pulse signal In 30-31H.

I/O must be divided into even- and odd-addressed ports. Data from the even ports is transferred via D0-D7 and D8-D15 are used to transfer data from the odd-addressed ports. As shown in the figure BHE and AB0 are combined with In 30-31H

to generate separate even- and odd-device select pulses.

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Example 8. 1

Write a procedure (subroutine) for the input port in Figure 8.2 to check if switches 13, 11, 3, or 2 are open. If the condition is met, return with CF = 1; if the condition is not met, return with CF=0.

Solution An open switch will present a logic 1 level on its input line. Thus, the problem becomes one of determining if any of bits 13, 11, 3, or 2 are logic 1s. This can be done with the instruction TEST AX,280CH. A nonzero result means that at least one of the bits is set. Figure 8.3 provides a listing for the program. The statement PUBLIC FIG8-3 will allow this routine to be linked by another calling program. This will be done in Example 8.4.

TITLE Fig. 8.3 ;Function: Test if bits 13, 11, 3 or 2 of ; the 16-bit data port are high.;Inputs: Status information from IPORT.;Outputs: CF=1 if condition TRUE, else CF=0.;Destroys: AX, flags. PUBLIC FIG8_3 IPORT EQU 30H ;Data input port CODE SEGMENT BYTE PUBLIC 'CODE'

ASSUME CS:CODE

FIG8_3 PROC NEAR

CLC ;Be sure CF=0IN AX,IPORT ;Sample dataTEST AX,0010100000001100B

;Test input dataJZ DONE ;No bits highSTC ;At least 1 bit high

DONE: RETFIG8_3 ENDP END

CODE

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Designing a Parallel Output Port

The hardware required for an output port is similar to that of an input port except that the DSP signal is used to strobe a latch instead of the tri-state buffers. The latch is required due to the short time that data is placed on the bus by the processor .The figure shows a design for an 8-bit output port mapped to address 30H. There are two ways of using this port:

OUT 30H,AL or OUT DX,AL, where DX = xx30H

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Example

Write a program that tests if any of the switches 13, 11, 3, or 2 in the input port of Fig. 8.1 are open. If the condition is met, output FFH to port 30H in Fig. 8.4. If the condition is not met, output 00 to this port. The program should cycle indefinitely.

Solution

We can take advantage of the procedure written in the previous example to test the input port. Depending on the condition of CF, FFH or 00 can then be output to port 9. Figure 8.4 is a listing of the program. FIG8-2 is declared as an external symbol, so that this routine can be linked to the program in Fig. 8.4 without having to rewrite that procedure's code.

TITLE Fig. 8.5

;This program calls the routine in Fig. 8.3.;If switches 13, 11, 3 or 2 are open, FFH is;output to OPORT, else 00 is output.;Note: To build this program specify Chap8.Lib;under Link Options - Additional Global Libraries. EXTRN FIG8_3:NEAR

OPORT EQU 30H ;Output port CODE SEGMENT 'CODE'

ASSUME CS:CODE START: MOV BL,0FFH ;Open switches code is FF

CALL FIG8_3 ;Test switches JC SET ;Condition met MOV BL,0 ;Condition not met code is 00

SET: MOV AL,BL ;Code to AL OUT OPORT,AL ;Program the port JMP START ;Monitor continuously

CODE ENDS END START

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Applications for the Device Select Pulse

Normally the DSP signal is used to enable a latch or set of tri-state gates. However, in some cases the pulse alone is sufficient. Figure 8.5 provides an example. Using the IN 30H and OUT 30H DSP signals from the decoder in Fig. 8.1 and Fig.8.4, this circuit controls a mechanical relay.

An IN AL,30H instruction resets the fIip-flop and turns on the transistor. This, in turn, allows current to flow through the relay coil. The normally open (NO) contact closes and some external (non- TTL-compatible) device can be turned on.

An OUT 30H,AL instruction turns the relay off.The 74LS05 is an open-collector buffer. This allows its output to be pulled to + 5 V and the transistor base drive to be supplied through the pull-up resistor. Transistor Ql is required because the relay's ON current exceeds the sink capability of the 74LS05.

A similar application for the DSP is to trigger a one-shot to generate pulse widths of a particular length. Be sure to note that it is only the DSP that is used. No data is transferred. For this reason the contents of register AL is a “don't care” , when an output instruction is executed, and indeterminate when an input instruction is executed.

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