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Ajit Pal

ProfessorDepartment of Computer Science and Engineering

Indian Institute of Technology Kharagpur

INDIA-721302

Microcontrollers: The 8051Family

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Architecture of the Intel 8051

On

chip oscillator and CPU Timing

Memory Organization

Register Organization

Multifunction I/O ports

ALU capability of 8051

Reset Operation

Interrupt structure

The 8051 Family

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Key Features of 8051

8-bit CPU

On-chip oscillatorHarvard architecture4 KB of on-chip ROM128 bytes of on-chip RAM21 special function registers

32 I/O lines64 KB address space for external Program

memory64 KB address space for external Data memoryTwo 16-bit timer/counters

One full-duplex serial portFive-source interrupt structure with two priority

levelsBit addressability for Boolean processing

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Simplified Block Diagram of 8051

INTERRUPT

CONTROL

128 BYTES

RAM

4K

ROM

CPU

TIMER 1

TIMER 0

OSCBUS

CONTROL4 I/O PORTS

SERIAL

PORT

EXTERNAL

INTERRUPTS

COUNTER

INPUTS

P0 P2 P1 P3

ADDRESS / DATA

TXD RXD

INTERNAL

INTERRUPTS

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Ajit Pal, IIT Kharagpur

Onchip oscillator and CPU Timing

30pF

30pF

1.24 to

12 MHz.

XTAL2

XTAL1

XTAL2

XTAL1

External

clock

generator

p1 p2 p1 p2 p1 p2 p2 p2 p2 p2p1 p1 p1 p1

S1 S2 S3 S4 S5 S6 S1 S2

p1 p2

Machine cycle

Clock

Phases

States

Machine cycle

ALE

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8051 Memory Map

EXTERNAL

INTERNAL

ROM

EXTERNAL

ROM

0000

0FFF

1000

FFFF

INTERNAL

DATA RAM

SFR

EXTERNAL

DATA RAM

00

7F

80

FF

0000

FFFF

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Register Organization of 8051

General purpose registers

4 banks of 8-registers

Twenty one Special function registers

A , B , DPL, DPH, IE , IP , P0 , P1 , P2 ,

P3 , PCON, PSW, SCON, SBUF, SP,

TMOD, TCON, TL0, TH0, TL1, TH1

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NAME Function RAM

ADDRESS

SCON* Serial Port 98

SBUF Serial Data

Buffer.

99

SP Stack Pointer 81

TMOD T/C Mode

Control

89

TCON* T/C Control 88

TL0 Timer 0 Lower

order byte

8A

TH0 Timer 0 Higher

order byte

8C

TL1 Timer 1 Lower

order byte

8B

TH1 Timer 1 Higher

order byte

8D

NAME Function RAM

ADDRESS

A* Accumulator E0

B* Arithmetic F0

DPH External Memory

Address.

83

DPL External memory

Address.

82

IE* Interrupt Enable A8

IP* Interrupt Priority

Control

B8

P0* I/O Port 80

P1* I/O Port 90

P2* I/O Port A0

P3* I/O Port B0

PCON Power Control 87

PSW Program Status

Word

D0

Special Function Register of 8051

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Program Status Word

BITS:

CY AY F0 RS1 RS0 OV P

7

Carry

Auxiliary-Carry

User Flag

0

0 0

0 1

1 0

1 1

Bank 0

Bank 1

Bank 2

Bank 3

OverflowReserved

Parity: 0-even1-odd

-

123456

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Interrupt Structure of 8051

5 interrupts apart from RESET

Interrupts can be individually enabled/disabledEach source can be programmed to two priority

levels

INTERRUPTS FUNCTIONS VECTOR ADDRESS

INTO External Interrupt 0003H

on PIN P3.2

TIMER0 Overflow of Timer0 000BH

activates TF0

INT1 External interrupt 0013H

on PIN P3.3

TIMER1 Overflow of Timer1 001BH

activates TF1

SERIAL Completion of 0023H

transmission/reception

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Ports of 8051

P0

While accessing external memory provides

lower order byte of address (A0-A7)

Otherwise acts as normal port line

READ

LATCH

LATCH

P0.XINT.BUS D Q

CL Q

WRITE

TO

LATCH

READ

PIN

MUX

ADDR / DATA

CONTROLV

CC

P0.X

PIN

Q1

Q2

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VCC

High for two

Oscillator period

Week depletion

mode FET

READLATCH

LATCH

P1.XINT.BUS D Q

CL QWRITE

TO

LATCH

READ

PIN

VCCINTERNAL

PULL-UP*

P1.X

PIN

Q1

Ports of 8051

P1: Port 1 has no dual function. It is simplyused as programmable bi-directional I/O Port.

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Ports of 8051

P2:

While accessing external memory provides

higher order byte of address (A8-A15)

Otherwise acts as normal port line

READ

LATCH

LATCHP2.X

INT.BUS D Q

CL QWRITE

TO

LATCH

READ

PIN

MUX

ADDR CONTROL

P2.X

PIN

VCC

*

INTERNAL

PULL-UP

Q1

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Ports of 8051

READ

LATCH

LATCH

P3.XINT.BUS D Q

CL QWRITE

TO

LATCH

READ

PIN

P3.X

PIN

VCC

*

ALTERNATE

OUTPUT

FUNCTION

ALTERNATE

INPUT

FUNCTION

INTERNAL

PULL-UP

Q1

Port Pin Name Alternate

Function

P3.0 RXD Serial input

port

P3.1 TXD Serial output

port

P3.2 INT0 External

interrupt

P3.3 INT1 External

interrupt

P3.4 T0 Timer 0

external input

P3.5 T1 Timer 1

external input

P3.6 WR External Data

memory write

store

P3.7 RD External Data

memory Read

store

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Reset Operation Of 8051

By holding RST pin high for twomachine cycles

On reset the registers have thefollowing contents:

PC, A, B, PSW, DPTR, TMOD,TCON, TH0, TL0, TH1, TL1 allare initialized to zero.

SP 07H, P0 P3 0FFH, IP xxx00000,

IE 0xx00000, PCON -0xxxxxxx, SBUF xxxxxxxx.

Register Content

PC 0000H

A 00H

B 00H

PSW 00H

SP 07H

DPTR 0000H

P0-P3 0FFH

IP (XXX00000)

IE (0XX00000)

TMOD 00H

TCOM 00H

THO 00H

TH1 00H

TL1 00H

SCOM 00H

SBUF Indeterminate

PCON (0XXXXXXX)

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Ajit Pal, IIT Kharagpur

8051 Family

FEATURE 8051 8031 8751 8052 AT89C51 DS500-8ROM 4K 0K EPROM

4K 8K FLASH 4K NVRAM 8KRAM 128 128 128 256 128 128I/O 32 32 32 32 32 32

Serial I/O 1 1 1 1 1 1Timer 2 2 2 3 2 2

Interrupt

Sources 6 6 6 8 6 6

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Low Power Features ATMEL microprocessors provide several power

saving options, which can be used to reduce powerdissipation of the processor for battery operatedsystems

The operating frequency of ATMEL 89C51 is from 0to 24 MHz. Since P V2 dd.f, low-power circuits can

be realized in applications where high performanceis not required

The processor can also be put to sleep, but the on-chip peripherals remain in the active state

One can invoke the idle mode by software meanssimply by setting the IDLE bit of the PCON specialfunction register

The IDLE bit of PECON register is cleared, whichterminates the IDLE mode

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Applications

Household

items

Office Equipment Communication

Toys FAX machines Cordless phones

TVs Printers Cellular phones

Microwave oven Plotters Pagers

Washing Machine Mouse Answering

machine

Garage door

openerSmart cards

Home securingsystem

Vacuum cleaner

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Ajit Pal, IIT Kharagpur

Thanks!