8051-based Processor Interfacing

Memory System Design

Design alternatives for 8051 microcontroller

1. Internal program memory and external data memory. This configuration is suitable for applications that will be produced in large quantities and need more data memory that can be satisfied by the internal one.

2. External program and data memories. This configuration is suitable for any application that is still in prototype phase or building evaluation boards for the microcontroller. The external program will use EPROM because the program may need to be revised many times. An evaluation board also use SRAM for external program memory so that dynamic programs can be downloaded for execution.

3. Internal program memory and external program and data memories. This configuration probably will be used only in microcontroller evaluation boards in which the monitor program resides in the internal PROM and the user program needs to be downloaded into external program memory for execution. The external program and data memories can be combined.

4. Internal program and data memories. This configuration will be the ideal choice if the program and data storage requirements can be satisfied by internal program and data memories. This configuration will have the smallest size among all possible memory configurations.

Example 1. Add a CY7C199 32KB SRAM to the Atmel89C51 microcontroller operated with as 12MHz crystal. Wire the SRAM so that only 8 KB will be accessed (or made available to the microcontroller). Include a 74F138 3 x 8 decoder as an address decoder. Assign the address space 0000 – 1FFFH to this SRAM chip. Draw the system circuit diagram.

Example 2. Verify that the read access timing parameters are satisfied in the circuit diagram of Example 1.

Solution: The timing analysis is performed as follows:

1. Address latch timing requirement. The address latch 74LS373 requires that the data inputs D7-D0 be valid for 18 ns before ALE goes low. The microcontroller outputs the address AD7-AD0 43 ns before ALE low (TAVLL - Address Valid to ALE Low= 43 ns) and maintain this data for 48 ns (TLLAX - Address Hold after ALE Low). Address is available at the output of the latch 30 ns after ALE goes low.

2. Read Access timing requirement. The 89C51 requires that the read data be valid no more than 517 ns (TLLDV) after the ALE goes low. The read data must remain valid 0 ns (TRHDX

= Data Hold after RD) after the RD* signal goes high.

The CY7C199 32KB SRAM data output timing is determined by the following signals:• CE. This signal is connected to output 0 of the decoder. This signal becomes valid

30 ns after the falling edge of ALE.• A12-A8are valid 43 ns before the falling edge of ALE whereas A7 – A0 become

valid 30 ns after ALE goes low. • RD. This signal becomes valid between 200 and 300 ns after the falling edge of the

ALE signal. (tLLWL = ALE Low to RD or WR Low) • Since the RD signal is used as the OE input for the SRAM determines the actual

access time. Data from SRAM becomes valid (tLLWL + OE: ALE Low to RD or WR Low + OE)

ALE low to Valid Data In (T LLDV) requirement. From previous analysis, RD is the latest signal that is asserted and hence determines when data from SRAM become valid. Since RD becomes valid 200 – 300 ns after falling edge of ELE and the SRAM CY7C199 - 12 has access time TOE that equals to 5 ns, the actual value of TLLDV is 205-305 ns and is smaller than the value 517 ns (worst case).

RD low to Valid Data In (TRLDV) Requirement. The 12 MHZ 89C51 microcontroller requires external data to be valid no later than 252 ns after the falling edge of RD. The actual value is 5 ns after the falling edge of RD and satisfies the requirement.

Address to Valid Data In (TAVDV) Requirement. . This parameter is equal to the sum of TAVLL and TLLDV. Since TAVLL is 43 ns the actual value of TAVDV will be 200 + 43+5 = 248 to 300+48=348. The 12 MHZ 89C51 microcontroller requires TAVDV to be no larger than 585 ns, the requirement is satisfied.

Data Hold After RD (TRHDX) Requirement. The 12 MHZ 89C51 microcontroller requires external data to hold for 0 ns after OE (RD) becomes invalid. The data output from the 89C51 will become invalid after 35 ns after OE goes high. Therefore, the read data hold time requirement is satisfied.

Summary of Read Cycle Timing Requirement VerificationsTiming Parameter Required Value (ns) Actual Value (ns)T RHDX 0 (min) 5 ns (SRAM data)T LLDV 517 (max) 205-305T RLDV 252 (max) 5 T AVDV 585 (max) 248 - 348

Example 3. Verify that all write timing requirements are satisfied in the system diagram in Example 1.

Solution. The following SRAM timing parameters must be satisfied:• Write cycle time (T WC)• Chip select to end of write (T CW)• Address setup time ( T AS)• Write time (T W)• Address valid to end of write (T AW)• Data setup time (T DS)• Data Hold time (T DH)• Write recovery time (T WR)

Write cycle time (T WC) Requirement. Defined as the period in a write access during which the address inputs are valid.

= T LLWL + T WLWH – delay of 74LS373 + TWHLH + the width of ALE – T AVLL

Chip select to end of write (T CW) Requirement

= T LLWL + T WLWH – address decoder delay

Address setup time ( T AS) Requirement

= smallest TLLWL – 43 ns = 200 ns – 43 ns = 157 ns

since T AS = 0 ns for this SRAM, the requirement is satisfied

Write time (T W) Requirement. SRAM requires that the write pulse width is at least 60 ns.

For the SRAM, T W = 60 ns. Since the microcontroller asserts this signal for 400 ns, the requirment is satisfied.

Address valid to end of write (T AW) Requirement. This parameter is measured from the moment that all address inputs to SRAM become valid until the moment that the WE signal rises to high.

= T LLWL + T WLWH – address valid delay relative to the falling edge of ALE= 200~300 ns + 400 ns – 43 ns

Data Setup Time (T DS) requirement. SRAM requirement for data setup time.

Data Hold Time (T DH) requirement. SRAM hold time requirement.

Write Recovery Time (T WR) Requirement. Write recovery time is the time delay from the moment that the write-enable signal (WE) becomes invalid until the moment that the address signals become invalid.

Write recovery time = T WHLH + T LHLL - T AVLL

Write Timing Analysis SummaryParameter required value actual valueWrite cycle time (T WC)Chip select to end of write (T CW)Address setup time ( T AS)Write time (T W)Address valid to end of write (T AW)Data setup time (T DS)Data Hold time (T DH)Write recovery time (T WR)